1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac XGMAC support. 5 */ 6 7 #include <linux/iopoll.h> 8 #include "stmmac.h" 9 #include "dwxgmac2.h" 10 11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) 12 { 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); 14 15 /* DMA SW reset */ 16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); 17 18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, 19 !(value & XGMAC_SWR), 0, 100000); 20 } 21 22 static void dwxgmac2_dma_init(void __iomem *ioaddr, 23 struct stmmac_dma_cfg *dma_cfg, int atds) 24 { 25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 26 27 if (dma_cfg->aal) 28 value |= XGMAC_AAL; 29 30 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 31 } 32 33 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, 34 struct stmmac_dma_cfg *dma_cfg, u32 chan) 35 { 36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 37 38 if (dma_cfg->pblx8) 39 value |= XGMAC_PBLx8; 40 41 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 42 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 43 } 44 45 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, 46 struct stmmac_dma_cfg *dma_cfg, 47 u32 dma_rx_phy, u32 chan) 48 { 49 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 50 u32 value; 51 52 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 53 value &= ~XGMAC_RxPBL; 54 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; 55 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 56 57 writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); 58 } 59 60 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr, 61 struct stmmac_dma_cfg *dma_cfg, 62 u32 dma_tx_phy, u32 chan) 63 { 64 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 65 u32 value; 66 67 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 68 value &= ~XGMAC_TxPBL; 69 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL; 70 value |= XGMAC_OSP; 71 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 72 73 writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); 74 } 75 76 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 77 { 78 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 79 int i; 80 81 if (axi->axi_lpi_en) 82 value |= XGMAC_EN_LPI; 83 if (axi->axi_xit_frm) 84 value |= XGMAC_LPI_XIT_PKT; 85 86 value &= ~XGMAC_WR_OSR_LMT; 87 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) & 88 XGMAC_WR_OSR_LMT; 89 90 value &= ~XGMAC_RD_OSR_LMT; 91 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) & 92 XGMAC_RD_OSR_LMT; 93 94 value &= ~XGMAC_BLEN; 95 for (i = 0; i < AXI_BLEN; i++) { 96 if (axi->axi_blen[i]) 97 value &= ~XGMAC_UNDEF; 98 99 switch (axi->axi_blen[i]) { 100 case 256: 101 value |= XGMAC_BLEN256; 102 break; 103 case 128: 104 value |= XGMAC_BLEN128; 105 break; 106 case 64: 107 value |= XGMAC_BLEN64; 108 break; 109 case 32: 110 value |= XGMAC_BLEN32; 111 break; 112 case 16: 113 value |= XGMAC_BLEN16; 114 break; 115 case 8: 116 value |= XGMAC_BLEN8; 117 break; 118 case 4: 119 value |= XGMAC_BLEN4; 120 break; 121 } 122 } 123 124 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 125 } 126 127 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, 128 u32 channel, int fifosz, u8 qmode) 129 { 130 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); 131 unsigned int rqs = fifosz / 256 - 1; 132 133 if (mode == SF_DMA_MODE) { 134 value |= XGMAC_RSF; 135 } else { 136 value &= ~XGMAC_RSF; 137 value &= ~XGMAC_RTC; 138 139 if (mode <= 64) 140 value |= 0x0 << XGMAC_RTC_SHIFT; 141 else if (mode <= 96) 142 value |= 0x2 << XGMAC_RTC_SHIFT; 143 else 144 value |= 0x3 << XGMAC_RTC_SHIFT; 145 } 146 147 value &= ~XGMAC_RQS; 148 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; 149 150 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); 151 152 /* Enable MTL RX overflow */ 153 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); 154 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); 155 } 156 157 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode, 158 u32 channel, int fifosz, u8 qmode) 159 { 160 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 161 unsigned int tqs = fifosz / 256 - 1; 162 163 if (mode == SF_DMA_MODE) { 164 value |= XGMAC_TSF; 165 } else { 166 value &= ~XGMAC_TSF; 167 value &= ~XGMAC_TTC; 168 169 if (mode <= 64) 170 value |= 0x0 << XGMAC_TTC_SHIFT; 171 else if (mode <= 96) 172 value |= 0x2 << XGMAC_TTC_SHIFT; 173 else if (mode <= 128) 174 value |= 0x3 << XGMAC_TTC_SHIFT; 175 else if (mode <= 192) 176 value |= 0x4 << XGMAC_TTC_SHIFT; 177 else if (mode <= 256) 178 value |= 0x5 << XGMAC_TTC_SHIFT; 179 else if (mode <= 384) 180 value |= 0x6 << XGMAC_TTC_SHIFT; 181 else 182 value |= 0x7 << XGMAC_TTC_SHIFT; 183 } 184 185 /* Use static TC to Queue mapping */ 186 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP; 187 188 value &= ~XGMAC_TXQEN; 189 if (qmode != MTL_QUEUE_AVB) 190 value |= 0x2 << XGMAC_TXQEN_SHIFT; 191 else 192 value |= 0x1 << XGMAC_TXQEN_SHIFT; 193 194 value &= ~XGMAC_TQS; 195 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS; 196 197 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 198 } 199 200 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan) 201 { 202 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 203 } 204 205 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan) 206 { 207 writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 208 } 209 210 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan) 211 { 212 u32 value; 213 214 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 215 value |= XGMAC_TXST; 216 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 217 218 value = readl(ioaddr + XGMAC_TX_CONFIG); 219 value |= XGMAC_CONFIG_TE; 220 writel(value, ioaddr + XGMAC_TX_CONFIG); 221 } 222 223 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan) 224 { 225 u32 value; 226 227 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 228 value &= ~XGMAC_TXST; 229 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 230 231 value = readl(ioaddr + XGMAC_TX_CONFIG); 232 value &= ~XGMAC_CONFIG_TE; 233 writel(value, ioaddr + XGMAC_TX_CONFIG); 234 } 235 236 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan) 237 { 238 u32 value; 239 240 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 241 value |= XGMAC_RXST; 242 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 243 244 value = readl(ioaddr + XGMAC_RX_CONFIG); 245 value |= XGMAC_CONFIG_RE; 246 writel(value, ioaddr + XGMAC_RX_CONFIG); 247 } 248 249 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan) 250 { 251 u32 value; 252 253 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 254 value &= ~XGMAC_RXST; 255 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 256 257 value = readl(ioaddr + XGMAC_RX_CONFIG); 258 value &= ~XGMAC_CONFIG_RE; 259 writel(value, ioaddr + XGMAC_RX_CONFIG); 260 } 261 262 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr, 263 struct stmmac_extra_stats *x, u32 chan) 264 { 265 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan)); 266 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 267 int ret = 0; 268 269 /* ABNORMAL interrupts */ 270 if (unlikely(intr_status & XGMAC_AIS)) { 271 if (unlikely(intr_status & XGMAC_TPS)) { 272 x->tx_process_stopped_irq++; 273 ret |= tx_hard_error; 274 } 275 if (unlikely(intr_status & XGMAC_FBE)) { 276 x->fatal_bus_error_irq++; 277 ret |= tx_hard_error; 278 } 279 } 280 281 /* TX/RX NORMAL interrupts */ 282 if (likely(intr_status & XGMAC_NIS)) { 283 x->normal_irq_n++; 284 285 if (likely(intr_status & XGMAC_RI)) { 286 x->rx_normal_irq_n++; 287 ret |= handle_rx; 288 } 289 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { 290 x->tx_normal_irq_n++; 291 ret |= handle_tx; 292 } 293 } 294 295 /* Clear interrupts */ 296 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); 297 298 return ret; 299 } 300 301 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr, 302 struct dma_features *dma_cap) 303 { 304 u32 hw_cap; 305 306 /* MAC HW feature 0 */ 307 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0); 308 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16; 309 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14; 310 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12; 311 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11; 312 dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10; 313 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7; 314 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6; 315 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; 316 317 /* MAC HW feature 1 */ 318 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1); 319 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18; 320 dma_cap->tx_fifo_size = 321 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6); 322 dma_cap->rx_fifo_size = 323 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0); 324 325 /* MAC HW feature 2 */ 326 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2); 327 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24; 328 dma_cap->number_tx_channel = 329 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1; 330 dma_cap->number_rx_channel = 331 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1; 332 dma_cap->number_tx_queues = 333 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1; 334 dma_cap->number_rx_queues = 335 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1; 336 } 337 338 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan) 339 { 340 u32 i; 341 342 for (i = 0; i < nchan; i++) 343 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i)); 344 } 345 346 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 347 { 348 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan)); 349 } 350 351 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 352 { 353 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan)); 354 } 355 356 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) 357 { 358 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan)); 359 } 360 361 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) 362 { 363 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan)); 364 } 365 366 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 367 { 368 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 369 370 if (en) 371 value |= XGMAC_TSE; 372 else 373 value &= ~XGMAC_TSE; 374 375 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 376 } 377 378 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 379 { 380 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 381 382 value &= ~XGMAC_TXQEN; 383 if (qmode != MTL_QUEUE_AVB) { 384 value |= 0x2 << XGMAC_TXQEN_SHIFT; 385 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel)); 386 } else { 387 value |= 0x1 << XGMAC_TXQEN_SHIFT; 388 } 389 390 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 391 } 392 393 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 394 { 395 u32 value; 396 397 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 398 value |= bfsize << 1; 399 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 400 } 401 402 const struct stmmac_dma_ops dwxgmac210_dma_ops = { 403 .reset = dwxgmac2_dma_reset, 404 .init = dwxgmac2_dma_init, 405 .init_chan = dwxgmac2_dma_init_chan, 406 .init_rx_chan = dwxgmac2_dma_init_rx_chan, 407 .init_tx_chan = dwxgmac2_dma_init_tx_chan, 408 .axi = dwxgmac2_dma_axi, 409 .dump_regs = NULL, 410 .dma_rx_mode = dwxgmac2_dma_rx_mode, 411 .dma_tx_mode = dwxgmac2_dma_tx_mode, 412 .enable_dma_irq = dwxgmac2_enable_dma_irq, 413 .disable_dma_irq = dwxgmac2_disable_dma_irq, 414 .start_tx = dwxgmac2_dma_start_tx, 415 .stop_tx = dwxgmac2_dma_stop_tx, 416 .start_rx = dwxgmac2_dma_start_rx, 417 .stop_rx = dwxgmac2_dma_stop_rx, 418 .dma_interrupt = dwxgmac2_dma_interrupt, 419 .get_hw_feature = dwxgmac2_get_hw_feature, 420 .rx_watchdog = dwxgmac2_rx_watchdog, 421 .set_rx_ring_len = dwxgmac2_set_rx_ring_len, 422 .set_tx_ring_len = dwxgmac2_set_tx_ring_len, 423 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr, 424 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr, 425 .enable_tso = dwxgmac2_enable_tso, 426 .qmode = dwxgmac2_qmode, 427 .set_bfsize = dwxgmac2_set_bfsize, 428 }; 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