1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac XGMAC support. 5 */ 6 7 #include <linux/iopoll.h> 8 #include "stmmac.h" 9 #include "dwxgmac2.h" 10 11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) 12 { 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); 14 15 /* DMA SW reset */ 16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); 17 18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, 19 !(value & XGMAC_SWR), 0, 100000); 20 } 21 22 static void dwxgmac2_dma_init(void __iomem *ioaddr, 23 struct stmmac_dma_cfg *dma_cfg, int atds) 24 { 25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 26 27 if (dma_cfg->aal) 28 value |= XGMAC_AAL; 29 30 writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE); 31 } 32 33 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, 34 struct stmmac_dma_cfg *dma_cfg, u32 chan) 35 { 36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 37 38 if (dma_cfg->pblx8) 39 value |= XGMAC_PBLx8; 40 41 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 42 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 43 } 44 45 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, 46 struct stmmac_dma_cfg *dma_cfg, 47 dma_addr_t phy, u32 chan) 48 { 49 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 50 u32 value; 51 52 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 53 value &= ~XGMAC_RxPBL; 54 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL; 55 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 56 57 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); 58 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); 59 } 60 61 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr, 62 struct stmmac_dma_cfg *dma_cfg, 63 dma_addr_t phy, u32 chan) 64 { 65 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 66 u32 value; 67 68 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 69 value &= ~XGMAC_TxPBL; 70 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL; 71 value |= XGMAC_OSP; 72 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 73 74 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); 75 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); 76 } 77 78 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 79 { 80 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); 81 int i; 82 83 if (axi->axi_lpi_en) 84 value |= XGMAC_EN_LPI; 85 if (axi->axi_xit_frm) 86 value |= XGMAC_LPI_XIT_PKT; 87 88 value &= ~XGMAC_WR_OSR_LMT; 89 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) & 90 XGMAC_WR_OSR_LMT; 91 92 value &= ~XGMAC_RD_OSR_LMT; 93 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) & 94 XGMAC_RD_OSR_LMT; 95 96 if (!axi->axi_fb) 97 value |= XGMAC_UNDEF; 98 99 value &= ~XGMAC_BLEN; 100 for (i = 0; i < AXI_BLEN; i++) { 101 switch (axi->axi_blen[i]) { 102 case 256: 103 value |= XGMAC_BLEN256; 104 break; 105 case 128: 106 value |= XGMAC_BLEN128; 107 break; 108 case 64: 109 value |= XGMAC_BLEN64; 110 break; 111 case 32: 112 value |= XGMAC_BLEN32; 113 break; 114 case 16: 115 value |= XGMAC_BLEN16; 116 break; 117 case 8: 118 value |= XGMAC_BLEN8; 119 break; 120 case 4: 121 value |= XGMAC_BLEN4; 122 break; 123 } 124 } 125 126 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); 127 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL); 128 writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL); 129 } 130 131 static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space) 132 { 133 int i; 134 135 for (i = (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++) 136 reg_space[i] = readl(ioaddr + i * 4); 137 } 138 139 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, 140 u32 channel, int fifosz, u8 qmode) 141 { 142 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); 143 unsigned int rqs = fifosz / 256 - 1; 144 145 if (mode == SF_DMA_MODE) { 146 value |= XGMAC_RSF; 147 } else { 148 value &= ~XGMAC_RSF; 149 value &= ~XGMAC_RTC; 150 151 if (mode <= 64) 152 value |= 0x0 << XGMAC_RTC_SHIFT; 153 else if (mode <= 96) 154 value |= 0x2 << XGMAC_RTC_SHIFT; 155 else 156 value |= 0x3 << XGMAC_RTC_SHIFT; 157 } 158 159 value &= ~XGMAC_RQS; 160 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS; 161 162 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 163 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); 164 unsigned int rfd, rfa; 165 166 value |= XGMAC_EHFC; 167 168 /* Set Threshold for Activating Flow Control to min 2 frames, 169 * i.e. 1500 * 2 = 3000 bytes. 170 * 171 * Set Threshold for Deactivating Flow Control to min 1 frame, 172 * i.e. 1500 bytes. 173 */ 174 switch (fifosz) { 175 case 4096: 176 /* This violates the above formula because of FIFO size 177 * limit therefore overflow may occur in spite of this. 178 */ 179 rfd = 0x03; /* Full-2.5K */ 180 rfa = 0x01; /* Full-1.5K */ 181 break; 182 183 case 8192: 184 rfd = 0x06; /* Full-4K */ 185 rfa = 0x0a; /* Full-6K */ 186 break; 187 188 case 16384: 189 rfd = 0x06; /* Full-4K */ 190 rfa = 0x12; /* Full-10K */ 191 break; 192 193 default: 194 rfd = 0x06; /* Full-4K */ 195 rfa = 0x1e; /* Full-16K */ 196 break; 197 } 198 199 flow &= ~XGMAC_RFD; 200 flow |= rfd << XGMAC_RFD_SHIFT; 201 202 flow &= ~XGMAC_RFA; 203 flow |= rfa << XGMAC_RFA_SHIFT; 204 205 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); 206 } 207 208 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); 209 210 /* Enable MTL RX overflow */ 211 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); 212 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); 213 } 214 215 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode, 216 u32 channel, int fifosz, u8 qmode) 217 { 218 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 219 unsigned int tqs = fifosz / 256 - 1; 220 221 if (mode == SF_DMA_MODE) { 222 value |= XGMAC_TSF; 223 } else { 224 value &= ~XGMAC_TSF; 225 value &= ~XGMAC_TTC; 226 227 if (mode <= 64) 228 value |= 0x0 << XGMAC_TTC_SHIFT; 229 else if (mode <= 96) 230 value |= 0x2 << XGMAC_TTC_SHIFT; 231 else if (mode <= 128) 232 value |= 0x3 << XGMAC_TTC_SHIFT; 233 else if (mode <= 192) 234 value |= 0x4 << XGMAC_TTC_SHIFT; 235 else if (mode <= 256) 236 value |= 0x5 << XGMAC_TTC_SHIFT; 237 else if (mode <= 384) 238 value |= 0x6 << XGMAC_TTC_SHIFT; 239 else 240 value |= 0x7 << XGMAC_TTC_SHIFT; 241 } 242 243 /* Use static TC to Queue mapping */ 244 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP; 245 246 value &= ~XGMAC_TXQEN; 247 if (qmode != MTL_QUEUE_AVB) 248 value |= 0x2 << XGMAC_TXQEN_SHIFT; 249 else 250 value |= 0x1 << XGMAC_TXQEN_SHIFT; 251 252 value &= ~XGMAC_TQS; 253 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS; 254 255 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 256 } 257 258 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan) 259 { 260 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 261 } 262 263 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan) 264 { 265 writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 266 } 267 268 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan) 269 { 270 u32 value; 271 272 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 273 value |= XGMAC_TXST; 274 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 275 276 value = readl(ioaddr + XGMAC_TX_CONFIG); 277 value |= XGMAC_CONFIG_TE; 278 writel(value, ioaddr + XGMAC_TX_CONFIG); 279 } 280 281 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan) 282 { 283 u32 value; 284 285 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 286 value &= ~XGMAC_TXST; 287 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 288 289 value = readl(ioaddr + XGMAC_TX_CONFIG); 290 value &= ~XGMAC_CONFIG_TE; 291 writel(value, ioaddr + XGMAC_TX_CONFIG); 292 } 293 294 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan) 295 { 296 u32 value; 297 298 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 299 value |= XGMAC_RXST; 300 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 301 302 value = readl(ioaddr + XGMAC_RX_CONFIG); 303 value |= XGMAC_CONFIG_RE; 304 writel(value, ioaddr + XGMAC_RX_CONFIG); 305 } 306 307 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan) 308 { 309 u32 value; 310 311 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 312 value &= ~XGMAC_RXST; 313 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 314 } 315 316 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr, 317 struct stmmac_extra_stats *x, u32 chan) 318 { 319 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan)); 320 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); 321 int ret = 0; 322 323 /* ABNORMAL interrupts */ 324 if (unlikely(intr_status & XGMAC_AIS)) { 325 if (unlikely(intr_status & XGMAC_RBU)) { 326 x->rx_buf_unav_irq++; 327 ret |= handle_rx; 328 } 329 if (unlikely(intr_status & XGMAC_TPS)) { 330 x->tx_process_stopped_irq++; 331 ret |= tx_hard_error; 332 } 333 if (unlikely(intr_status & XGMAC_FBE)) { 334 x->fatal_bus_error_irq++; 335 ret |= tx_hard_error; 336 } 337 } 338 339 /* TX/RX NORMAL interrupts */ 340 if (likely(intr_status & XGMAC_NIS)) { 341 x->normal_irq_n++; 342 343 if (likely(intr_status & XGMAC_RI)) { 344 x->rx_normal_irq_n++; 345 ret |= handle_rx; 346 } 347 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { 348 x->tx_normal_irq_n++; 349 ret |= handle_tx; 350 } 351 } 352 353 /* Clear interrupts */ 354 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); 355 356 return ret; 357 } 358 359 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr, 360 struct dma_features *dma_cap) 361 { 362 u32 hw_cap; 363 364 /* MAC HW feature 0 */ 365 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0); 366 dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27; 367 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16; 368 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14; 369 dma_cap->eee = (hw_cap & XGMAC_HWFEAT_EEESEL) >> 13; 370 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12; 371 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11; 372 dma_cap->av &= !(hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10; 373 dma_cap->arpoffsel = (hw_cap & XGMAC_HWFEAT_ARPOFFSEL) >> 9; 374 dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8; 375 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7; 376 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6; 377 dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4; 378 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; 379 380 /* MAC HW feature 1 */ 381 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1); 382 dma_cap->l3l4fnum = (hw_cap & XGMAC_HWFEAT_L3L4FNUM) >> 27; 383 dma_cap->hash_tb_sz = (hw_cap & XGMAC_HWFEAT_HASHTBLSZ) >> 24; 384 dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20; 385 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18; 386 dma_cap->sphen = (hw_cap & XGMAC_HWFEAT_SPHEN) >> 17; 387 388 dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14; 389 switch (dma_cap->addr64) { 390 case 0: 391 dma_cap->addr64 = 32; 392 break; 393 case 1: 394 dma_cap->addr64 = 40; 395 break; 396 case 2: 397 dma_cap->addr64 = 48; 398 break; 399 default: 400 dma_cap->addr64 = 32; 401 break; 402 } 403 404 dma_cap->tx_fifo_size = 405 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6); 406 dma_cap->rx_fifo_size = 407 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0); 408 409 /* MAC HW feature 2 */ 410 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2); 411 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24; 412 dma_cap->number_tx_channel = 413 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1; 414 dma_cap->number_rx_channel = 415 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1; 416 dma_cap->number_tx_queues = 417 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1; 418 dma_cap->number_rx_queues = 419 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1; 420 421 /* MAC HW feature 3 */ 422 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3); 423 dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14; 424 dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13; 425 dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11; 426 dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9; 427 dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3; 428 } 429 430 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan) 431 { 432 u32 i; 433 434 for (i = 0; i < nchan; i++) 435 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i)); 436 } 437 438 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 439 { 440 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan)); 441 } 442 443 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) 444 { 445 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan)); 446 } 447 448 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) 449 { 450 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan)); 451 } 452 453 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) 454 { 455 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan)); 456 } 457 458 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 459 { 460 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 461 462 if (en) 463 value |= XGMAC_TSE; 464 else 465 value &= ~XGMAC_TSE; 466 467 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); 468 } 469 470 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 471 { 472 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 473 474 value &= ~XGMAC_TXQEN; 475 if (qmode != MTL_QUEUE_AVB) { 476 value |= 0x2 << XGMAC_TXQEN_SHIFT; 477 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel)); 478 } else { 479 value |= 0x1 << XGMAC_TXQEN_SHIFT; 480 } 481 482 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); 483 } 484 485 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 486 { 487 u32 value; 488 489 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 490 value |= bfsize << 1; 491 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); 492 } 493 494 static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan) 495 { 496 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); 497 498 value &= ~XGMAC_CONFIG_HDSMS; 499 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ 500 writel(value, ioaddr + XGMAC_RX_CONFIG); 501 502 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 503 if (en) 504 value |= XGMAC_SPH; 505 else 506 value &= ~XGMAC_SPH; 507 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); 508 } 509 510 const struct stmmac_dma_ops dwxgmac210_dma_ops = { 511 .reset = dwxgmac2_dma_reset, 512 .init = dwxgmac2_dma_init, 513 .init_chan = dwxgmac2_dma_init_chan, 514 .init_rx_chan = dwxgmac2_dma_init_rx_chan, 515 .init_tx_chan = dwxgmac2_dma_init_tx_chan, 516 .axi = dwxgmac2_dma_axi, 517 .dump_regs = dwxgmac2_dma_dump_regs, 518 .dma_rx_mode = dwxgmac2_dma_rx_mode, 519 .dma_tx_mode = dwxgmac2_dma_tx_mode, 520 .enable_dma_irq = dwxgmac2_enable_dma_irq, 521 .disable_dma_irq = dwxgmac2_disable_dma_irq, 522 .start_tx = dwxgmac2_dma_start_tx, 523 .stop_tx = dwxgmac2_dma_stop_tx, 524 .start_rx = dwxgmac2_dma_start_rx, 525 .stop_rx = dwxgmac2_dma_stop_rx, 526 .dma_interrupt = dwxgmac2_dma_interrupt, 527 .get_hw_feature = dwxgmac2_get_hw_feature, 528 .rx_watchdog = dwxgmac2_rx_watchdog, 529 .set_rx_ring_len = dwxgmac2_set_rx_ring_len, 530 .set_tx_ring_len = dwxgmac2_set_tx_ring_len, 531 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr, 532 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr, 533 .enable_tso = dwxgmac2_enable_tso, 534 .qmode = dwxgmac2_qmode, 535 .set_bfsize = dwxgmac2_set_bfsize, 536 .enable_sph = dwxgmac2_enable_sph, 537 }; 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