1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac XGMAC support. 5 */ 6 7 #include <linux/stmmac.h> 8 #include "common.h" 9 #include "dwxgmac2.h" 10 11 static int dwxgmac2_get_tx_status(struct net_device_stats *stats, 12 struct stmmac_extra_stats *x, 13 struct dma_desc *p, void __iomem *ioaddr) 14 { 15 unsigned int tdes3 = le32_to_cpu(p->des3); 16 int ret = tx_done; 17 18 if (unlikely(tdes3 & XGMAC_TDES3_OWN)) 19 return tx_dma_own; 20 if (likely(!(tdes3 & XGMAC_TDES3_LD))) 21 return tx_not_ls; 22 23 return ret; 24 } 25 26 static int dwxgmac2_get_rx_status(struct net_device_stats *stats, 27 struct stmmac_extra_stats *x, 28 struct dma_desc *p) 29 { 30 unsigned int rdes3 = le32_to_cpu(p->des3); 31 32 if (unlikely(rdes3 & XGMAC_RDES3_OWN)) 33 return dma_own; 34 if (unlikely(rdes3 & XGMAC_RDES3_CTXT)) 35 return discard_frame; 36 if (likely(!(rdes3 & XGMAC_RDES3_LD))) 37 return rx_not_ls; 38 if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD))) 39 return discard_frame; 40 41 return good_frame; 42 } 43 44 static int dwxgmac2_get_tx_len(struct dma_desc *p) 45 { 46 return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L); 47 } 48 49 static int dwxgmac2_get_tx_owner(struct dma_desc *p) 50 { 51 return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0; 52 } 53 54 static void dwxgmac2_set_tx_owner(struct dma_desc *p) 55 { 56 p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN); 57 } 58 59 static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic) 60 { 61 p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN); 62 63 if (!disable_rx_ic) 64 p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC); 65 } 66 67 static int dwxgmac2_get_tx_ls(struct dma_desc *p) 68 { 69 return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0; 70 } 71 72 static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe) 73 { 74 return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL); 75 } 76 77 static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p) 78 { 79 p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE); 80 } 81 82 static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p) 83 { 84 return 0; /* Not supported */ 85 } 86 87 static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts) 88 { 89 struct dma_desc *p = (struct dma_desc *)desc; 90 u64 ns = 0; 91 92 ns += le32_to_cpu(p->des1) * 1000000000ULL; 93 ns += le32_to_cpu(p->des0); 94 95 *ts = ns; 96 } 97 98 static int dwxgmac2_rx_check_timestamp(void *desc) 99 { 100 struct dma_desc *p = (struct dma_desc *)desc; 101 unsigned int rdes3 = le32_to_cpu(p->des3); 102 bool desc_valid, ts_valid; 103 104 dma_rmb(); 105 106 desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT); 107 ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA); 108 109 if (likely(desc_valid && ts_valid)) { 110 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff)) 111 return -EINVAL; 112 return 0; 113 } 114 115 return -EINVAL; 116 } 117 118 static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc, 119 u32 ats) 120 { 121 struct dma_desc *p = (struct dma_desc *)desc; 122 unsigned int rdes3 = le32_to_cpu(p->des3); 123 int ret = -EBUSY; 124 125 if (likely(rdes3 & XGMAC_RDES3_CDA)) 126 ret = dwxgmac2_rx_check_timestamp(next_desc); 127 128 return !ret; 129 } 130 131 static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic, 132 int mode, int end, int bfsize) 133 { 134 dwxgmac2_set_rx_owner(p, disable_rx_ic); 135 } 136 137 static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end) 138 { 139 p->des0 = 0; 140 p->des1 = 0; 141 p->des2 = 0; 142 p->des3 = 0; 143 } 144 145 static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 146 bool csum_flag, int mode, bool tx_own, 147 bool ls, unsigned int tot_pkt_len) 148 { 149 unsigned int tdes3 = le32_to_cpu(p->des3); 150 151 p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L); 152 153 tdes3 |= tot_pkt_len & XGMAC_TDES3_FL; 154 if (is_fs) 155 tdes3 |= XGMAC_TDES3_FD; 156 else 157 tdes3 &= ~XGMAC_TDES3_FD; 158 159 if (csum_flag) 160 tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT; 161 else 162 tdes3 &= ~XGMAC_TDES3_CIC; 163 164 if (ls) 165 tdes3 |= XGMAC_TDES3_LD; 166 else 167 tdes3 &= ~XGMAC_TDES3_LD; 168 169 /* Finally set the OWN bit. Later the DMA will start! */ 170 if (tx_own) 171 tdes3 |= XGMAC_TDES3_OWN; 172 173 if (is_fs && tx_own) 174 /* When the own bit, for the first frame, has to be set, all 175 * descriptors for the same frame has to be set before, to 176 * avoid race condition. 177 */ 178 dma_wmb(); 179 180 p->des3 = cpu_to_le32(tdes3); 181 } 182 183 static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs, 184 int len1, int len2, bool tx_own, 185 bool ls, unsigned int tcphdrlen, 186 unsigned int tcppayloadlen) 187 { 188 unsigned int tdes3 = le32_to_cpu(p->des3); 189 190 if (len1) 191 p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L); 192 if (len2) 193 p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) & 194 XGMAC_TDES2_B2L); 195 if (is_fs) { 196 tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE; 197 tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) & 198 XGMAC_TDES3_THL; 199 tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL; 200 } else { 201 tdes3 &= ~XGMAC_TDES3_FD; 202 } 203 204 if (ls) 205 tdes3 |= XGMAC_TDES3_LD; 206 else 207 tdes3 &= ~XGMAC_TDES3_LD; 208 209 /* Finally set the OWN bit. Later the DMA will start! */ 210 if (tx_own) 211 tdes3 |= XGMAC_TDES3_OWN; 212 213 if (is_fs && tx_own) 214 /* When the own bit, for the first frame, has to be set, all 215 * descriptors for the same frame has to be set before, to 216 * avoid race condition. 217 */ 218 dma_wmb(); 219 220 p->des3 = cpu_to_le32(tdes3); 221 } 222 223 static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode) 224 { 225 p->des0 = 0; 226 p->des1 = 0; 227 p->des2 = 0; 228 p->des3 = 0; 229 } 230 231 static void dwxgmac2_set_tx_ic(struct dma_desc *p) 232 { 233 p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC); 234 } 235 236 static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss) 237 { 238 p->des0 = 0; 239 p->des1 = 0; 240 p->des2 = cpu_to_le32(mss); 241 p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV); 242 } 243 244 static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr) 245 { 246 p->des0 = cpu_to_le32(lower_32_bits(addr)); 247 p->des1 = cpu_to_le32(upper_32_bits(addr)); 248 } 249 250 static void dwxgmac2_clear(struct dma_desc *p) 251 { 252 p->des0 = 0; 253 p->des1 = 0; 254 p->des2 = 0; 255 p->des3 = 0; 256 } 257 258 static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash, 259 enum pkt_hash_types *type) 260 { 261 unsigned int rdes3 = le32_to_cpu(p->des3); 262 u32 ptype; 263 264 if (rdes3 & XGMAC_RDES3_RSV) { 265 ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT; 266 267 switch (ptype) { 268 case XGMAC_L34T_IP4TCP: 269 case XGMAC_L34T_IP4UDP: 270 case XGMAC_L34T_IP6TCP: 271 case XGMAC_L34T_IP6UDP: 272 *type = PKT_HASH_TYPE_L4; 273 break; 274 default: 275 *type = PKT_HASH_TYPE_L3; 276 break; 277 } 278 279 *hash = le32_to_cpu(p->des1); 280 return 0; 281 } 282 283 return -EINVAL; 284 } 285 286 static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len) 287 { 288 if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T) 289 *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; 290 } 291 292 static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid) 293 { 294 p->des2 = cpu_to_le32(lower_32_bits(addr)); 295 p->des3 = cpu_to_le32(upper_32_bits(addr)); 296 } 297 298 static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type) 299 { 300 sarc_type <<= XGMAC_TDES3_SAIC_SHIFT; 301 302 p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC); 303 } 304 305 static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag, 306 u32 inner_type) 307 { 308 p->des0 = 0; 309 p->des1 = 0; 310 p->des2 = 0; 311 p->des3 = 0; 312 313 /* Inner VLAN */ 314 if (inner_type) { 315 u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT; 316 317 des &= XGMAC_TDES2_IVT; 318 p->des2 = cpu_to_le32(des); 319 320 des = inner_type << XGMAC_TDES3_IVTIR_SHIFT; 321 des &= XGMAC_TDES3_IVTIR; 322 p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV); 323 } 324 325 /* Outer VLAN */ 326 p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT); 327 p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV); 328 329 p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT); 330 } 331 332 static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type) 333 { 334 type <<= XGMAC_TDES2_VTIR_SHIFT; 335 p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR); 336 } 337 338 static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec) 339 { 340 p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV); 341 p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT); 342 p->des6 = 0; 343 p->des7 = 0; 344 } 345 346 const struct stmmac_desc_ops dwxgmac210_desc_ops = { 347 .tx_status = dwxgmac2_get_tx_status, 348 .rx_status = dwxgmac2_get_rx_status, 349 .get_tx_len = dwxgmac2_get_tx_len, 350 .get_tx_owner = dwxgmac2_get_tx_owner, 351 .set_tx_owner = dwxgmac2_set_tx_owner, 352 .set_rx_owner = dwxgmac2_set_rx_owner, 353 .get_tx_ls = dwxgmac2_get_tx_ls, 354 .get_rx_frame_len = dwxgmac2_get_rx_frame_len, 355 .enable_tx_timestamp = dwxgmac2_enable_tx_timestamp, 356 .get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status, 357 .get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status, 358 .get_timestamp = dwxgmac2_get_timestamp, 359 .set_tx_ic = dwxgmac2_set_tx_ic, 360 .prepare_tx_desc = dwxgmac2_prepare_tx_desc, 361 .prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc, 362 .release_tx_desc = dwxgmac2_release_tx_desc, 363 .init_rx_desc = dwxgmac2_init_rx_desc, 364 .init_tx_desc = dwxgmac2_init_tx_desc, 365 .set_mss = dwxgmac2_set_mss, 366 .set_addr = dwxgmac2_set_addr, 367 .clear = dwxgmac2_clear, 368 .get_rx_hash = dwxgmac2_get_rx_hash, 369 .get_rx_header_len = dwxgmac2_get_rx_header_len, 370 .set_sec_addr = dwxgmac2_set_sec_addr, 371 .set_sarc = dwxgmac2_set_sarc, 372 .set_vlan_tag = dwxgmac2_set_vlan_tag, 373 .set_vlan = dwxgmac2_set_vlan, 374 .set_tbs = dwxgmac2_set_tbs, 375 }; 376