1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac XGMAC definitions. 5 */ 6 7 #ifndef __STMMAC_DWXGMAC2_H__ 8 #define __STMMAC_DWXGMAC2_H__ 9 10 #include "common.h" 11 12 /* Misc */ 13 #define XGMAC_JUMBO_LEN 16368 14 15 /* MAC Registers */ 16 #define XGMAC_TX_CONFIG 0x00000000 17 #define XGMAC_CONFIG_SS_OFF 29 18 #define XGMAC_CONFIG_SS_MASK GENMASK(30, 29) 19 #define XGMAC_CONFIG_SS_10000 (0x0 << XGMAC_CONFIG_SS_OFF) 20 #define XGMAC_CONFIG_SS_2500 (0x2 << XGMAC_CONFIG_SS_OFF) 21 #define XGMAC_CONFIG_SS_1000 (0x3 << XGMAC_CONFIG_SS_OFF) 22 #define XGMAC_CONFIG_SARC GENMASK(22, 20) 23 #define XGMAC_CONFIG_SARC_SHIFT 20 24 #define XGMAC_CONFIG_JD BIT(16) 25 #define XGMAC_CONFIG_TE BIT(0) 26 #define XGMAC_CORE_INIT_TX (XGMAC_CONFIG_JD) 27 #define XGMAC_RX_CONFIG 0x00000004 28 #define XGMAC_CONFIG_ARPEN BIT(31) 29 #define XGMAC_CONFIG_GPSL GENMASK(29, 16) 30 #define XGMAC_CONFIG_GPSL_SHIFT 16 31 #define XGMAC_CONFIG_S2KP BIT(11) 32 #define XGMAC_CONFIG_IPC BIT(9) 33 #define XGMAC_CONFIG_JE BIT(8) 34 #define XGMAC_CONFIG_WD BIT(7) 35 #define XGMAC_CONFIG_GPSLCE BIT(6) 36 #define XGMAC_CONFIG_CST BIT(2) 37 #define XGMAC_CONFIG_ACS BIT(1) 38 #define XGMAC_CONFIG_RE BIT(0) 39 #define XGMAC_CORE_INIT_RX 0 40 #define XGMAC_PACKET_FILTER 0x00000008 41 #define XGMAC_FILTER_RA BIT(31) 42 #define XGMAC_FILTER_PM BIT(4) 43 #define XGMAC_FILTER_HMC BIT(2) 44 #define XGMAC_FILTER_PR BIT(0) 45 #define XGMAC_HASH_TABLE(x) (0x00000010 + (x) * 4) 46 #define XGMAC_RXQ_CTRL0 0x000000a0 47 #define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2) 48 #define XGMAC_RXQEN_SHIFT(x) ((x) * 2) 49 #define XGMAC_RXQ_CTRL2 0x000000a8 50 #define XGMAC_RXQ_CTRL3 0x000000ac 51 #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8) 52 #define XGMAC_PSRQ_SHIFT(x) ((x) * 8) 53 #define XGMAC_INT_STATUS 0x000000b0 54 #define XGMAC_PMTIS BIT(4) 55 #define XGMAC_INT_EN 0x000000b4 56 #define XGMAC_TSIE BIT(12) 57 #define XGMAC_LPIIE BIT(5) 58 #define XGMAC_PMTIE BIT(4) 59 #define XGMAC_INT_DEFAULT_EN (XGMAC_LPIIE | XGMAC_PMTIE | XGMAC_TSIE) 60 #define XGMAC_Qx_TX_FLOW_CTRL(x) (0x00000070 + (x) * 4) 61 #define XGMAC_PT GENMASK(31, 16) 62 #define XGMAC_PT_SHIFT 16 63 #define XGMAC_TFE BIT(1) 64 #define XGMAC_RX_FLOW_CTRL 0x00000090 65 #define XGMAC_RFE BIT(0) 66 #define XGMAC_PMT 0x000000c0 67 #define XGMAC_GLBLUCAST BIT(9) 68 #define XGMAC_RWKPKTEN BIT(2) 69 #define XGMAC_MGKPKTEN BIT(1) 70 #define XGMAC_PWRDWN BIT(0) 71 #define XGMAC_HW_FEATURE0 0x0000011c 72 #define XGMAC_HWFEAT_SAVLANINS BIT(27) 73 #define XGMAC_HWFEAT_RXCOESEL BIT(16) 74 #define XGMAC_HWFEAT_TXCOESEL BIT(14) 75 #define XGMAC_HWFEAT_TSSEL BIT(12) 76 #define XGMAC_HWFEAT_AVSEL BIT(11) 77 #define XGMAC_HWFEAT_RAVSEL BIT(10) 78 #define XGMAC_HWFEAT_ARPOFFSEL BIT(9) 79 #define XGMAC_HWFEAT_MGKSEL BIT(7) 80 #define XGMAC_HWFEAT_RWKSEL BIT(6) 81 #define XGMAC_HWFEAT_GMIISEL BIT(1) 82 #define XGMAC_HW_FEATURE1 0x00000120 83 #define XGMAC_HWFEAT_TSOEN BIT(18) 84 #define XGMAC_HWFEAT_TXFIFOSIZE GENMASK(10, 6) 85 #define XGMAC_HWFEAT_RXFIFOSIZE GENMASK(4, 0) 86 #define XGMAC_HW_FEATURE2 0x00000124 87 #define XGMAC_HWFEAT_PPSOUTNUM GENMASK(26, 24) 88 #define XGMAC_HWFEAT_TXCHCNT GENMASK(21, 18) 89 #define XGMAC_HWFEAT_RXCHCNT GENMASK(15, 12) 90 #define XGMAC_HWFEAT_TXQCNT GENMASK(9, 6) 91 #define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0) 92 #define XGMAC_MDIO_ADDR 0x00000200 93 #define XGMAC_MDIO_DATA 0x00000204 94 #define XGMAC_MDIO_C22P 0x00000220 95 #define XGMAC_ADDR0_HIGH 0x00000300 96 #define XGMAC_AE BIT(31) 97 #define XGMAC_DCS GENMASK(19, 16) 98 #define XGMAC_DCS_SHIFT 16 99 #define XGMAC_ADDR0_LOW 0x00000304 100 #define XGMAC_ARP_ADDR 0x00000c10 101 #define XGMAC_TIMESTAMP_STATUS 0x00000d20 102 #define XGMAC_TXTSC BIT(15) 103 #define XGMAC_TXTIMESTAMP_NSEC 0x00000d30 104 #define XGMAC_TXTSSTSLO GENMASK(30, 0) 105 #define XGMAC_TXTIMESTAMP_SEC 0x00000d34 106 107 /* MTL Registers */ 108 #define XGMAC_MTL_OPMODE 0x00001000 109 #define XGMAC_ETSALG GENMASK(6, 5) 110 #define XGMAC_WRR (0x0 << 5) 111 #define XGMAC_WFQ (0x1 << 5) 112 #define XGMAC_DWRR (0x2 << 5) 113 #define XGMAC_RAA BIT(2) 114 #define XGMAC_MTL_INT_STATUS 0x00001020 115 #define XGMAC_MTL_RXQ_DMA_MAP0 0x00001030 116 #define XGMAC_MTL_RXQ_DMA_MAP1 0x00001034 117 #define XGMAC_QxMDMACH(x) GENMASK((x) * 8 + 3, (x) * 8) 118 #define XGMAC_QxMDMACH_SHIFT(x) ((x) * 8) 119 #define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x))) 120 #define XGMAC_TQS GENMASK(25, 16) 121 #define XGMAC_TQS_SHIFT 16 122 #define XGMAC_Q2TCMAP GENMASK(10, 8) 123 #define XGMAC_Q2TCMAP_SHIFT 8 124 #define XGMAC_TTC GENMASK(6, 4) 125 #define XGMAC_TTC_SHIFT 4 126 #define XGMAC_TXQEN GENMASK(3, 2) 127 #define XGMAC_TXQEN_SHIFT 2 128 #define XGMAC_TSF BIT(1) 129 #define XGMAC_MTL_TCx_ETS_CONTROL(x) (0x00001110 + (0x80 * (x))) 130 #define XGMAC_MTL_TCx_QUANTUM_WEIGHT(x) (0x00001118 + (0x80 * (x))) 131 #define XGMAC_MTL_TCx_SENDSLOPE(x) (0x0000111c + (0x80 * (x))) 132 #define XGMAC_MTL_TCx_HICREDIT(x) (0x00001120 + (0x80 * (x))) 133 #define XGMAC_MTL_TCx_LOCREDIT(x) (0x00001124 + (0x80 * (x))) 134 #define XGMAC_CC BIT(3) 135 #define XGMAC_TSA GENMASK(1, 0) 136 #define XGMAC_SP (0x0 << 0) 137 #define XGMAC_CBS (0x1 << 0) 138 #define XGMAC_ETS (0x2 << 0) 139 #define XGMAC_MTL_RXQ_OPMODE(x) (0x00001140 + (0x80 * (x))) 140 #define XGMAC_RQS GENMASK(25, 16) 141 #define XGMAC_RQS_SHIFT 16 142 #define XGMAC_EHFC BIT(7) 143 #define XGMAC_RSF BIT(5) 144 #define XGMAC_RTC GENMASK(1, 0) 145 #define XGMAC_RTC_SHIFT 0 146 #define XGMAC_MTL_RXQ_FLOW_CONTROL(x) (0x00001150 + (0x80 * (x))) 147 #define XGMAC_RFD GENMASK(31, 17) 148 #define XGMAC_RFD_SHIFT 17 149 #define XGMAC_RFA GENMASK(15, 1) 150 #define XGMAC_RFA_SHIFT 1 151 #define XGMAC_MTL_QINTEN(x) (0x00001170 + (0x80 * (x))) 152 #define XGMAC_RXOIE BIT(16) 153 #define XGMAC_MTL_QINT_STATUS(x) (0x00001174 + (0x80 * (x))) 154 #define XGMAC_RXOVFIS BIT(16) 155 #define XGMAC_ABPSIS BIT(1) 156 #define XGMAC_TXUNFIS BIT(0) 157 158 /* DMA Registers */ 159 #define XGMAC_DMA_MODE 0x00003000 160 #define XGMAC_SWR BIT(0) 161 #define XGMAC_DMA_SYSBUS_MODE 0x00003004 162 #define XGMAC_WR_OSR_LMT GENMASK(29, 24) 163 #define XGMAC_WR_OSR_LMT_SHIFT 24 164 #define XGMAC_RD_OSR_LMT GENMASK(21, 16) 165 #define XGMAC_RD_OSR_LMT_SHIFT 16 166 #define XGMAC_EN_LPI BIT(15) 167 #define XGMAC_LPI_XIT_PKT BIT(14) 168 #define XGMAC_AAL BIT(12) 169 #define XGMAC_BLEN GENMASK(7, 1) 170 #define XGMAC_BLEN256 BIT(7) 171 #define XGMAC_BLEN128 BIT(6) 172 #define XGMAC_BLEN64 BIT(5) 173 #define XGMAC_BLEN32 BIT(4) 174 #define XGMAC_BLEN16 BIT(3) 175 #define XGMAC_BLEN8 BIT(2) 176 #define XGMAC_BLEN4 BIT(1) 177 #define XGMAC_UNDEF BIT(0) 178 #define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x))) 179 #define XGMAC_PBLx8 BIT(16) 180 #define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x))) 181 #define XGMAC_TxPBL GENMASK(21, 16) 182 #define XGMAC_TxPBL_SHIFT 16 183 #define XGMAC_TSE BIT(12) 184 #define XGMAC_OSP BIT(4) 185 #define XGMAC_TXST BIT(0) 186 #define XGMAC_DMA_CH_RX_CONTROL(x) (0x00003108 + (0x80 * (x))) 187 #define XGMAC_RxPBL GENMASK(21, 16) 188 #define XGMAC_RxPBL_SHIFT 16 189 #define XGMAC_RXST BIT(0) 190 #define XGMAC_DMA_CH_TxDESC_LADDR(x) (0x00003114 + (0x80 * (x))) 191 #define XGMAC_DMA_CH_RxDESC_LADDR(x) (0x0000311c + (0x80 * (x))) 192 #define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x) (0x00003124 + (0x80 * (x))) 193 #define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x) (0x0000312c + (0x80 * (x))) 194 #define XGMAC_DMA_CH_TxDESC_RING_LEN(x) (0x00003130 + (0x80 * (x))) 195 #define XGMAC_DMA_CH_RxDESC_RING_LEN(x) (0x00003134 + (0x80 * (x))) 196 #define XGMAC_DMA_CH_INT_EN(x) (0x00003138 + (0x80 * (x))) 197 #define XGMAC_NIE BIT(15) 198 #define XGMAC_AIE BIT(14) 199 #define XGMAC_RBUE BIT(7) 200 #define XGMAC_RIE BIT(6) 201 #define XGMAC_TBUE BIT(2) 202 #define XGMAC_TIE BIT(0) 203 #define XGMAC_DMA_INT_DEFAULT_EN (XGMAC_NIE | XGMAC_AIE | XGMAC_RBUE | \ 204 XGMAC_RIE | XGMAC_TBUE | XGMAC_TIE) 205 #define XGMAC_DMA_CH_Rx_WATCHDOG(x) (0x0000313c + (0x80 * (x))) 206 #define XGMAC_RWT GENMASK(7, 0) 207 #define XGMAC_DMA_CH_STATUS(x) (0x00003160 + (0x80 * (x))) 208 #define XGMAC_NIS BIT(15) 209 #define XGMAC_AIS BIT(14) 210 #define XGMAC_FBE BIT(12) 211 #define XGMAC_RBU BIT(7) 212 #define XGMAC_RI BIT(6) 213 #define XGMAC_TBU BIT(2) 214 #define XGMAC_TPS BIT(1) 215 #define XGMAC_TI BIT(0) 216 217 /* Descriptors */ 218 #define XGMAC_TDES2_IOC BIT(31) 219 #define XGMAC_TDES2_TTSE BIT(30) 220 #define XGMAC_TDES2_B2L GENMASK(29, 16) 221 #define XGMAC_TDES2_B2L_SHIFT 16 222 #define XGMAC_TDES2_B1L GENMASK(13, 0) 223 #define XGMAC_TDES3_OWN BIT(31) 224 #define XGMAC_TDES3_CTXT BIT(30) 225 #define XGMAC_TDES3_FD BIT(29) 226 #define XGMAC_TDES3_LD BIT(28) 227 #define XGMAC_TDES3_CPC GENMASK(27, 26) 228 #define XGMAC_TDES3_CPC_SHIFT 26 229 #define XGMAC_TDES3_TCMSSV BIT(26) 230 #define XGMAC_TDES3_THL GENMASK(22, 19) 231 #define XGMAC_TDES3_THL_SHIFT 19 232 #define XGMAC_TDES3_TSE BIT(18) 233 #define XGMAC_TDES3_CIC GENMASK(17, 16) 234 #define XGMAC_TDES3_CIC_SHIFT 16 235 #define XGMAC_TDES3_TPL GENMASK(17, 0) 236 #define XGMAC_TDES3_FL GENMASK(14, 0) 237 #define XGMAC_RDES3_OWN BIT(31) 238 #define XGMAC_RDES3_CTXT BIT(30) 239 #define XGMAC_RDES3_IOC BIT(30) 240 #define XGMAC_RDES3_LD BIT(28) 241 #define XGMAC_RDES3_CDA BIT(27) 242 #define XGMAC_RDES3_ES BIT(15) 243 #define XGMAC_RDES3_PL GENMASK(13, 0) 244 #define XGMAC_RDES3_TSD BIT(6) 245 #define XGMAC_RDES3_TSA BIT(4) 246 247 #endif /* __STMMAC_DWXGMAC2_H__ */ 248