1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include "common.h" 12 #include "dwmac_dma.h" 13 14 #define GMAC_HI_REG_AE 0x80000000 15 16 int dwmac_dma_reset(void __iomem *ioaddr) 17 { 18 u32 value = readl(ioaddr + DMA_BUS_MODE); 19 int err; 20 21 /* DMA SW reset */ 22 value |= DMA_BUS_MODE_SFT_RESET; 23 writel(value, ioaddr + DMA_BUS_MODE); 24 25 err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 26 !(value & DMA_BUS_MODE_SFT_RESET), 27 10000, 100000); 28 if (err) 29 return -EBUSY; 30 31 return 0; 32 } 33 34 /* CSR1 enables the transmit DMA to check for new descriptor */ 35 void dwmac_enable_dma_transmission(void __iomem *ioaddr) 36 { 37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 38 } 39 40 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) 41 { 42 u32 value = readl(ioaddr + DMA_INTR_ENA); 43 44 if (rx) 45 value |= DMA_INTR_DEFAULT_RX; 46 if (tx) 47 value |= DMA_INTR_DEFAULT_TX; 48 49 writel(value, ioaddr + DMA_INTR_ENA); 50 } 51 52 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) 53 { 54 u32 value = readl(ioaddr + DMA_INTR_ENA); 55 56 if (rx) 57 value &= ~DMA_INTR_DEFAULT_RX; 58 if (tx) 59 value &= ~DMA_INTR_DEFAULT_TX; 60 61 writel(value, ioaddr + DMA_INTR_ENA); 62 } 63 64 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 65 { 66 u32 value = readl(ioaddr + DMA_CONTROL); 67 value |= DMA_CONTROL_ST; 68 writel(value, ioaddr + DMA_CONTROL); 69 } 70 71 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 72 { 73 u32 value = readl(ioaddr + DMA_CONTROL); 74 value &= ~DMA_CONTROL_ST; 75 writel(value, ioaddr + DMA_CONTROL); 76 } 77 78 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 79 { 80 u32 value = readl(ioaddr + DMA_CONTROL); 81 value |= DMA_CONTROL_SR; 82 writel(value, ioaddr + DMA_CONTROL); 83 } 84 85 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 86 { 87 u32 value = readl(ioaddr + DMA_CONTROL); 88 value &= ~DMA_CONTROL_SR; 89 writel(value, ioaddr + DMA_CONTROL); 90 } 91 92 #ifdef DWMAC_DMA_DEBUG 93 static void show_tx_process_state(unsigned int status) 94 { 95 unsigned int state; 96 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 97 98 switch (state) { 99 case 0: 100 pr_debug("- TX (Stopped): Reset or Stop command\n"); 101 break; 102 case 1: 103 pr_debug("- TX (Running): Fetching the Tx desc\n"); 104 break; 105 case 2: 106 pr_debug("- TX (Running): Waiting for end of tx\n"); 107 break; 108 case 3: 109 pr_debug("- TX (Running): Reading the data " 110 "and queuing the data into the Tx buf\n"); 111 break; 112 case 6: 113 pr_debug("- TX (Suspended): Tx Buff Underflow " 114 "or an unavailable Transmit descriptor\n"); 115 break; 116 case 7: 117 pr_debug("- TX (Running): Closing Tx descriptor\n"); 118 break; 119 default: 120 break; 121 } 122 } 123 124 static void show_rx_process_state(unsigned int status) 125 { 126 unsigned int state; 127 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 128 129 switch (state) { 130 case 0: 131 pr_debug("- RX (Stopped): Reset or Stop command\n"); 132 break; 133 case 1: 134 pr_debug("- RX (Running): Fetching the Rx desc\n"); 135 break; 136 case 2: 137 pr_debug("- RX (Running): Checking for end of pkt\n"); 138 break; 139 case 3: 140 pr_debug("- RX (Running): Waiting for Rx pkt\n"); 141 break; 142 case 4: 143 pr_debug("- RX (Suspended): Unavailable Rx buf\n"); 144 break; 145 case 5: 146 pr_debug("- RX (Running): Closing Rx descriptor\n"); 147 break; 148 case 6: 149 pr_debug("- RX(Running): Flushing the current frame" 150 " from the Rx buf\n"); 151 break; 152 case 7: 153 pr_debug("- RX (Running): Queuing the Rx frame" 154 " from the Rx buf into memory\n"); 155 break; 156 default: 157 break; 158 } 159 } 160 #endif 161 162 int dwmac_dma_interrupt(void __iomem *ioaddr, 163 struct stmmac_extra_stats *x, u32 chan) 164 { 165 int ret = 0; 166 /* read the status register (CSR5) */ 167 u32 intr_status = readl(ioaddr + DMA_STATUS); 168 169 #ifdef DWMAC_DMA_DEBUG 170 /* Enable it to monitor DMA rx/tx status in case of critical problems */ 171 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status); 172 show_tx_process_state(intr_status); 173 show_rx_process_state(intr_status); 174 #endif 175 /* ABNORMAL interrupts */ 176 if (unlikely(intr_status & DMA_STATUS_AIS)) { 177 if (unlikely(intr_status & DMA_STATUS_UNF)) { 178 ret = tx_hard_error_bump_tc; 179 x->tx_undeflow_irq++; 180 } 181 if (unlikely(intr_status & DMA_STATUS_TJT)) 182 x->tx_jabber_irq++; 183 184 if (unlikely(intr_status & DMA_STATUS_OVF)) 185 x->rx_overflow_irq++; 186 187 if (unlikely(intr_status & DMA_STATUS_RU)) 188 x->rx_buf_unav_irq++; 189 if (unlikely(intr_status & DMA_STATUS_RPS)) 190 x->rx_process_stopped_irq++; 191 if (unlikely(intr_status & DMA_STATUS_RWT)) 192 x->rx_watchdog_irq++; 193 if (unlikely(intr_status & DMA_STATUS_ETI)) 194 x->tx_early_irq++; 195 if (unlikely(intr_status & DMA_STATUS_TPS)) { 196 x->tx_process_stopped_irq++; 197 ret = tx_hard_error; 198 } 199 if (unlikely(intr_status & DMA_STATUS_FBI)) { 200 x->fatal_bus_error_irq++; 201 ret = tx_hard_error; 202 } 203 } 204 /* TX/RX NORMAL interrupts */ 205 if (likely(intr_status & DMA_STATUS_NIS)) { 206 x->normal_irq_n++; 207 if (likely(intr_status & DMA_STATUS_RI)) { 208 u32 value = readl(ioaddr + DMA_INTR_ENA); 209 /* to schedule NAPI on real RIE event. */ 210 if (likely(value & DMA_INTR_ENA_RIE)) { 211 x->rx_normal_irq_n++; 212 ret |= handle_rx; 213 } 214 } 215 if (likely(intr_status & DMA_STATUS_TI)) { 216 x->tx_normal_irq_n++; 217 ret |= handle_tx; 218 } 219 if (unlikely(intr_status & DMA_STATUS_ERI)) 220 x->rx_early_irq++; 221 } 222 /* Optional hardware blocks, interrupts should be disabled */ 223 if (unlikely(intr_status & 224 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 225 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 226 227 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 228 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 229 230 return ret; 231 } 232 233 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) 234 { 235 u32 csr6 = readl(ioaddr + DMA_CONTROL); 236 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 237 238 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 239 } 240 241 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 242 unsigned int high, unsigned int low) 243 { 244 unsigned long data; 245 246 data = (addr[5] << 8) | addr[4]; 247 /* For MAC Addr registers we have to set the Address Enable (AE) 248 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 249 * is RO. 250 */ 251 writel(data | GMAC_HI_REG_AE, ioaddr + high); 252 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 253 writel(data, ioaddr + low); 254 } 255 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr); 256 257 /* Enable disable MAC RX/TX */ 258 void stmmac_set_mac(void __iomem *ioaddr, bool enable) 259 { 260 u32 value = readl(ioaddr + MAC_CTRL_REG); 261 262 if (enable) 263 value |= MAC_ENABLE_RX | MAC_ENABLE_TX; 264 else 265 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); 266 267 writel(value, ioaddr + MAC_CTRL_REG); 268 } 269 270 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 271 unsigned int high, unsigned int low) 272 { 273 unsigned int hi_addr, lo_addr; 274 275 /* Read the MAC address from the hardware */ 276 hi_addr = readl(ioaddr + high); 277 lo_addr = readl(ioaddr + low); 278 279 /* Extract the MAC address from the high and low words */ 280 addr[0] = lo_addr & 0xff; 281 addr[1] = (lo_addr >> 8) & 0xff; 282 addr[2] = (lo_addr >> 16) & 0xff; 283 addr[3] = (lo_addr >> 24) & 0xff; 284 addr[4] = hi_addr & 0xff; 285 addr[5] = (hi_addr >> 8) & 0xff; 286 } 287 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr); 288