1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 4 5 6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 *******************************************************************************/ 8 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include "common.h" 12 #include "dwmac_dma.h" 13 14 #define GMAC_HI_REG_AE 0x80000000 15 16 int dwmac_dma_reset(void __iomem *ioaddr) 17 { 18 u32 value = readl(ioaddr + DMA_BUS_MODE); 19 20 /* DMA SW reset */ 21 value |= DMA_BUS_MODE_SFT_RESET; 22 writel(value, ioaddr + DMA_BUS_MODE); 23 24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, 25 !(value & DMA_BUS_MODE_SFT_RESET), 26 10000, 100000); 27 } 28 29 /* CSR1 enables the transmit DMA to check for new descriptor */ 30 void dwmac_enable_dma_transmission(void __iomem *ioaddr) 31 { 32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 33 } 34 35 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) 36 { 37 u32 value = readl(ioaddr + DMA_INTR_ENA); 38 39 if (rx) 40 value |= DMA_INTR_DEFAULT_RX; 41 if (tx) 42 value |= DMA_INTR_DEFAULT_TX; 43 44 writel(value, ioaddr + DMA_INTR_ENA); 45 } 46 47 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) 48 { 49 u32 value = readl(ioaddr + DMA_INTR_ENA); 50 51 if (rx) 52 value &= ~DMA_INTR_DEFAULT_RX; 53 if (tx) 54 value &= ~DMA_INTR_DEFAULT_TX; 55 56 writel(value, ioaddr + DMA_INTR_ENA); 57 } 58 59 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 60 { 61 u32 value = readl(ioaddr + DMA_CONTROL); 62 value |= DMA_CONTROL_ST; 63 writel(value, ioaddr + DMA_CONTROL); 64 } 65 66 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 67 { 68 u32 value = readl(ioaddr + DMA_CONTROL); 69 value &= ~DMA_CONTROL_ST; 70 writel(value, ioaddr + DMA_CONTROL); 71 } 72 73 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 74 { 75 u32 value = readl(ioaddr + DMA_CONTROL); 76 value |= DMA_CONTROL_SR; 77 writel(value, ioaddr + DMA_CONTROL); 78 } 79 80 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 81 { 82 u32 value = readl(ioaddr + DMA_CONTROL); 83 value &= ~DMA_CONTROL_SR; 84 writel(value, ioaddr + DMA_CONTROL); 85 } 86 87 #ifdef DWMAC_DMA_DEBUG 88 static void show_tx_process_state(unsigned int status) 89 { 90 unsigned int state; 91 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 92 93 switch (state) { 94 case 0: 95 pr_debug("- TX (Stopped): Reset or Stop command\n"); 96 break; 97 case 1: 98 pr_debug("- TX (Running): Fetching the Tx desc\n"); 99 break; 100 case 2: 101 pr_debug("- TX (Running): Waiting for end of tx\n"); 102 break; 103 case 3: 104 pr_debug("- TX (Running): Reading the data " 105 "and queuing the data into the Tx buf\n"); 106 break; 107 case 6: 108 pr_debug("- TX (Suspended): Tx Buff Underflow " 109 "or an unavailable Transmit descriptor\n"); 110 break; 111 case 7: 112 pr_debug("- TX (Running): Closing Tx descriptor\n"); 113 break; 114 default: 115 break; 116 } 117 } 118 119 static void show_rx_process_state(unsigned int status) 120 { 121 unsigned int state; 122 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 123 124 switch (state) { 125 case 0: 126 pr_debug("- RX (Stopped): Reset or Stop command\n"); 127 break; 128 case 1: 129 pr_debug("- RX (Running): Fetching the Rx desc\n"); 130 break; 131 case 2: 132 pr_debug("- RX (Running): Checking for end of pkt\n"); 133 break; 134 case 3: 135 pr_debug("- RX (Running): Waiting for Rx pkt\n"); 136 break; 137 case 4: 138 pr_debug("- RX (Suspended): Unavailable Rx buf\n"); 139 break; 140 case 5: 141 pr_debug("- RX (Running): Closing Rx descriptor\n"); 142 break; 143 case 6: 144 pr_debug("- RX(Running): Flushing the current frame" 145 " from the Rx buf\n"); 146 break; 147 case 7: 148 pr_debug("- RX (Running): Queuing the Rx frame" 149 " from the Rx buf into memory\n"); 150 break; 151 default: 152 break; 153 } 154 } 155 #endif 156 157 int dwmac_dma_interrupt(void __iomem *ioaddr, 158 struct stmmac_extra_stats *x, u32 chan) 159 { 160 int ret = 0; 161 /* read the status register (CSR5) */ 162 u32 intr_status = readl(ioaddr + DMA_STATUS); 163 164 #ifdef DWMAC_DMA_DEBUG 165 /* Enable it to monitor DMA rx/tx status in case of critical problems */ 166 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status); 167 show_tx_process_state(intr_status); 168 show_rx_process_state(intr_status); 169 #endif 170 /* ABNORMAL interrupts */ 171 if (unlikely(intr_status & DMA_STATUS_AIS)) { 172 if (unlikely(intr_status & DMA_STATUS_UNF)) { 173 ret = tx_hard_error_bump_tc; 174 x->tx_undeflow_irq++; 175 } 176 if (unlikely(intr_status & DMA_STATUS_TJT)) 177 x->tx_jabber_irq++; 178 179 if (unlikely(intr_status & DMA_STATUS_OVF)) 180 x->rx_overflow_irq++; 181 182 if (unlikely(intr_status & DMA_STATUS_RU)) 183 x->rx_buf_unav_irq++; 184 if (unlikely(intr_status & DMA_STATUS_RPS)) 185 x->rx_process_stopped_irq++; 186 if (unlikely(intr_status & DMA_STATUS_RWT)) 187 x->rx_watchdog_irq++; 188 if (unlikely(intr_status & DMA_STATUS_ETI)) 189 x->tx_early_irq++; 190 if (unlikely(intr_status & DMA_STATUS_TPS)) { 191 x->tx_process_stopped_irq++; 192 ret = tx_hard_error; 193 } 194 if (unlikely(intr_status & DMA_STATUS_FBI)) { 195 x->fatal_bus_error_irq++; 196 ret = tx_hard_error; 197 } 198 } 199 /* TX/RX NORMAL interrupts */ 200 if (likely(intr_status & DMA_STATUS_NIS)) { 201 x->normal_irq_n++; 202 if (likely(intr_status & DMA_STATUS_RI)) { 203 u32 value = readl(ioaddr + DMA_INTR_ENA); 204 /* to schedule NAPI on real RIE event. */ 205 if (likely(value & DMA_INTR_ENA_RIE)) { 206 x->rx_normal_irq_n++; 207 ret |= handle_rx; 208 } 209 } 210 if (likely(intr_status & DMA_STATUS_TI)) { 211 x->tx_normal_irq_n++; 212 ret |= handle_tx; 213 } 214 if (unlikely(intr_status & DMA_STATUS_ERI)) 215 x->rx_early_irq++; 216 } 217 /* Optional hardware blocks, interrupts should be disabled */ 218 if (unlikely(intr_status & 219 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 220 pr_warn("%s: unexpected status %08x\n", __func__, intr_status); 221 222 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 223 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 224 225 return ret; 226 } 227 228 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) 229 { 230 u32 csr6 = readl(ioaddr + DMA_CONTROL); 231 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 232 233 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 234 } 235 236 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 237 unsigned int high, unsigned int low) 238 { 239 unsigned long data; 240 241 data = (addr[5] << 8) | addr[4]; 242 /* For MAC Addr registers we have to set the Address Enable (AE) 243 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 244 * is RO. 245 */ 246 writel(data | GMAC_HI_REG_AE, ioaddr + high); 247 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 248 writel(data, ioaddr + low); 249 } 250 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr); 251 252 /* Enable disable MAC RX/TX */ 253 void stmmac_set_mac(void __iomem *ioaddr, bool enable) 254 { 255 u32 value = readl(ioaddr + MAC_CTRL_REG); 256 257 if (enable) 258 value |= MAC_ENABLE_RX | MAC_ENABLE_TX; 259 else 260 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); 261 262 writel(value, ioaddr + MAC_CTRL_REG); 263 } 264 265 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 266 unsigned int high, unsigned int low) 267 { 268 unsigned int hi_addr, lo_addr; 269 270 /* Read the MAC address from the hardware */ 271 hi_addr = readl(ioaddr + high); 272 lo_addr = readl(ioaddr + low); 273 274 /* Extract the MAC address from the high and low words */ 275 addr[0] = lo_addr & 0xff; 276 addr[1] = (lo_addr >> 8) & 0xff; 277 addr[2] = (lo_addr >> 16) & 0xff; 278 addr[3] = (lo_addr >> 24) & 0xff; 279 addr[4] = hi_addr & 0xff; 280 addr[5] = (hi_addr >> 8) & 0xff; 281 } 282 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr); 283