xref: /openbmc/linux/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h (revision 8b0adbe3e38dbe5aae9edf6f5159ffdca7cfbdf1) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * DWMAC4 DMA Header file.
4  *
5  * Copyright (C) 2007-2015  STMicroelectronics Ltd
6  *
7  * Author: Alexandre Torgue <alexandre.torgue@st.com>
8  */
9 
10 #ifndef __DWMAC4_DMA_H__
11 #define __DWMAC4_DMA_H__
12 
13 /* Define the max channel number used for tx (also rx).
14  * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
15  */
16 #define DMA_CHANNEL_NB_MAX		1
17 
18 #define DMA_BUS_MODE			0x00001000
19 #define DMA_SYS_BUS_MODE		0x00001004
20 #define DMA_STATUS			0x00001008
21 #define DMA_DEBUG_STATUS_0		0x0000100c
22 #define DMA_DEBUG_STATUS_1		0x00001010
23 #define DMA_DEBUG_STATUS_2		0x00001014
24 #define DMA_AXI_BUS_MODE		0x00001028
25 #define DMA_TBS_CTRL			0x00001050
26 
27 /* DMA Bus Mode bitmap */
28 #define DMA_BUS_MODE_INTM_MASK		GENMASK(17, 16)
29 #define DMA_BUS_MODE_INTM_SHIFT		16
30 #define DMA_BUS_MODE_INTM_MODE1		0x1
31 #define DMA_BUS_MODE_SFT_RESET		BIT(0)
32 
33 /* DMA SYS Bus Mode bitmap */
34 #define DMA_BUS_MODE_SPH		BIT(24)
35 #define DMA_BUS_MODE_PBL		BIT(16)
36 #define DMA_BUS_MODE_PBL_SHIFT		16
37 #define DMA_BUS_MODE_RPBL_SHIFT		16
38 #define DMA_BUS_MODE_MB			BIT(14)
39 #define DMA_BUS_MODE_FB			BIT(0)
40 
41 /* DMA Interrupt top status */
42 #define DMA_STATUS_MAC			BIT(17)
43 #define DMA_STATUS_MTL			BIT(16)
44 #define DMA_STATUS_CHAN7		BIT(7)
45 #define DMA_STATUS_CHAN6		BIT(6)
46 #define DMA_STATUS_CHAN5		BIT(5)
47 #define DMA_STATUS_CHAN4		BIT(4)
48 #define DMA_STATUS_CHAN3		BIT(3)
49 #define DMA_STATUS_CHAN2		BIT(2)
50 #define DMA_STATUS_CHAN1		BIT(1)
51 #define DMA_STATUS_CHAN0		BIT(0)
52 
53 /* DMA debug status bitmap */
54 #define DMA_DEBUG_STATUS_TS_MASK	0xf
55 #define DMA_DEBUG_STATUS_RS_MASK	0xf
56 
57 /* DMA AXI bitmap */
58 #define DMA_AXI_EN_LPI			BIT(31)
59 #define DMA_AXI_LPI_XIT_FRM		BIT(30)
60 #define DMA_AXI_WR_OSR_LMT		GENMASK(27, 24)
61 #define DMA_AXI_WR_OSR_LMT_SHIFT	24
62 #define DMA_AXI_RD_OSR_LMT		GENMASK(19, 16)
63 #define DMA_AXI_RD_OSR_LMT_SHIFT	16
64 
65 #define DMA_AXI_OSR_MAX			0xf
66 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
67 				(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
68 
69 #define DMA_SYS_BUS_MB			BIT(14)
70 #define DMA_AXI_1KBBE			BIT(13)
71 #define DMA_SYS_BUS_AAL			BIT(12)
72 #define DMA_SYS_BUS_EAME		BIT(11)
73 #define DMA_AXI_BLEN256			BIT(7)
74 #define DMA_AXI_BLEN128			BIT(6)
75 #define DMA_AXI_BLEN64			BIT(5)
76 #define DMA_AXI_BLEN32			BIT(4)
77 #define DMA_AXI_BLEN16			BIT(3)
78 #define DMA_AXI_BLEN8			BIT(2)
79 #define DMA_AXI_BLEN4			BIT(1)
80 #define DMA_SYS_BUS_FB			BIT(0)
81 
82 #define DMA_BURST_LEN_DEFAULT		(DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
83 					DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
84 					DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
85 					DMA_AXI_BLEN4)
86 
87 #define DMA_AXI_BURST_LEN_MASK		0x000000FE
88 
89 /* DMA TBS Control */
90 #define DMA_TBS_FTOS			GENMASK(31, 8)
91 #define DMA_TBS_FTOV			BIT(0)
92 #define DMA_TBS_DEF_FTOS		(DMA_TBS_FTOS | DMA_TBS_FTOV)
93 
94 /* Following DMA defines are chanels oriented */
95 #define DMA_CHAN_BASE_ADDR		0x00001100
96 #define DMA_CHAN_BASE_OFFSET		0x80
97 #define DMA_CHANX_BASE_ADDR(x)		(DMA_CHAN_BASE_ADDR + \
98 					(x * DMA_CHAN_BASE_OFFSET))
99 #define DMA_CHAN_REG_NUMBER		17
100 
101 #define DMA_CHAN_CONTROL(x)		DMA_CHANX_BASE_ADDR(x)
102 #define DMA_CHAN_TX_CONTROL(x)		(DMA_CHANX_BASE_ADDR(x) + 0x4)
103 #define DMA_CHAN_RX_CONTROL(x)		(DMA_CHANX_BASE_ADDR(x) + 0x8)
104 #define DMA_CHAN_TX_BASE_ADDR_HI(x)	(DMA_CHANX_BASE_ADDR(x) + 0x10)
105 #define DMA_CHAN_TX_BASE_ADDR(x)	(DMA_CHANX_BASE_ADDR(x) + 0x14)
106 #define DMA_CHAN_RX_BASE_ADDR_HI(x)	(DMA_CHANX_BASE_ADDR(x) + 0x18)
107 #define DMA_CHAN_RX_BASE_ADDR(x)	(DMA_CHANX_BASE_ADDR(x) + 0x1c)
108 #define DMA_CHAN_TX_END_ADDR(x)		(DMA_CHANX_BASE_ADDR(x) + 0x20)
109 #define DMA_CHAN_RX_END_ADDR(x)		(DMA_CHANX_BASE_ADDR(x) + 0x28)
110 #define DMA_CHAN_TX_RING_LEN(x)		(DMA_CHANX_BASE_ADDR(x) + 0x2c)
111 #define DMA_CHAN_RX_RING_LEN(x)		(DMA_CHANX_BASE_ADDR(x) + 0x30)
112 #define DMA_CHAN_INTR_ENA(x)		(DMA_CHANX_BASE_ADDR(x) + 0x34)
113 #define DMA_CHAN_RX_WATCHDOG(x)		(DMA_CHANX_BASE_ADDR(x) + 0x38)
114 #define DMA_CHAN_SLOT_CTRL_STATUS(x)	(DMA_CHANX_BASE_ADDR(x) + 0x3c)
115 #define DMA_CHAN_CUR_TX_DESC(x)		(DMA_CHANX_BASE_ADDR(x) + 0x44)
116 #define DMA_CHAN_CUR_RX_DESC(x)		(DMA_CHANX_BASE_ADDR(x) + 0x4c)
117 #define DMA_CHAN_CUR_TX_BUF_ADDR(x)	(DMA_CHANX_BASE_ADDR(x) + 0x54)
118 #define DMA_CHAN_CUR_RX_BUF_ADDR(x)	(DMA_CHANX_BASE_ADDR(x) + 0x5c)
119 #define DMA_CHAN_STATUS(x)		(DMA_CHANX_BASE_ADDR(x) + 0x60)
120 
121 /* DMA Control X */
122 #define DMA_CONTROL_SPH			BIT(24)
123 #define DMA_CONTROL_MSS_MASK		GENMASK(13, 0)
124 
125 /* DMA Tx Channel X Control register defines */
126 #define DMA_CONTROL_EDSE		BIT(28)
127 #define DMA_CONTROL_TSE			BIT(12)
128 #define DMA_CONTROL_OSP			BIT(4)
129 #define DMA_CONTROL_ST			BIT(0)
130 
131 /* DMA Rx Channel X Control register defines */
132 #define DMA_CONTROL_SR			BIT(0)
133 #define DMA_RBSZ_MASK			GENMASK(14, 1)
134 #define DMA_RBSZ_SHIFT			1
135 
136 /* Interrupt status per channel */
137 #define DMA_CHAN_STATUS_REB		GENMASK(21, 19)
138 #define DMA_CHAN_STATUS_REB_SHIFT	19
139 #define DMA_CHAN_STATUS_TEB		GENMASK(18, 16)
140 #define DMA_CHAN_STATUS_TEB_SHIFT	16
141 #define DMA_CHAN_STATUS_NIS		BIT(15)
142 #define DMA_CHAN_STATUS_AIS		BIT(14)
143 #define DMA_CHAN_STATUS_CDE		BIT(13)
144 #define DMA_CHAN_STATUS_FBE		BIT(12)
145 #define DMA_CHAN_STATUS_ERI		BIT(11)
146 #define DMA_CHAN_STATUS_ETI		BIT(10)
147 #define DMA_CHAN_STATUS_RWT		BIT(9)
148 #define DMA_CHAN_STATUS_RPS		BIT(8)
149 #define DMA_CHAN_STATUS_RBU		BIT(7)
150 #define DMA_CHAN_STATUS_RI		BIT(6)
151 #define DMA_CHAN_STATUS_TBU		BIT(2)
152 #define DMA_CHAN_STATUS_TPS		BIT(1)
153 #define DMA_CHAN_STATUS_TI		BIT(0)
154 
155 #define DMA_CHAN_STATUS_MSK_COMMON	(DMA_CHAN_STATUS_NIS | \
156 					 DMA_CHAN_STATUS_AIS | \
157 					 DMA_CHAN_STATUS_CDE | \
158 					 DMA_CHAN_STATUS_FBE)
159 
160 #define DMA_CHAN_STATUS_MSK_RX		(DMA_CHAN_STATUS_REB | \
161 					 DMA_CHAN_STATUS_ERI | \
162 					 DMA_CHAN_STATUS_RWT | \
163 					 DMA_CHAN_STATUS_RPS | \
164 					 DMA_CHAN_STATUS_RBU | \
165 					 DMA_CHAN_STATUS_RI | \
166 					 DMA_CHAN_STATUS_MSK_COMMON)
167 
168 #define DMA_CHAN_STATUS_MSK_TX		(DMA_CHAN_STATUS_ETI | \
169 					 DMA_CHAN_STATUS_TBU | \
170 					 DMA_CHAN_STATUS_TPS | \
171 					 DMA_CHAN_STATUS_TI | \
172 					 DMA_CHAN_STATUS_MSK_COMMON)
173 
174 /* Interrupt enable bits per channel */
175 #define DMA_CHAN_INTR_ENA_NIE		BIT(16)
176 #define DMA_CHAN_INTR_ENA_AIE		BIT(15)
177 #define DMA_CHAN_INTR_ENA_NIE_4_10	BIT(15)
178 #define DMA_CHAN_INTR_ENA_AIE_4_10	BIT(14)
179 #define DMA_CHAN_INTR_ENA_CDE		BIT(13)
180 #define DMA_CHAN_INTR_ENA_FBE		BIT(12)
181 #define DMA_CHAN_INTR_ENA_ERE		BIT(11)
182 #define DMA_CHAN_INTR_ENA_ETE		BIT(10)
183 #define DMA_CHAN_INTR_ENA_RWE		BIT(9)
184 #define DMA_CHAN_INTR_ENA_RSE		BIT(8)
185 #define DMA_CHAN_INTR_ENA_RBUE		BIT(7)
186 #define DMA_CHAN_INTR_ENA_RIE		BIT(6)
187 #define DMA_CHAN_INTR_ENA_TBUE		BIT(2)
188 #define DMA_CHAN_INTR_ENA_TSE		BIT(1)
189 #define DMA_CHAN_INTR_ENA_TIE		BIT(0)
190 
191 #define DMA_CHAN_INTR_NORMAL		(DMA_CHAN_INTR_ENA_NIE | \
192 					 DMA_CHAN_INTR_ENA_RIE | \
193 					 DMA_CHAN_INTR_ENA_TIE)
194 
195 #define DMA_CHAN_INTR_ABNORMAL		(DMA_CHAN_INTR_ENA_AIE | \
196 					 DMA_CHAN_INTR_ENA_FBE)
197 /* DMA default interrupt mask for 4.00 */
198 #define DMA_CHAN_INTR_DEFAULT_MASK	(DMA_CHAN_INTR_NORMAL | \
199 					 DMA_CHAN_INTR_ABNORMAL)
200 #define DMA_CHAN_INTR_DEFAULT_RX	(DMA_CHAN_INTR_ENA_RIE)
201 #define DMA_CHAN_INTR_DEFAULT_TX	(DMA_CHAN_INTR_ENA_TIE)
202 
203 #define DMA_CHAN_INTR_NORMAL_4_10	(DMA_CHAN_INTR_ENA_NIE_4_10 | \
204 					 DMA_CHAN_INTR_ENA_RIE | \
205 					 DMA_CHAN_INTR_ENA_TIE)
206 
207 #define DMA_CHAN_INTR_ABNORMAL_4_10	(DMA_CHAN_INTR_ENA_AIE_4_10 | \
208 					 DMA_CHAN_INTR_ENA_FBE)
209 /* DMA default interrupt mask for 4.10a */
210 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10	(DMA_CHAN_INTR_NORMAL_4_10 | \
211 					 DMA_CHAN_INTR_ABNORMAL_4_10)
212 #define DMA_CHAN_INTR_DEFAULT_RX_4_10	(DMA_CHAN_INTR_ENA_RIE)
213 #define DMA_CHAN_INTR_DEFAULT_TX_4_10	(DMA_CHAN_INTR_ENA_TIE)
214 
215 /* channel 0 specific fields */
216 #define DMA_CHAN0_DBG_STAT_TPS		GENMASK(15, 12)
217 #define DMA_CHAN0_DBG_STAT_TPS_SHIFT	12
218 #define DMA_CHAN0_DBG_STAT_RPS		GENMASK(11, 8)
219 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT	8
220 
221 int dwmac4_dma_reset(void __iomem *ioaddr);
222 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
223 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
224 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
225 void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
226 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan);
227 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan);
228 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan);
229 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan);
230 int dwmac4_dma_interrupt(void __iomem *ioaddr,
231 			 struct stmmac_extra_stats *x, u32 chan, u32 dir);
232 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
233 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
234 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
235 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
236 
237 #endif /* __DWMAC4_DMA_H__ */
238