1 /* 2 * DWMAC4 Header file. 3 * 4 * Copyright (C) 2015 STMicroelectronics Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * Author: Alexandre Torgue <alexandre.torgue@st.com> 11 */ 12 13 #ifndef __DWMAC4_H__ 14 #define __DWMAC4_H__ 15 16 #include "common.h" 17 18 /* MAC registers */ 19 #define GMAC_CONFIG 0x00000000 20 #define GMAC_PACKET_FILTER 0x00000008 21 #define GMAC_HASH_TAB_0_31 0x00000010 22 #define GMAC_HASH_TAB_32_63 0x00000014 23 #define GMAC_RX_FLOW_CTRL 0x00000090 24 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 25 #define GMAC_TXQ_PRTY_MAP0 0x98 26 #define GMAC_TXQ_PRTY_MAP1 0x9C 27 #define GMAC_RXQ_CTRL0 0x000000a0 28 #define GMAC_RXQ_CTRL1 0x000000a4 29 #define GMAC_RXQ_CTRL2 0x000000a8 30 #define GMAC_RXQ_CTRL3 0x000000ac 31 #define GMAC_INT_STATUS 0x000000b0 32 #define GMAC_INT_EN 0x000000b4 33 #define GMAC_1US_TIC_COUNTER 0x000000dc 34 #define GMAC_PCS_BASE 0x000000e0 35 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 36 #define GMAC_PMT 0x000000c0 37 #define GMAC_VERSION 0x00000110 38 #define GMAC_DEBUG 0x00000114 39 #define GMAC_HW_FEATURE0 0x0000011c 40 #define GMAC_HW_FEATURE1 0x00000120 41 #define GMAC_HW_FEATURE2 0x00000124 42 #define GMAC_HW_FEATURE3 0x00000128 43 #define GMAC_MDIO_ADDR 0x00000200 44 #define GMAC_MDIO_DATA 0x00000204 45 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 46 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 47 48 /* RX Queues Routing */ 49 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 50 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0 51 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 52 #define GMAC_RXQCTRL_PTPQ_SHIFT 4 53 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 54 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 55 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 56 #define GMAC_RXQCTRL_UPQ_SHIFT 12 57 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 58 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16 59 #define GMAC_RXQCTRL_MCBCQEN BIT(20) 60 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 61 #define GMAC_RXQCTRL_TACPQE BIT(21) 62 #define GMAC_RXQCTRL_TACPQE_SHIFT 21 63 64 /* MAC Packet Filtering */ 65 #define GMAC_PACKET_FILTER_PR BIT(0) 66 #define GMAC_PACKET_FILTER_HMC BIT(2) 67 #define GMAC_PACKET_FILTER_PM BIT(4) 68 69 #define GMAC_MAX_PERFECT_ADDRESSES 128 70 71 /* MAC RX Queue Enable */ 72 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 73 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 74 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 75 76 /* MAC Flow Control RX */ 77 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 78 79 /* RX Queues Priorities */ 80 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 81 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 82 83 /* TX Queues Priorities */ 84 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 85 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 86 87 /* MAC Flow Control TX */ 88 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 89 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 90 91 /* MAC Interrupt bitmap*/ 92 #define GMAC_INT_RGSMIIS BIT(0) 93 #define GMAC_INT_PCS_LINK BIT(1) 94 #define GMAC_INT_PCS_ANE BIT(2) 95 #define GMAC_INT_PCS_PHYIS BIT(3) 96 #define GMAC_INT_PMT_EN BIT(4) 97 #define GMAC_INT_LPI_EN BIT(5) 98 99 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 100 GMAC_INT_PCS_ANE) 101 102 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN) 103 104 enum dwmac4_irq_status { 105 time_stamp_irq = 0x00001000, 106 mmc_rx_csum_offload_irq = 0x00000800, 107 mmc_tx_irq = 0x00000400, 108 mmc_rx_irq = 0x00000200, 109 mmc_irq = 0x00000100, 110 lpi_irq = 0x00000020, 111 pmt_irq = 0x00000010, 112 }; 113 114 /* MAC PMT bitmap */ 115 enum power_event { 116 pointer_reset = 0x80000000, 117 global_unicast = 0x00000200, 118 wake_up_rx_frame = 0x00000040, 119 magic_frame = 0x00000020, 120 wake_up_frame_en = 0x00000004, 121 magic_pkt_en = 0x00000002, 122 power_down = 0x00000001, 123 }; 124 125 /* Energy Efficient Ethernet (EEE) for GMAC4 126 * 127 * LPI status, timer and control register offset 128 */ 129 #define GMAC4_LPI_CTRL_STATUS 0xd0 130 #define GMAC4_LPI_TIMER_CTRL 0xd4 131 132 /* LPI control and status defines */ 133 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */ 134 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 135 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 136 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 137 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 138 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 139 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 140 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 141 142 /* MAC Debug bitmap */ 143 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 144 #define GMAC_DEBUG_TFCSTS_SHIFT 17 145 #define GMAC_DEBUG_TFCSTS_IDLE 0 146 #define GMAC_DEBUG_TFCSTS_WAIT 1 147 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 148 #define GMAC_DEBUG_TFCSTS_XFER 3 149 #define GMAC_DEBUG_TPESTS BIT(16) 150 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 151 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 152 #define GMAC_DEBUG_RPESTS BIT(0) 153 154 /* MAC config */ 155 #define GMAC_CONFIG_IPC BIT(27) 156 #define GMAC_CONFIG_2K BIT(22) 157 #define GMAC_CONFIG_ACS BIT(20) 158 #define GMAC_CONFIG_BE BIT(18) 159 #define GMAC_CONFIG_JD BIT(17) 160 #define GMAC_CONFIG_JE BIT(16) 161 #define GMAC_CONFIG_PS BIT(15) 162 #define GMAC_CONFIG_FES BIT(14) 163 #define GMAC_CONFIG_DM BIT(13) 164 #define GMAC_CONFIG_DCRS BIT(9) 165 #define GMAC_CONFIG_TE BIT(1) 166 #define GMAC_CONFIG_RE BIT(0) 167 168 /* MAC HW features0 bitmap */ 169 #define GMAC_HW_FEAT_ADDMAC BIT(18) 170 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 171 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 172 #define GMAC_HW_FEAT_EEESEL BIT(13) 173 #define GMAC_HW_FEAT_TSSEL BIT(12) 174 #define GMAC_HW_FEAT_MMCSEL BIT(8) 175 #define GMAC_HW_FEAT_MGKSEL BIT(7) 176 #define GMAC_HW_FEAT_RWKSEL BIT(6) 177 #define GMAC_HW_FEAT_SMASEL BIT(5) 178 #define GMAC_HW_FEAT_VLHASH BIT(4) 179 #define GMAC_HW_FEAT_PCSSEL BIT(3) 180 #define GMAC_HW_FEAT_HDSEL BIT(2) 181 #define GMAC_HW_FEAT_GMIISEL BIT(1) 182 #define GMAC_HW_FEAT_MIISEL BIT(0) 183 184 /* MAC HW features1 bitmap */ 185 #define GMAC_HW_FEAT_AVSEL BIT(20) 186 #define GMAC_HW_TSOEN BIT(18) 187 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 188 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 189 190 /* MAC HW features2 bitmap */ 191 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 192 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 193 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 194 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 195 196 /* MAC HW features3 bitmap */ 197 #define GMAC_HW_FEAT_ASP GENMASK(29, 28) 198 199 /* MAC HW ADDR regs */ 200 #define GMAC_HI_DCS GENMASK(18, 16) 201 #define GMAC_HI_DCS_SHIFT 16 202 #define GMAC_HI_REG_AE BIT(31) 203 204 /* MTL registers */ 205 #define MTL_OPERATION_MODE 0x00000c00 206 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 207 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 208 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 209 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 210 #define MTL_OPERATION_SCHALG_SP (0x3 << 5) 211 #define MTL_OPERATION_RAA BIT(2) 212 #define MTL_OPERATION_RAA_SP (0x0 << 2) 213 #define MTL_OPERATION_RAA_WSP (0x1 << 2) 214 215 #define MTL_INT_STATUS 0x00000c20 216 #define MTL_INT_QX(x) BIT(x) 217 218 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 219 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 220 #define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0) 221 #define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0) 222 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x)) 223 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 224 225 #define MTL_CHAN_BASE_ADDR 0x00000d00 226 #define MTL_CHAN_BASE_OFFSET 0x40 227 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 228 (x * MTL_CHAN_BASE_OFFSET)) 229 230 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 231 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 232 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 233 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 234 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 235 236 #define MTL_OP_MODE_RSF BIT(5) 237 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 238 #define MTL_OP_MODE_TXQEN_AV BIT(2) 239 #define MTL_OP_MODE_TXQEN BIT(3) 240 #define MTL_OP_MODE_TSF BIT(1) 241 242 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 243 #define MTL_OP_MODE_TQS_SHIFT 16 244 245 #define MTL_OP_MODE_TTC_MASK 0x70 246 #define MTL_OP_MODE_TTC_SHIFT 4 247 248 #define MTL_OP_MODE_TTC_32 0 249 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 250 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 251 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 252 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 253 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 254 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 255 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 256 257 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 258 #define MTL_OP_MODE_RQS_SHIFT 20 259 260 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 261 #define MTL_OP_MODE_RFD_SHIFT 14 262 263 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 264 #define MTL_OP_MODE_RFA_SHIFT 8 265 266 #define MTL_OP_MODE_EHFC BIT(7) 267 268 #define MTL_OP_MODE_RTC_MASK 0x18 269 #define MTL_OP_MODE_RTC_SHIFT 3 270 271 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 272 #define MTL_OP_MODE_RTC_64 0 273 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 274 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 275 276 /* MTL ETS Control register */ 277 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 278 #define MTL_ETS_CTRL_BASE_OFFSET 0x40 279 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \ 280 ((x) * MTL_ETS_CTRL_BASE_OFFSET)) 281 282 #define MTL_ETS_CTRL_CC BIT(3) 283 #define MTL_ETS_CTRL_AVALG BIT(2) 284 285 /* MTL Queue Quantum Weight */ 286 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 287 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 288 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \ 289 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET)) 290 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 291 292 /* MTL sendSlopeCredit register */ 293 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 294 #define MTL_SEND_SLP_CRED_OFFSET 0x40 295 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \ 296 ((x) * MTL_SEND_SLP_CRED_OFFSET)) 297 298 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 299 300 /* MTL hiCredit register */ 301 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 302 #define MTL_HIGH_CRED_OFFSET 0x40 303 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \ 304 ((x) * MTL_HIGH_CRED_OFFSET)) 305 306 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 307 308 /* MTL loCredit register */ 309 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24 310 #define MTL_LOW_CRED_OFFSET 0x40 311 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \ 312 ((x) * MTL_LOW_CRED_OFFSET)) 313 314 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 315 316 /* MTL debug */ 317 #define MTL_DEBUG_TXSTSFSTS BIT(5) 318 #define MTL_DEBUG_TXFSTS BIT(4) 319 #define MTL_DEBUG_TWCSTS BIT(3) 320 321 /* MTL debug: Tx FIFO Read Controller Status */ 322 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 323 #define MTL_DEBUG_TRCSTS_SHIFT 1 324 #define MTL_DEBUG_TRCSTS_IDLE 0 325 #define MTL_DEBUG_TRCSTS_READ 1 326 #define MTL_DEBUG_TRCSTS_TXW 2 327 #define MTL_DEBUG_TRCSTS_WRITE 3 328 #define MTL_DEBUG_TXPAUSED BIT(0) 329 330 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 331 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 332 #define MTL_DEBUG_RXFSTS_SHIFT 4 333 #define MTL_DEBUG_RXFSTS_EMPTY 0 334 #define MTL_DEBUG_RXFSTS_BT 1 335 #define MTL_DEBUG_RXFSTS_AT 2 336 #define MTL_DEBUG_RXFSTS_FULL 3 337 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 338 #define MTL_DEBUG_RRCSTS_SHIFT 1 339 #define MTL_DEBUG_RRCSTS_IDLE 0 340 #define MTL_DEBUG_RRCSTS_RDATA 1 341 #define MTL_DEBUG_RRCSTS_RSTAT 2 342 #define MTL_DEBUG_RRCSTS_FLUSH 3 343 #define MTL_DEBUG_RWCSTS BIT(0) 344 345 /* MTL interrupt */ 346 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 347 #define MTL_RX_OVERFLOW_INT BIT(16) 348 349 /* Default operating mode of the MAC */ 350 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 351 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS) 352 353 /* To dump the core regs excluding the Address Registers */ 354 #define GMAC_REG_NUM 132 355 356 /* MTL debug */ 357 #define MTL_DEBUG_TXSTSFSTS BIT(5) 358 #define MTL_DEBUG_TXFSTS BIT(4) 359 #define MTL_DEBUG_TWCSTS BIT(3) 360 361 /* MTL debug: Tx FIFO Read Controller Status */ 362 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 363 #define MTL_DEBUG_TRCSTS_SHIFT 1 364 #define MTL_DEBUG_TRCSTS_IDLE 0 365 #define MTL_DEBUG_TRCSTS_READ 1 366 #define MTL_DEBUG_TRCSTS_TXW 2 367 #define MTL_DEBUG_TRCSTS_WRITE 3 368 #define MTL_DEBUG_TXPAUSED BIT(0) 369 370 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 371 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 372 #define MTL_DEBUG_RXFSTS_SHIFT 4 373 #define MTL_DEBUG_RXFSTS_EMPTY 0 374 #define MTL_DEBUG_RXFSTS_BT 1 375 #define MTL_DEBUG_RXFSTS_AT 2 376 #define MTL_DEBUG_RXFSTS_FULL 3 377 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 378 #define MTL_DEBUG_RRCSTS_SHIFT 1 379 #define MTL_DEBUG_RRCSTS_IDLE 0 380 #define MTL_DEBUG_RRCSTS_RDATA 1 381 #define MTL_DEBUG_RRCSTS_RSTAT 2 382 #define MTL_DEBUG_RRCSTS_FLUSH 3 383 #define MTL_DEBUG_RWCSTS BIT(0) 384 385 /* SGMII/RGMII status register */ 386 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 387 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 388 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 389 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 390 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 391 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 392 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 393 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 394 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 395 /* LNKMOD */ 396 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 397 /* LNKSPEED */ 398 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 399 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 400 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 401 402 extern const struct stmmac_dma_ops dwmac4_dma_ops; 403 extern const struct stmmac_dma_ops dwmac410_dma_ops; 404 #endif /* __DWMAC4_H__ */ 405