1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * DWMAC4 Header file.
4  *
5  * Copyright (C) 2015  STMicroelectronics Ltd
6  *
7  * Author: Alexandre Torgue <alexandre.torgue@st.com>
8  */
9 
10 #ifndef __DWMAC4_H__
11 #define __DWMAC4_H__
12 
13 #include "common.h"
14 
15 /*  MAC registers */
16 #define GMAC_CONFIG			0x00000000
17 #define GMAC_EXT_CONFIG			0x00000004
18 #define GMAC_PACKET_FILTER		0x00000008
19 #define GMAC_HASH_TAB(x)		(0x10 + (x) * 4)
20 #define GMAC_VLAN_TAG			0x00000050
21 #define GMAC_VLAN_HASH_TABLE		0x00000058
22 #define GMAC_RX_FLOW_CTRL		0x00000090
23 #define GMAC_VLAN_INCL			0x00000060
24 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
25 #define GMAC_TXQ_PRTY_MAP0		0x98
26 #define GMAC_TXQ_PRTY_MAP1		0x9C
27 #define GMAC_RXQ_CTRL0			0x000000a0
28 #define GMAC_RXQ_CTRL1			0x000000a4
29 #define GMAC_RXQ_CTRL2			0x000000a8
30 #define GMAC_RXQ_CTRL3			0x000000ac
31 #define GMAC_INT_STATUS			0x000000b0
32 #define GMAC_INT_EN			0x000000b4
33 #define GMAC_1US_TIC_COUNTER		0x000000dc
34 #define GMAC_PCS_BASE			0x000000e0
35 #define GMAC_PHYIF_CONTROL_STATUS	0x000000f8
36 #define GMAC_PMT			0x000000c0
37 #define GMAC_DEBUG			0x00000114
38 #define GMAC_HW_FEATURE0		0x0000011c
39 #define GMAC_HW_FEATURE1		0x00000120
40 #define GMAC_HW_FEATURE2		0x00000124
41 #define GMAC_HW_FEATURE3		0x00000128
42 #define GMAC_MDIO_ADDR			0x00000200
43 #define GMAC_MDIO_DATA			0x00000204
44 #define GMAC_ARP_ADDR			0x00000210
45 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
46 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
47 #define GMAC_L3L4_CTRL(reg)		(0x900 + (reg) * 0x30)
48 #define GMAC_L4_ADDR(reg)		(0x904 + (reg) * 0x30)
49 #define GMAC_L3_ADDR0(reg)		(0x910 + (reg) * 0x30)
50 #define GMAC_L3_ADDR1(reg)		(0x914 + (reg) * 0x30)
51 
52 /* RX Queues Routing */
53 #define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
54 #define GMAC_RXQCTRL_AVCPQ_SHIFT	0
55 #define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
56 #define GMAC_RXQCTRL_PTPQ_SHIFT		4
57 #define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
58 #define GMAC_RXQCTRL_DCBCPQ_SHIFT	8
59 #define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
60 #define GMAC_RXQCTRL_UPQ_SHIFT		12
61 #define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
62 #define GMAC_RXQCTRL_MCBCQ_SHIFT	16
63 #define GMAC_RXQCTRL_MCBCQEN		BIT(20)
64 #define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
65 #define GMAC_RXQCTRL_TACPQE		BIT(21)
66 #define GMAC_RXQCTRL_TACPQE_SHIFT	21
67 #define GMAC_RXQCTRL_FPRQ		GENMASK(26, 24)
68 #define GMAC_RXQCTRL_FPRQ_SHIFT		24
69 
70 /* MAC Packet Filtering */
71 #define GMAC_PACKET_FILTER_PR		BIT(0)
72 #define GMAC_PACKET_FILTER_HMC		BIT(2)
73 #define GMAC_PACKET_FILTER_PM		BIT(4)
74 #define GMAC_PACKET_FILTER_PCF		BIT(7)
75 #define GMAC_PACKET_FILTER_HPF		BIT(10)
76 #define GMAC_PACKET_FILTER_VTFE		BIT(16)
77 #define GMAC_PACKET_FILTER_IPFE		BIT(20)
78 
79 #define GMAC_MAX_PERFECT_ADDRESSES	128
80 
81 /* MAC VLAN */
82 #define GMAC_VLAN_EDVLP			BIT(26)
83 #define GMAC_VLAN_VTHM			BIT(25)
84 #define GMAC_VLAN_DOVLTC		BIT(20)
85 #define GMAC_VLAN_ESVL			BIT(18)
86 #define GMAC_VLAN_ETV			BIT(16)
87 #define GMAC_VLAN_VID			GENMASK(15, 0)
88 #define GMAC_VLAN_VLTI			BIT(20)
89 #define GMAC_VLAN_CSVL			BIT(19)
90 #define GMAC_VLAN_VLC			GENMASK(17, 16)
91 #define GMAC_VLAN_VLC_SHIFT		16
92 
93 /* MAC RX Queue Enable */
94 #define GMAC_RX_QUEUE_CLEAR(queue)	~(GENMASK(1, 0) << ((queue) * 2))
95 #define GMAC_RX_AV_QUEUE_ENABLE(queue)	BIT((queue) * 2)
96 #define GMAC_RX_DCB_QUEUE_ENABLE(queue)	BIT(((queue) * 2) + 1)
97 
98 /* MAC Flow Control RX */
99 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
100 
101 /* RX Queues Priorities */
102 #define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
103 #define GMAC_RXQCTRL_PSRQX_SHIFT(x)	((x) * 8)
104 
105 /* TX Queues Priorities */
106 #define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
107 #define GMAC_TXQCTRL_PSTQX_SHIFT(x)	((x) * 8)
108 
109 /* MAC Flow Control TX */
110 #define GMAC_TX_FLOW_CTRL_TFE		BIT(1)
111 #define GMAC_TX_FLOW_CTRL_PT_SHIFT	16
112 
113 /*  MAC Interrupt bitmap*/
114 #define GMAC_INT_RGSMIIS		BIT(0)
115 #define GMAC_INT_PCS_LINK		BIT(1)
116 #define GMAC_INT_PCS_ANE		BIT(2)
117 #define GMAC_INT_PCS_PHYIS		BIT(3)
118 #define GMAC_INT_PMT_EN			BIT(4)
119 #define GMAC_INT_LPI_EN			BIT(5)
120 
121 #define	GMAC_PCS_IRQ_DEFAULT	(GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK |	\
122 				 GMAC_INT_PCS_ANE)
123 
124 #define	GMAC_INT_DEFAULT_ENABLE	(GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
125 
126 enum dwmac4_irq_status {
127 	time_stamp_irq = 0x00001000,
128 	mmc_rx_csum_offload_irq = 0x00000800,
129 	mmc_tx_irq = 0x00000400,
130 	mmc_rx_irq = 0x00000200,
131 	mmc_irq = 0x00000100,
132 	lpi_irq = 0x00000020,
133 	pmt_irq = 0x00000010,
134 };
135 
136 /* MAC PMT bitmap */
137 enum power_event {
138 	pointer_reset =	0x80000000,
139 	global_unicast = 0x00000200,
140 	wake_up_rx_frame = 0x00000040,
141 	magic_frame = 0x00000020,
142 	wake_up_frame_en = 0x00000004,
143 	magic_pkt_en = 0x00000002,
144 	power_down = 0x00000001,
145 };
146 
147 /* Energy Efficient Ethernet (EEE) for GMAC4
148  *
149  * LPI status, timer and control register offset
150  */
151 #define GMAC4_LPI_CTRL_STATUS	0xd0
152 #define GMAC4_LPI_TIMER_CTRL	0xd4
153 
154 /* LPI control and status defines */
155 #define GMAC4_LPI_CTRL_STATUS_LPITCSE	BIT(21)	/* LPI Tx Clock Stop Enable */
156 #define GMAC4_LPI_CTRL_STATUS_LPITXA	BIT(19)	/* Enable LPI TX Automate */
157 #define GMAC4_LPI_CTRL_STATUS_PLS	BIT(17) /* PHY Link Status */
158 #define GMAC4_LPI_CTRL_STATUS_LPIEN	BIT(16)	/* LPI Enable */
159 #define GMAC4_LPI_CTRL_STATUS_RLPIEX	BIT(3) /* Receive LPI Exit */
160 #define GMAC4_LPI_CTRL_STATUS_RLPIEN	BIT(2) /* Receive LPI Entry */
161 #define GMAC4_LPI_CTRL_STATUS_TLPIEX	BIT(1) /* Transmit LPI Exit */
162 #define GMAC4_LPI_CTRL_STATUS_TLPIEN	BIT(0) /* Transmit LPI Entry */
163 
164 /* MAC Debug bitmap */
165 #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
166 #define GMAC_DEBUG_TFCSTS_SHIFT		17
167 #define GMAC_DEBUG_TFCSTS_IDLE		0
168 #define GMAC_DEBUG_TFCSTS_WAIT		1
169 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
170 #define GMAC_DEBUG_TFCSTS_XFER		3
171 #define GMAC_DEBUG_TPESTS		BIT(16)
172 #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
173 #define GMAC_DEBUG_RFCFCSTS_SHIFT	1
174 #define GMAC_DEBUG_RPESTS		BIT(0)
175 
176 /* MAC config */
177 #define GMAC_CONFIG_ARPEN		BIT(31)
178 #define GMAC_CONFIG_SARC		GENMASK(30, 28)
179 #define GMAC_CONFIG_SARC_SHIFT		28
180 #define GMAC_CONFIG_IPC			BIT(27)
181 #define GMAC_CONFIG_IPG			GENMASK(26, 24)
182 #define GMAC_CONFIG_IPG_SHIFT		24
183 #define GMAC_CONFIG_2K			BIT(22)
184 #define GMAC_CONFIG_ACS			BIT(20)
185 #define GMAC_CONFIG_BE			BIT(18)
186 #define GMAC_CONFIG_JD			BIT(17)
187 #define GMAC_CONFIG_JE			BIT(16)
188 #define GMAC_CONFIG_PS			BIT(15)
189 #define GMAC_CONFIG_FES			BIT(14)
190 #define GMAC_CONFIG_FES_SHIFT		14
191 #define GMAC_CONFIG_DM			BIT(13)
192 #define GMAC_CONFIG_LM			BIT(12)
193 #define GMAC_CONFIG_DCRS		BIT(9)
194 #define GMAC_CONFIG_TE			BIT(1)
195 #define GMAC_CONFIG_RE			BIT(0)
196 
197 /* MAC extended config */
198 #define GMAC_CONFIG_EIPG		GENMASK(29, 25)
199 #define GMAC_CONFIG_EIPG_SHIFT		25
200 #define GMAC_CONFIG_EIPG_EN		BIT(24)
201 #define GMAC_CONFIG_HDSMS		GENMASK(22, 20)
202 #define GMAC_CONFIG_HDSMS_SHIFT		20
203 #define GMAC_CONFIG_HDSMS_256		(0x2 << GMAC_CONFIG_HDSMS_SHIFT)
204 
205 /* MAC HW features0 bitmap */
206 #define GMAC_HW_FEAT_SAVLANINS		BIT(27)
207 #define GMAC_HW_FEAT_ADDMAC		BIT(18)
208 #define GMAC_HW_FEAT_RXCOESEL		BIT(16)
209 #define GMAC_HW_FEAT_TXCOSEL		BIT(14)
210 #define GMAC_HW_FEAT_EEESEL		BIT(13)
211 #define GMAC_HW_FEAT_TSSEL		BIT(12)
212 #define GMAC_HW_FEAT_ARPOFFSEL		BIT(9)
213 #define GMAC_HW_FEAT_MMCSEL		BIT(8)
214 #define GMAC_HW_FEAT_MGKSEL		BIT(7)
215 #define GMAC_HW_FEAT_RWKSEL		BIT(6)
216 #define GMAC_HW_FEAT_SMASEL		BIT(5)
217 #define GMAC_HW_FEAT_VLHASH		BIT(4)
218 #define GMAC_HW_FEAT_PCSSEL		BIT(3)
219 #define GMAC_HW_FEAT_HDSEL		BIT(2)
220 #define GMAC_HW_FEAT_GMIISEL		BIT(1)
221 #define GMAC_HW_FEAT_MIISEL		BIT(0)
222 
223 /* MAC HW features1 bitmap */
224 #define GMAC_HW_FEAT_L3L4FNUM		GENMASK(30, 27)
225 #define GMAC_HW_HASH_TB_SZ		GENMASK(25, 24)
226 #define GMAC_HW_FEAT_AVSEL		BIT(20)
227 #define GMAC_HW_TSOEN			BIT(18)
228 #define GMAC_HW_FEAT_SPHEN		BIT(17)
229 #define GMAC_HW_ADDR64			GENMASK(15, 14)
230 #define GMAC_HW_TXFIFOSIZE		GENMASK(10, 6)
231 #define GMAC_HW_RXFIFOSIZE		GENMASK(4, 0)
232 
233 /* MAC HW features2 bitmap */
234 #define GMAC_HW_FEAT_PPSOUTNUM		GENMASK(26, 24)
235 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
236 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
237 #define GMAC_HW_FEAT_TXQCNT		GENMASK(9, 6)
238 #define GMAC_HW_FEAT_RXQCNT		GENMASK(3, 0)
239 
240 /* MAC HW features3 bitmap */
241 #define GMAC_HW_FEAT_ASP		GENMASK(29, 28)
242 #define GMAC_HW_FEAT_TBSSEL		BIT(27)
243 #define GMAC_HW_FEAT_FPESEL		BIT(26)
244 #define GMAC_HW_FEAT_ESTWID		GENMASK(21, 20)
245 #define GMAC_HW_FEAT_ESTDEP		GENMASK(19, 17)
246 #define GMAC_HW_FEAT_ESTSEL		BIT(16)
247 #define GMAC_HW_FEAT_FRPES		GENMASK(14, 13)
248 #define GMAC_HW_FEAT_FRPBS		GENMASK(12, 11)
249 #define GMAC_HW_FEAT_FRPSEL		BIT(10)
250 #define GMAC_HW_FEAT_DVLAN		BIT(5)
251 
252 /* MAC HW ADDR regs */
253 #define GMAC_HI_DCS			GENMASK(18, 16)
254 #define GMAC_HI_DCS_SHIFT		16
255 #define GMAC_HI_REG_AE			BIT(31)
256 
257 /* L3/L4 Filters regs */
258 #define GMAC_L4DPIM0			BIT(21)
259 #define GMAC_L4DPM0			BIT(20)
260 #define GMAC_L4SPIM0			BIT(19)
261 #define GMAC_L4SPM0			BIT(18)
262 #define GMAC_L4PEN0			BIT(16)
263 #define GMAC_L3DAIM0			BIT(5)
264 #define GMAC_L3DAM0			BIT(4)
265 #define GMAC_L3SAIM0			BIT(3)
266 #define GMAC_L3SAM0			BIT(2)
267 #define GMAC_L3PEN0			BIT(0)
268 #define GMAC_L4DP0			GENMASK(31, 16)
269 #define GMAC_L4DP0_SHIFT		16
270 #define GMAC_L4SP0			GENMASK(15, 0)
271 
272 /*  MTL registers */
273 #define MTL_OPERATION_MODE		0x00000c00
274 #define MTL_FRPE			BIT(15)
275 #define MTL_OPERATION_SCHALG_MASK	GENMASK(6, 5)
276 #define MTL_OPERATION_SCHALG_WRR	(0x0 << 5)
277 #define MTL_OPERATION_SCHALG_WFQ	(0x1 << 5)
278 #define MTL_OPERATION_SCHALG_DWRR	(0x2 << 5)
279 #define MTL_OPERATION_SCHALG_SP		(0x3 << 5)
280 #define MTL_OPERATION_RAA		BIT(2)
281 #define MTL_OPERATION_RAA_SP		(0x0 << 2)
282 #define MTL_OPERATION_RAA_WSP		(0x1 << 2)
283 
284 #define MTL_INT_STATUS			0x00000c20
285 #define MTL_INT_QX(x)			BIT(x)
286 
287 #define MTL_RXQ_DMA_MAP0		0x00000c30 /* queue 0 to 3 */
288 #define MTL_RXQ_DMA_MAP1		0x00000c34 /* queue 4 to 7 */
289 #define MTL_RXQ_DMA_Q04MDMACH_MASK	GENMASK(3, 0)
290 #define MTL_RXQ_DMA_Q04MDMACH(x)	((x) << 0)
291 #define MTL_RXQ_DMA_QXMDMACH_MASK(x)	GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
292 #define MTL_RXQ_DMA_QXMDMACH(chan, q)	((chan) << (8 * (q)))
293 
294 #define MTL_CHAN_BASE_ADDR		0x00000d00
295 #define MTL_CHAN_BASE_OFFSET		0x40
296 #define MTL_CHANX_BASE_ADDR(x)		(MTL_CHAN_BASE_ADDR + \
297 					(x * MTL_CHAN_BASE_OFFSET))
298 
299 #define MTL_CHAN_TX_OP_MODE(x)		MTL_CHANX_BASE_ADDR(x)
300 #define MTL_CHAN_TX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x8)
301 #define MTL_CHAN_INT_CTRL(x)		(MTL_CHANX_BASE_ADDR(x) + 0x2c)
302 #define MTL_CHAN_RX_OP_MODE(x)		(MTL_CHANX_BASE_ADDR(x) + 0x30)
303 #define MTL_CHAN_RX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x38)
304 
305 #define MTL_OP_MODE_RSF			BIT(5)
306 #define MTL_OP_MODE_TXQEN_MASK		GENMASK(3, 2)
307 #define MTL_OP_MODE_TXQEN_AV		BIT(2)
308 #define MTL_OP_MODE_TXQEN		BIT(3)
309 #define MTL_OP_MODE_TSF			BIT(1)
310 
311 #define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
312 #define MTL_OP_MODE_TQS_SHIFT		16
313 
314 #define MTL_OP_MODE_TTC_MASK		0x70
315 #define MTL_OP_MODE_TTC_SHIFT		4
316 
317 #define MTL_OP_MODE_TTC_32		0
318 #define MTL_OP_MODE_TTC_64		(1 << MTL_OP_MODE_TTC_SHIFT)
319 #define MTL_OP_MODE_TTC_96		(2 << MTL_OP_MODE_TTC_SHIFT)
320 #define MTL_OP_MODE_TTC_128		(3 << MTL_OP_MODE_TTC_SHIFT)
321 #define MTL_OP_MODE_TTC_192		(4 << MTL_OP_MODE_TTC_SHIFT)
322 #define MTL_OP_MODE_TTC_256		(5 << MTL_OP_MODE_TTC_SHIFT)
323 #define MTL_OP_MODE_TTC_384		(6 << MTL_OP_MODE_TTC_SHIFT)
324 #define MTL_OP_MODE_TTC_512		(7 << MTL_OP_MODE_TTC_SHIFT)
325 
326 #define MTL_OP_MODE_RQS_MASK		GENMASK(29, 20)
327 #define MTL_OP_MODE_RQS_SHIFT		20
328 
329 #define MTL_OP_MODE_RFD_MASK		GENMASK(19, 14)
330 #define MTL_OP_MODE_RFD_SHIFT		14
331 
332 #define MTL_OP_MODE_RFA_MASK		GENMASK(13, 8)
333 #define MTL_OP_MODE_RFA_SHIFT		8
334 
335 #define MTL_OP_MODE_EHFC		BIT(7)
336 
337 #define MTL_OP_MODE_RTC_MASK		0x18
338 #define MTL_OP_MODE_RTC_SHIFT		3
339 
340 #define MTL_OP_MODE_RTC_32		(1 << MTL_OP_MODE_RTC_SHIFT)
341 #define MTL_OP_MODE_RTC_64		0
342 #define MTL_OP_MODE_RTC_96		(2 << MTL_OP_MODE_RTC_SHIFT)
343 #define MTL_OP_MODE_RTC_128		(3 << MTL_OP_MODE_RTC_SHIFT)
344 
345 /* MTL ETS Control register */
346 #define MTL_ETS_CTRL_BASE_ADDR		0x00000d10
347 #define MTL_ETS_CTRL_BASE_OFFSET	0x40
348 #define MTL_ETSX_CTRL_BASE_ADDR(x)	(MTL_ETS_CTRL_BASE_ADDR + \
349 					((x) * MTL_ETS_CTRL_BASE_OFFSET))
350 
351 #define MTL_ETS_CTRL_CC			BIT(3)
352 #define MTL_ETS_CTRL_AVALG		BIT(2)
353 
354 /* MTL Queue Quantum Weight */
355 #define MTL_TXQ_WEIGHT_BASE_ADDR	0x00000d18
356 #define MTL_TXQ_WEIGHT_BASE_OFFSET	0x40
357 #define MTL_TXQX_WEIGHT_BASE_ADDR(x)	(MTL_TXQ_WEIGHT_BASE_ADDR + \
358 					((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
359 #define MTL_TXQ_WEIGHT_ISCQW_MASK	GENMASK(20, 0)
360 
361 /* MTL sendSlopeCredit register */
362 #define MTL_SEND_SLP_CRED_BASE_ADDR	0x00000d1c
363 #define MTL_SEND_SLP_CRED_OFFSET	0x40
364 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x)	(MTL_SEND_SLP_CRED_BASE_ADDR + \
365 					((x) * MTL_SEND_SLP_CRED_OFFSET))
366 
367 #define MTL_SEND_SLP_CRED_SSC_MASK	GENMASK(13, 0)
368 
369 /* MTL hiCredit register */
370 #define MTL_HIGH_CRED_BASE_ADDR		0x00000d20
371 #define MTL_HIGH_CRED_OFFSET		0x40
372 #define MTL_HIGH_CREDX_BASE_ADDR(x)	(MTL_HIGH_CRED_BASE_ADDR + \
373 					((x) * MTL_HIGH_CRED_OFFSET))
374 
375 #define MTL_HIGH_CRED_HC_MASK		GENMASK(28, 0)
376 
377 /* MTL loCredit register */
378 #define MTL_LOW_CRED_BASE_ADDR		0x00000d24
379 #define MTL_LOW_CRED_OFFSET		0x40
380 #define MTL_LOW_CREDX_BASE_ADDR(x)	(MTL_LOW_CRED_BASE_ADDR + \
381 					((x) * MTL_LOW_CRED_OFFSET))
382 
383 #define MTL_HIGH_CRED_LC_MASK		GENMASK(28, 0)
384 
385 /*  MTL debug */
386 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
387 #define MTL_DEBUG_TXFSTS		BIT(4)
388 #define MTL_DEBUG_TWCSTS		BIT(3)
389 
390 /* MTL debug: Tx FIFO Read Controller Status */
391 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
392 #define MTL_DEBUG_TRCSTS_SHIFT		1
393 #define MTL_DEBUG_TRCSTS_IDLE		0
394 #define MTL_DEBUG_TRCSTS_READ		1
395 #define MTL_DEBUG_TRCSTS_TXW		2
396 #define MTL_DEBUG_TRCSTS_WRITE		3
397 #define MTL_DEBUG_TXPAUSED		BIT(0)
398 
399 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
400 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
401 #define MTL_DEBUG_RXFSTS_SHIFT		4
402 #define MTL_DEBUG_RXFSTS_EMPTY		0
403 #define MTL_DEBUG_RXFSTS_BT		1
404 #define MTL_DEBUG_RXFSTS_AT		2
405 #define MTL_DEBUG_RXFSTS_FULL		3
406 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
407 #define MTL_DEBUG_RRCSTS_SHIFT		1
408 #define MTL_DEBUG_RRCSTS_IDLE		0
409 #define MTL_DEBUG_RRCSTS_RDATA		1
410 #define MTL_DEBUG_RRCSTS_RSTAT		2
411 #define MTL_DEBUG_RRCSTS_FLUSH		3
412 #define MTL_DEBUG_RWCSTS		BIT(0)
413 
414 /*  MTL interrupt */
415 #define MTL_RX_OVERFLOW_INT_EN		BIT(24)
416 #define MTL_RX_OVERFLOW_INT		BIT(16)
417 
418 /* Default operating mode of the MAC */
419 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
420 			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
421 			GMAC_CONFIG_JE)
422 
423 /* To dump the core regs excluding  the Address Registers */
424 #define	GMAC_REG_NUM	132
425 
426 /*  MTL debug */
427 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
428 #define MTL_DEBUG_TXFSTS		BIT(4)
429 #define MTL_DEBUG_TWCSTS		BIT(3)
430 
431 /* MTL debug: Tx FIFO Read Controller Status */
432 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
433 #define MTL_DEBUG_TRCSTS_SHIFT		1
434 #define MTL_DEBUG_TRCSTS_IDLE		0
435 #define MTL_DEBUG_TRCSTS_READ		1
436 #define MTL_DEBUG_TRCSTS_TXW		2
437 #define MTL_DEBUG_TRCSTS_WRITE		3
438 #define MTL_DEBUG_TXPAUSED		BIT(0)
439 
440 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
441 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
442 #define MTL_DEBUG_RXFSTS_SHIFT		4
443 #define MTL_DEBUG_RXFSTS_EMPTY		0
444 #define MTL_DEBUG_RXFSTS_BT		1
445 #define MTL_DEBUG_RXFSTS_AT		2
446 #define MTL_DEBUG_RXFSTS_FULL		3
447 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
448 #define MTL_DEBUG_RRCSTS_SHIFT		1
449 #define MTL_DEBUG_RRCSTS_IDLE		0
450 #define MTL_DEBUG_RRCSTS_RDATA		1
451 #define MTL_DEBUG_RRCSTS_RSTAT		2
452 #define MTL_DEBUG_RRCSTS_FLUSH		3
453 #define MTL_DEBUG_RWCSTS		BIT(0)
454 
455 /* SGMII/RGMII status register */
456 #define GMAC_PHYIF_CTRLSTATUS_TC		BIT(0)
457 #define GMAC_PHYIF_CTRLSTATUS_LUD		BIT(1)
458 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS		BIT(4)
459 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD		BIT(16)
460 #define GMAC_PHYIF_CTRLSTATUS_SPEED		GENMASK(18, 17)
461 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT	17
462 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS		BIT(19)
463 #define GMAC_PHYIF_CTRLSTATUS_JABTO		BIT(20)
464 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET	BIT(21)
465 /* LNKMOD */
466 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK	0x1
467 /* LNKSPEED */
468 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125		0x2
469 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25		0x1
470 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5		0x0
471 
472 extern const struct stmmac_dma_ops dwmac4_dma_ops;
473 extern const struct stmmac_dma_ops dwmac410_dma_ops;
474 #endif /* __DWMAC4_H__ */
475