1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 Header file. 4 * 5 * Copyright (C) 2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_H__ 11 #define __DWMAC4_H__ 12 13 #include "common.h" 14 15 /* MAC registers */ 16 #define GMAC_CONFIG 0x00000000 17 #define GMAC_EXT_CONFIG 0x00000004 18 #define GMAC_PACKET_FILTER 0x00000008 19 #define GMAC_HASH_TAB(x) (0x10 + (x) * 4) 20 #define GMAC_VLAN_TAG 0x00000050 21 #define GMAC_VLAN_TAG_DATA 0x00000054 22 #define GMAC_VLAN_HASH_TABLE 0x00000058 23 #define GMAC_RX_FLOW_CTRL 0x00000090 24 #define GMAC_VLAN_INCL 0x00000060 25 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 26 #define GMAC_TXQ_PRTY_MAP0 0x98 27 #define GMAC_TXQ_PRTY_MAP1 0x9C 28 #define GMAC_RXQ_CTRL0 0x000000a0 29 #define GMAC_RXQ_CTRL1 0x000000a4 30 #define GMAC_RXQ_CTRL2 0x000000a8 31 #define GMAC_RXQ_CTRL3 0x000000ac 32 #define GMAC_INT_STATUS 0x000000b0 33 #define GMAC_INT_EN 0x000000b4 34 #define GMAC_1US_TIC_COUNTER 0x000000dc 35 #define GMAC_PCS_BASE 0x000000e0 36 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 37 #define GMAC_PMT 0x000000c0 38 #define GMAC_DEBUG 0x00000114 39 #define GMAC_HW_FEATURE0 0x0000011c 40 #define GMAC_HW_FEATURE1 0x00000120 41 #define GMAC_HW_FEATURE2 0x00000124 42 #define GMAC_HW_FEATURE3 0x00000128 43 #define GMAC_MDIO_ADDR 0x00000200 44 #define GMAC_MDIO_DATA 0x00000204 45 #define GMAC_GPIO_STATUS 0x0000020C 46 #define GMAC_ARP_ADDR 0x00000210 47 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 48 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 49 #define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30) 50 #define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30) 51 #define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30) 52 #define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30) 53 #define GMAC_TIMESTAMP_STATUS 0x00000b20 54 55 /* RX Queues Routing */ 56 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 57 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0 58 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 59 #define GMAC_RXQCTRL_PTPQ_SHIFT 4 60 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 61 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 62 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 63 #define GMAC_RXQCTRL_UPQ_SHIFT 12 64 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 65 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16 66 #define GMAC_RXQCTRL_MCBCQEN BIT(20) 67 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 68 #define GMAC_RXQCTRL_TACPQE BIT(21) 69 #define GMAC_RXQCTRL_TACPQE_SHIFT 21 70 #define GMAC_RXQCTRL_FPRQ GENMASK(26, 24) 71 #define GMAC_RXQCTRL_FPRQ_SHIFT 24 72 73 /* MAC Packet Filtering */ 74 #define GMAC_PACKET_FILTER_PR BIT(0) 75 #define GMAC_PACKET_FILTER_HMC BIT(2) 76 #define GMAC_PACKET_FILTER_PM BIT(4) 77 #define GMAC_PACKET_FILTER_PCF BIT(7) 78 #define GMAC_PACKET_FILTER_HPF BIT(10) 79 #define GMAC_PACKET_FILTER_VTFE BIT(16) 80 #define GMAC_PACKET_FILTER_IPFE BIT(20) 81 #define GMAC_PACKET_FILTER_RA BIT(31) 82 83 #define GMAC_MAX_PERFECT_ADDRESSES 128 84 85 /* MAC VLAN */ 86 #define GMAC_VLAN_EDVLP BIT(26) 87 #define GMAC_VLAN_VTHM BIT(25) 88 #define GMAC_VLAN_DOVLTC BIT(20) 89 #define GMAC_VLAN_ESVL BIT(18) 90 #define GMAC_VLAN_ETV BIT(16) 91 #define GMAC_VLAN_VID GENMASK(15, 0) 92 #define GMAC_VLAN_VLTI BIT(20) 93 #define GMAC_VLAN_CSVL BIT(19) 94 #define GMAC_VLAN_VLC GENMASK(17, 16) 95 #define GMAC_VLAN_VLC_SHIFT 16 96 #define GMAC_VLAN_VLHT GENMASK(15, 0) 97 98 /* MAC VLAN Tag */ 99 #define GMAC_VLAN_TAG_VID GENMASK(15, 0) 100 #define GMAC_VLAN_TAG_ETV BIT(16) 101 102 /* MAC VLAN Tag Control */ 103 #define GMAC_VLAN_TAG_CTRL_OB BIT(0) 104 #define GMAC_VLAN_TAG_CTRL_CT BIT(1) 105 #define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2) 106 #define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2 107 #define GMAC_VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21) 108 #define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT 21 109 #define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24) 110 111 #define GMAC_VLAN_TAG_STRIP_NONE (0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 112 #define GMAC_VLAN_TAG_STRIP_PASS (0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 113 #define GMAC_VLAN_TAG_STRIP_FAIL (0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 114 #define GMAC_VLAN_TAG_STRIP_ALL (0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT) 115 116 /* MAC VLAN Tag Data/Filter */ 117 #define GMAC_VLAN_TAG_DATA_VID GENMASK(15, 0) 118 #define GMAC_VLAN_TAG_DATA_VEN BIT(16) 119 #define GMAC_VLAN_TAG_DATA_ETV BIT(17) 120 121 /* MAC RX Queue Enable */ 122 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 123 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 124 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 125 126 /* MAC Flow Control RX */ 127 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 128 129 /* RX Queues Priorities */ 130 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 131 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 132 133 /* TX Queues Priorities */ 134 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 135 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 136 137 /* MAC Flow Control TX */ 138 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 139 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 140 141 /* MAC Interrupt bitmap*/ 142 #define GMAC_INT_RGSMIIS BIT(0) 143 #define GMAC_INT_PCS_LINK BIT(1) 144 #define GMAC_INT_PCS_ANE BIT(2) 145 #define GMAC_INT_PCS_PHYIS BIT(3) 146 #define GMAC_INT_PMT_EN BIT(4) 147 #define GMAC_INT_LPI_EN BIT(5) 148 #define GMAC_INT_TSIE BIT(12) 149 150 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 151 GMAC_INT_PCS_ANE) 152 153 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \ 154 GMAC_INT_TSIE) 155 156 enum dwmac4_irq_status { 157 time_stamp_irq = 0x00001000, 158 mmc_rx_csum_offload_irq = 0x00000800, 159 mmc_tx_irq = 0x00000400, 160 mmc_rx_irq = 0x00000200, 161 mmc_irq = 0x00000100, 162 lpi_irq = 0x00000020, 163 pmt_irq = 0x00000010, 164 }; 165 166 /* MAC PMT bitmap */ 167 enum power_event { 168 pointer_reset = 0x80000000, 169 global_unicast = 0x00000200, 170 wake_up_rx_frame = 0x00000040, 171 magic_frame = 0x00000020, 172 wake_up_frame_en = 0x00000004, 173 magic_pkt_en = 0x00000002, 174 power_down = 0x00000001, 175 }; 176 177 /* Energy Efficient Ethernet (EEE) for GMAC4 178 * 179 * LPI status, timer and control register offset 180 */ 181 #define GMAC4_LPI_CTRL_STATUS 0xd0 182 #define GMAC4_LPI_TIMER_CTRL 0xd4 183 #define GMAC4_LPI_ENTRY_TIMER 0xd8 184 185 /* LPI control and status defines */ 186 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */ 187 #define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */ 188 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 189 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 190 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 191 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 192 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 193 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 194 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 195 196 /* MAC Debug bitmap */ 197 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 198 #define GMAC_DEBUG_TFCSTS_SHIFT 17 199 #define GMAC_DEBUG_TFCSTS_IDLE 0 200 #define GMAC_DEBUG_TFCSTS_WAIT 1 201 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 202 #define GMAC_DEBUG_TFCSTS_XFER 3 203 #define GMAC_DEBUG_TPESTS BIT(16) 204 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 205 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 206 #define GMAC_DEBUG_RPESTS BIT(0) 207 208 /* MAC config */ 209 #define GMAC_CONFIG_ARPEN BIT(31) 210 #define GMAC_CONFIG_SARC GENMASK(30, 28) 211 #define GMAC_CONFIG_SARC_SHIFT 28 212 #define GMAC_CONFIG_IPC BIT(27) 213 #define GMAC_CONFIG_IPG GENMASK(26, 24) 214 #define GMAC_CONFIG_IPG_SHIFT 24 215 #define GMAC_CONFIG_2K BIT(22) 216 #define GMAC_CONFIG_ACS BIT(20) 217 #define GMAC_CONFIG_BE BIT(18) 218 #define GMAC_CONFIG_JD BIT(17) 219 #define GMAC_CONFIG_JE BIT(16) 220 #define GMAC_CONFIG_PS BIT(15) 221 #define GMAC_CONFIG_FES BIT(14) 222 #define GMAC_CONFIG_FES_SHIFT 14 223 #define GMAC_CONFIG_DM BIT(13) 224 #define GMAC_CONFIG_LM BIT(12) 225 #define GMAC_CONFIG_DCRS BIT(9) 226 #define GMAC_CONFIG_TE BIT(1) 227 #define GMAC_CONFIG_RE BIT(0) 228 229 /* MAC extended config */ 230 #define GMAC_CONFIG_EIPG GENMASK(29, 25) 231 #define GMAC_CONFIG_EIPG_SHIFT 25 232 #define GMAC_CONFIG_EIPG_EN BIT(24) 233 #define GMAC_CONFIG_HDSMS GENMASK(22, 20) 234 #define GMAC_CONFIG_HDSMS_SHIFT 20 235 #define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT) 236 237 /* MAC HW features0 bitmap */ 238 #define GMAC_HW_FEAT_SAVLANINS BIT(27) 239 #define GMAC_HW_FEAT_ADDMAC BIT(18) 240 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 241 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 242 #define GMAC_HW_FEAT_EEESEL BIT(13) 243 #define GMAC_HW_FEAT_TSSEL BIT(12) 244 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9) 245 #define GMAC_HW_FEAT_MMCSEL BIT(8) 246 #define GMAC_HW_FEAT_MGKSEL BIT(7) 247 #define GMAC_HW_FEAT_RWKSEL BIT(6) 248 #define GMAC_HW_FEAT_SMASEL BIT(5) 249 #define GMAC_HW_FEAT_VLHASH BIT(4) 250 #define GMAC_HW_FEAT_PCSSEL BIT(3) 251 #define GMAC_HW_FEAT_HDSEL BIT(2) 252 #define GMAC_HW_FEAT_GMIISEL BIT(1) 253 #define GMAC_HW_FEAT_MIISEL BIT(0) 254 255 /* MAC HW features1 bitmap */ 256 #define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27) 257 #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) 258 #define GMAC_HW_FEAT_AVSEL BIT(20) 259 #define GMAC_HW_TSOEN BIT(18) 260 #define GMAC_HW_FEAT_SPHEN BIT(17) 261 #define GMAC_HW_ADDR64 GENMASK(15, 14) 262 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 263 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 264 265 /* MAC HW features2 bitmap */ 266 #define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28) 267 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24) 268 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 269 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 270 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 271 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 272 273 /* MAC HW features3 bitmap */ 274 #define GMAC_HW_FEAT_ASP GENMASK(29, 28) 275 #define GMAC_HW_FEAT_TBSSEL BIT(27) 276 #define GMAC_HW_FEAT_FPESEL BIT(26) 277 #define GMAC_HW_FEAT_ESTWID GENMASK(21, 20) 278 #define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17) 279 #define GMAC_HW_FEAT_ESTSEL BIT(16) 280 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13) 281 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11) 282 #define GMAC_HW_FEAT_FRPSEL BIT(10) 283 #define GMAC_HW_FEAT_DVLAN BIT(5) 284 #define GMAC_HW_FEAT_NRVF GENMASK(2, 0) 285 286 /* GMAC GPIO Status reg */ 287 #define GMAC_GPO0 BIT(16) 288 #define GMAC_GPO1 BIT(17) 289 #define GMAC_GPO2 BIT(18) 290 #define GMAC_GPO3 BIT(19) 291 292 /* MAC HW ADDR regs */ 293 #define GMAC_HI_DCS GENMASK(18, 16) 294 #define GMAC_HI_DCS_SHIFT 16 295 #define GMAC_HI_REG_AE BIT(31) 296 297 /* L3/L4 Filters regs */ 298 #define GMAC_L4DPIM0 BIT(21) 299 #define GMAC_L4DPM0 BIT(20) 300 #define GMAC_L4SPIM0 BIT(19) 301 #define GMAC_L4SPM0 BIT(18) 302 #define GMAC_L4PEN0 BIT(16) 303 #define GMAC_L3DAIM0 BIT(5) 304 #define GMAC_L3DAM0 BIT(4) 305 #define GMAC_L3SAIM0 BIT(3) 306 #define GMAC_L3SAM0 BIT(2) 307 #define GMAC_L3PEN0 BIT(0) 308 #define GMAC_L4DP0 GENMASK(31, 16) 309 #define GMAC_L4DP0_SHIFT 16 310 #define GMAC_L4SP0 GENMASK(15, 0) 311 312 /* MAC Timestamp Status */ 313 #define GMAC_TIMESTAMP_AUXTSTRIG BIT(2) 314 #define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25) 315 #define GMAC_TIMESTAMP_ATSNS_SHIFT 25 316 317 /* MTL registers */ 318 #define MTL_OPERATION_MODE 0x00000c00 319 #define MTL_FRPE BIT(15) 320 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 321 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 322 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 323 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 324 #define MTL_OPERATION_SCHALG_SP (0x3 << 5) 325 #define MTL_OPERATION_RAA BIT(2) 326 #define MTL_OPERATION_RAA_SP (0x0 << 2) 327 #define MTL_OPERATION_RAA_WSP (0x1 << 2) 328 329 #define MTL_INT_STATUS 0x00000c20 330 #define MTL_INT_QX(x) BIT(x) 331 332 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 333 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 334 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x)) 335 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 336 337 #define MTL_CHAN_BASE_ADDR 0x00000d00 338 #define MTL_CHAN_BASE_OFFSET 0x40 339 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 340 (x * MTL_CHAN_BASE_OFFSET)) 341 342 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 343 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 344 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 345 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 346 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 347 348 #define MTL_OP_MODE_RSF BIT(5) 349 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 350 #define MTL_OP_MODE_TXQEN_AV BIT(2) 351 #define MTL_OP_MODE_TXQEN BIT(3) 352 #define MTL_OP_MODE_TSF BIT(1) 353 354 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 355 #define MTL_OP_MODE_TQS_SHIFT 16 356 357 #define MTL_OP_MODE_TTC_MASK 0x70 358 #define MTL_OP_MODE_TTC_SHIFT 4 359 360 #define MTL_OP_MODE_TTC_32 0 361 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 362 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 363 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 364 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 365 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 366 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 367 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 368 369 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 370 #define MTL_OP_MODE_RQS_SHIFT 20 371 372 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 373 #define MTL_OP_MODE_RFD_SHIFT 14 374 375 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 376 #define MTL_OP_MODE_RFA_SHIFT 8 377 378 #define MTL_OP_MODE_EHFC BIT(7) 379 380 #define MTL_OP_MODE_RTC_MASK 0x18 381 #define MTL_OP_MODE_RTC_SHIFT 3 382 383 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 384 #define MTL_OP_MODE_RTC_64 0 385 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 386 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 387 388 /* MTL ETS Control register */ 389 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 390 #define MTL_ETS_CTRL_BASE_OFFSET 0x40 391 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \ 392 ((x) * MTL_ETS_CTRL_BASE_OFFSET)) 393 394 #define MTL_ETS_CTRL_CC BIT(3) 395 #define MTL_ETS_CTRL_AVALG BIT(2) 396 397 /* MTL Queue Quantum Weight */ 398 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 399 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 400 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \ 401 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET)) 402 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 403 404 /* MTL sendSlopeCredit register */ 405 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 406 #define MTL_SEND_SLP_CRED_OFFSET 0x40 407 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \ 408 ((x) * MTL_SEND_SLP_CRED_OFFSET)) 409 410 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 411 412 /* MTL hiCredit register */ 413 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 414 #define MTL_HIGH_CRED_OFFSET 0x40 415 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \ 416 ((x) * MTL_HIGH_CRED_OFFSET)) 417 418 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 419 420 /* MTL loCredit register */ 421 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24 422 #define MTL_LOW_CRED_OFFSET 0x40 423 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \ 424 ((x) * MTL_LOW_CRED_OFFSET)) 425 426 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 427 428 /* MTL debug */ 429 #define MTL_DEBUG_TXSTSFSTS BIT(5) 430 #define MTL_DEBUG_TXFSTS BIT(4) 431 #define MTL_DEBUG_TWCSTS BIT(3) 432 433 /* MTL debug: Tx FIFO Read Controller Status */ 434 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 435 #define MTL_DEBUG_TRCSTS_SHIFT 1 436 #define MTL_DEBUG_TRCSTS_IDLE 0 437 #define MTL_DEBUG_TRCSTS_READ 1 438 #define MTL_DEBUG_TRCSTS_TXW 2 439 #define MTL_DEBUG_TRCSTS_WRITE 3 440 #define MTL_DEBUG_TXPAUSED BIT(0) 441 442 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 443 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 444 #define MTL_DEBUG_RXFSTS_SHIFT 4 445 #define MTL_DEBUG_RXFSTS_EMPTY 0 446 #define MTL_DEBUG_RXFSTS_BT 1 447 #define MTL_DEBUG_RXFSTS_AT 2 448 #define MTL_DEBUG_RXFSTS_FULL 3 449 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 450 #define MTL_DEBUG_RRCSTS_SHIFT 1 451 #define MTL_DEBUG_RRCSTS_IDLE 0 452 #define MTL_DEBUG_RRCSTS_RDATA 1 453 #define MTL_DEBUG_RRCSTS_RSTAT 2 454 #define MTL_DEBUG_RRCSTS_FLUSH 3 455 #define MTL_DEBUG_RWCSTS BIT(0) 456 457 /* MTL interrupt */ 458 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 459 #define MTL_RX_OVERFLOW_INT BIT(16) 460 461 /* Default operating mode of the MAC */ 462 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 463 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \ 464 GMAC_CONFIG_JE) 465 466 /* To dump the core regs excluding the Address Registers */ 467 #define GMAC_REG_NUM 132 468 469 /* MTL debug */ 470 #define MTL_DEBUG_TXSTSFSTS BIT(5) 471 #define MTL_DEBUG_TXFSTS BIT(4) 472 #define MTL_DEBUG_TWCSTS BIT(3) 473 474 /* MTL debug: Tx FIFO Read Controller Status */ 475 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 476 #define MTL_DEBUG_TRCSTS_SHIFT 1 477 #define MTL_DEBUG_TRCSTS_IDLE 0 478 #define MTL_DEBUG_TRCSTS_READ 1 479 #define MTL_DEBUG_TRCSTS_TXW 2 480 #define MTL_DEBUG_TRCSTS_WRITE 3 481 #define MTL_DEBUG_TXPAUSED BIT(0) 482 483 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 484 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 485 #define MTL_DEBUG_RXFSTS_SHIFT 4 486 #define MTL_DEBUG_RXFSTS_EMPTY 0 487 #define MTL_DEBUG_RXFSTS_BT 1 488 #define MTL_DEBUG_RXFSTS_AT 2 489 #define MTL_DEBUG_RXFSTS_FULL 3 490 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 491 #define MTL_DEBUG_RRCSTS_SHIFT 1 492 #define MTL_DEBUG_RRCSTS_IDLE 0 493 #define MTL_DEBUG_RRCSTS_RDATA 1 494 #define MTL_DEBUG_RRCSTS_RSTAT 2 495 #define MTL_DEBUG_RRCSTS_FLUSH 3 496 #define MTL_DEBUG_RWCSTS BIT(0) 497 498 /* SGMII/RGMII status register */ 499 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 500 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 501 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 502 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 503 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 504 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 505 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 506 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 507 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 508 /* LNKMOD */ 509 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 510 /* LNKSPEED */ 511 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 512 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 513 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 514 515 extern const struct stmmac_dma_ops dwmac4_dma_ops; 516 extern const struct stmmac_dma_ops dwmac410_dma_ops; 517 #endif /* __DWMAC4_H__ */ 518