1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DWMAC4 Header file. 4 * 5 * Copyright (C) 2015 STMicroelectronics Ltd 6 * 7 * Author: Alexandre Torgue <alexandre.torgue@st.com> 8 */ 9 10 #ifndef __DWMAC4_H__ 11 #define __DWMAC4_H__ 12 13 #include "common.h" 14 15 /* MAC registers */ 16 #define GMAC_CONFIG 0x00000000 17 #define GMAC_PACKET_FILTER 0x00000008 18 #define GMAC_HASH_TAB_0_31 0x00000010 19 #define GMAC_HASH_TAB_32_63 0x00000014 20 #define GMAC_RX_FLOW_CTRL 0x00000090 21 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4) 22 #define GMAC_TXQ_PRTY_MAP0 0x98 23 #define GMAC_TXQ_PRTY_MAP1 0x9C 24 #define GMAC_RXQ_CTRL0 0x000000a0 25 #define GMAC_RXQ_CTRL1 0x000000a4 26 #define GMAC_RXQ_CTRL2 0x000000a8 27 #define GMAC_RXQ_CTRL3 0x000000ac 28 #define GMAC_INT_STATUS 0x000000b0 29 #define GMAC_INT_EN 0x000000b4 30 #define GMAC_1US_TIC_COUNTER 0x000000dc 31 #define GMAC_PCS_BASE 0x000000e0 32 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8 33 #define GMAC_PMT 0x000000c0 34 #define GMAC_DEBUG 0x00000114 35 #define GMAC_HW_FEATURE0 0x0000011c 36 #define GMAC_HW_FEATURE1 0x00000120 37 #define GMAC_HW_FEATURE2 0x00000124 38 #define GMAC_HW_FEATURE3 0x00000128 39 #define GMAC_MDIO_ADDR 0x00000200 40 #define GMAC_MDIO_DATA 0x00000204 41 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) 42 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) 43 44 /* RX Queues Routing */ 45 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0) 46 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0 47 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4) 48 #define GMAC_RXQCTRL_PTPQ_SHIFT 4 49 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8) 50 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8 51 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12) 52 #define GMAC_RXQCTRL_UPQ_SHIFT 12 53 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16) 54 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16 55 #define GMAC_RXQCTRL_MCBCQEN BIT(20) 56 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20 57 #define GMAC_RXQCTRL_TACPQE BIT(21) 58 #define GMAC_RXQCTRL_TACPQE_SHIFT 21 59 60 /* MAC Packet Filtering */ 61 #define GMAC_PACKET_FILTER_PR BIT(0) 62 #define GMAC_PACKET_FILTER_HMC BIT(2) 63 #define GMAC_PACKET_FILTER_PM BIT(4) 64 65 #define GMAC_MAX_PERFECT_ADDRESSES 128 66 67 /* MAC RX Queue Enable */ 68 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2)) 69 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2) 70 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1) 71 72 /* MAC Flow Control RX */ 73 #define GMAC_RX_FLOW_CTRL_RFE BIT(0) 74 75 /* RX Queues Priorities */ 76 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 77 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) 78 79 /* TX Queues Priorities */ 80 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) 81 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) 82 83 /* MAC Flow Control TX */ 84 #define GMAC_TX_FLOW_CTRL_TFE BIT(1) 85 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 86 87 /* MAC Interrupt bitmap*/ 88 #define GMAC_INT_RGSMIIS BIT(0) 89 #define GMAC_INT_PCS_LINK BIT(1) 90 #define GMAC_INT_PCS_ANE BIT(2) 91 #define GMAC_INT_PCS_PHYIS BIT(3) 92 #define GMAC_INT_PMT_EN BIT(4) 93 #define GMAC_INT_LPI_EN BIT(5) 94 95 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ 96 GMAC_INT_PCS_ANE) 97 98 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN) 99 100 enum dwmac4_irq_status { 101 time_stamp_irq = 0x00001000, 102 mmc_rx_csum_offload_irq = 0x00000800, 103 mmc_tx_irq = 0x00000400, 104 mmc_rx_irq = 0x00000200, 105 mmc_irq = 0x00000100, 106 lpi_irq = 0x00000020, 107 pmt_irq = 0x00000010, 108 }; 109 110 /* MAC PMT bitmap */ 111 enum power_event { 112 pointer_reset = 0x80000000, 113 global_unicast = 0x00000200, 114 wake_up_rx_frame = 0x00000040, 115 magic_frame = 0x00000020, 116 wake_up_frame_en = 0x00000004, 117 magic_pkt_en = 0x00000002, 118 power_down = 0x00000001, 119 }; 120 121 /* Energy Efficient Ethernet (EEE) for GMAC4 122 * 123 * LPI status, timer and control register offset 124 */ 125 #define GMAC4_LPI_CTRL_STATUS 0xd0 126 #define GMAC4_LPI_TIMER_CTRL 0xd4 127 128 /* LPI control and status defines */ 129 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */ 130 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 131 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 132 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 133 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 134 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 135 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 136 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 137 138 /* MAC Debug bitmap */ 139 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 140 #define GMAC_DEBUG_TFCSTS_SHIFT 17 141 #define GMAC_DEBUG_TFCSTS_IDLE 0 142 #define GMAC_DEBUG_TFCSTS_WAIT 1 143 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 144 #define GMAC_DEBUG_TFCSTS_XFER 3 145 #define GMAC_DEBUG_TPESTS BIT(16) 146 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 147 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 148 #define GMAC_DEBUG_RPESTS BIT(0) 149 150 /* MAC config */ 151 #define GMAC_CONFIG_IPC BIT(27) 152 #define GMAC_CONFIG_2K BIT(22) 153 #define GMAC_CONFIG_ACS BIT(20) 154 #define GMAC_CONFIG_BE BIT(18) 155 #define GMAC_CONFIG_JD BIT(17) 156 #define GMAC_CONFIG_JE BIT(16) 157 #define GMAC_CONFIG_PS BIT(15) 158 #define GMAC_CONFIG_FES BIT(14) 159 #define GMAC_CONFIG_DM BIT(13) 160 #define GMAC_CONFIG_DCRS BIT(9) 161 #define GMAC_CONFIG_TE BIT(1) 162 #define GMAC_CONFIG_RE BIT(0) 163 164 /* MAC HW features0 bitmap */ 165 #define GMAC_HW_FEAT_ADDMAC BIT(18) 166 #define GMAC_HW_FEAT_RXCOESEL BIT(16) 167 #define GMAC_HW_FEAT_TXCOSEL BIT(14) 168 #define GMAC_HW_FEAT_EEESEL BIT(13) 169 #define GMAC_HW_FEAT_TSSEL BIT(12) 170 #define GMAC_HW_FEAT_MMCSEL BIT(8) 171 #define GMAC_HW_FEAT_MGKSEL BIT(7) 172 #define GMAC_HW_FEAT_RWKSEL BIT(6) 173 #define GMAC_HW_FEAT_SMASEL BIT(5) 174 #define GMAC_HW_FEAT_VLHASH BIT(4) 175 #define GMAC_HW_FEAT_PCSSEL BIT(3) 176 #define GMAC_HW_FEAT_HDSEL BIT(2) 177 #define GMAC_HW_FEAT_GMIISEL BIT(1) 178 #define GMAC_HW_FEAT_MIISEL BIT(0) 179 180 /* MAC HW features1 bitmap */ 181 #define GMAC_HW_FEAT_AVSEL BIT(20) 182 #define GMAC_HW_TSOEN BIT(18) 183 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) 184 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) 185 186 /* MAC HW features2 bitmap */ 187 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24) 188 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18) 189 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12) 190 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6) 191 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0) 192 193 /* MAC HW features3 bitmap */ 194 #define GMAC_HW_FEAT_ASP GENMASK(29, 28) 195 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13) 196 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11) 197 #define GMAC_HW_FEAT_FRPSEL BIT(10) 198 199 /* MAC HW ADDR regs */ 200 #define GMAC_HI_DCS GENMASK(18, 16) 201 #define GMAC_HI_DCS_SHIFT 16 202 #define GMAC_HI_REG_AE BIT(31) 203 204 /* MTL registers */ 205 #define MTL_OPERATION_MODE 0x00000c00 206 #define MTL_FRPE BIT(15) 207 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5) 208 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5) 209 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 210 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 211 #define MTL_OPERATION_SCHALG_SP (0x3 << 5) 212 #define MTL_OPERATION_RAA BIT(2) 213 #define MTL_OPERATION_RAA_SP (0x0 << 2) 214 #define MTL_OPERATION_RAA_WSP (0x1 << 2) 215 216 #define MTL_INT_STATUS 0x00000c20 217 #define MTL_INT_QX(x) BIT(x) 218 219 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */ 220 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */ 221 #define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0) 222 #define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0) 223 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x)) 224 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q))) 225 226 #define MTL_CHAN_BASE_ADDR 0x00000d00 227 #define MTL_CHAN_BASE_OFFSET 0x40 228 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \ 229 (x * MTL_CHAN_BASE_OFFSET)) 230 231 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x) 232 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8) 233 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c) 234 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30) 235 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38) 236 237 #define MTL_OP_MODE_RSF BIT(5) 238 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2) 239 #define MTL_OP_MODE_TXQEN_AV BIT(2) 240 #define MTL_OP_MODE_TXQEN BIT(3) 241 #define MTL_OP_MODE_TSF BIT(1) 242 243 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16) 244 #define MTL_OP_MODE_TQS_SHIFT 16 245 246 #define MTL_OP_MODE_TTC_MASK 0x70 247 #define MTL_OP_MODE_TTC_SHIFT 4 248 249 #define MTL_OP_MODE_TTC_32 0 250 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT) 251 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT) 252 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT) 253 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT) 254 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT) 255 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT) 256 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT) 257 258 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20) 259 #define MTL_OP_MODE_RQS_SHIFT 20 260 261 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14) 262 #define MTL_OP_MODE_RFD_SHIFT 14 263 264 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8) 265 #define MTL_OP_MODE_RFA_SHIFT 8 266 267 #define MTL_OP_MODE_EHFC BIT(7) 268 269 #define MTL_OP_MODE_RTC_MASK 0x18 270 #define MTL_OP_MODE_RTC_SHIFT 3 271 272 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) 273 #define MTL_OP_MODE_RTC_64 0 274 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT) 275 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT) 276 277 /* MTL ETS Control register */ 278 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10 279 #define MTL_ETS_CTRL_BASE_OFFSET 0x40 280 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \ 281 ((x) * MTL_ETS_CTRL_BASE_OFFSET)) 282 283 #define MTL_ETS_CTRL_CC BIT(3) 284 #define MTL_ETS_CTRL_AVALG BIT(2) 285 286 /* MTL Queue Quantum Weight */ 287 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18 288 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40 289 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \ 290 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET)) 291 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0) 292 293 /* MTL sendSlopeCredit register */ 294 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c 295 #define MTL_SEND_SLP_CRED_OFFSET 0x40 296 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \ 297 ((x) * MTL_SEND_SLP_CRED_OFFSET)) 298 299 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0) 300 301 /* MTL hiCredit register */ 302 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20 303 #define MTL_HIGH_CRED_OFFSET 0x40 304 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \ 305 ((x) * MTL_HIGH_CRED_OFFSET)) 306 307 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0) 308 309 /* MTL loCredit register */ 310 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24 311 #define MTL_LOW_CRED_OFFSET 0x40 312 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \ 313 ((x) * MTL_LOW_CRED_OFFSET)) 314 315 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0) 316 317 /* MTL debug */ 318 #define MTL_DEBUG_TXSTSFSTS BIT(5) 319 #define MTL_DEBUG_TXFSTS BIT(4) 320 #define MTL_DEBUG_TWCSTS BIT(3) 321 322 /* MTL debug: Tx FIFO Read Controller Status */ 323 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 324 #define MTL_DEBUG_TRCSTS_SHIFT 1 325 #define MTL_DEBUG_TRCSTS_IDLE 0 326 #define MTL_DEBUG_TRCSTS_READ 1 327 #define MTL_DEBUG_TRCSTS_TXW 2 328 #define MTL_DEBUG_TRCSTS_WRITE 3 329 #define MTL_DEBUG_TXPAUSED BIT(0) 330 331 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 332 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 333 #define MTL_DEBUG_RXFSTS_SHIFT 4 334 #define MTL_DEBUG_RXFSTS_EMPTY 0 335 #define MTL_DEBUG_RXFSTS_BT 1 336 #define MTL_DEBUG_RXFSTS_AT 2 337 #define MTL_DEBUG_RXFSTS_FULL 3 338 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 339 #define MTL_DEBUG_RRCSTS_SHIFT 1 340 #define MTL_DEBUG_RRCSTS_IDLE 0 341 #define MTL_DEBUG_RRCSTS_RDATA 1 342 #define MTL_DEBUG_RRCSTS_RSTAT 2 343 #define MTL_DEBUG_RRCSTS_FLUSH 3 344 #define MTL_DEBUG_RWCSTS BIT(0) 345 346 /* MTL interrupt */ 347 #define MTL_RX_OVERFLOW_INT_EN BIT(24) 348 #define MTL_RX_OVERFLOW_INT BIT(16) 349 350 /* Default operating mode of the MAC */ 351 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \ 352 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS) 353 354 /* To dump the core regs excluding the Address Registers */ 355 #define GMAC_REG_NUM 132 356 357 /* MTL debug */ 358 #define MTL_DEBUG_TXSTSFSTS BIT(5) 359 #define MTL_DEBUG_TXFSTS BIT(4) 360 #define MTL_DEBUG_TWCSTS BIT(3) 361 362 /* MTL debug: Tx FIFO Read Controller Status */ 363 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1) 364 #define MTL_DEBUG_TRCSTS_SHIFT 1 365 #define MTL_DEBUG_TRCSTS_IDLE 0 366 #define MTL_DEBUG_TRCSTS_READ 1 367 #define MTL_DEBUG_TRCSTS_TXW 2 368 #define MTL_DEBUG_TRCSTS_WRITE 3 369 #define MTL_DEBUG_TXPAUSED BIT(0) 370 371 /* MAC debug: GMII or MII Transmit Protocol Engine Status */ 372 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4) 373 #define MTL_DEBUG_RXFSTS_SHIFT 4 374 #define MTL_DEBUG_RXFSTS_EMPTY 0 375 #define MTL_DEBUG_RXFSTS_BT 1 376 #define MTL_DEBUG_RXFSTS_AT 2 377 #define MTL_DEBUG_RXFSTS_FULL 3 378 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1) 379 #define MTL_DEBUG_RRCSTS_SHIFT 1 380 #define MTL_DEBUG_RRCSTS_IDLE 0 381 #define MTL_DEBUG_RRCSTS_RDATA 1 382 #define MTL_DEBUG_RRCSTS_RSTAT 2 383 #define MTL_DEBUG_RRCSTS_FLUSH 3 384 #define MTL_DEBUG_RWCSTS BIT(0) 385 386 /* SGMII/RGMII status register */ 387 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 388 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 389 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 390 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 391 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 392 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17 393 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 394 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 395 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 396 /* LNKMOD */ 397 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1 398 /* LNKSPEED */ 399 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 400 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 401 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 402 403 extern const struct stmmac_dma_ops dwmac4_dma_ops; 404 extern const struct stmmac_dma_ops dwmac410_dma_ops; 405 #endif /* __DWMAC4_H__ */ 406