1 /*
2  * DWMAC4 Header file.
3  *
4  * Copyright (C) 2015  STMicroelectronics Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
11  */
12 
13 #ifndef __DWMAC4_H__
14 #define __DWMAC4_H__
15 
16 #include "common.h"
17 
18 /*  MAC registers */
19 #define GMAC_CONFIG			0x00000000
20 #define GMAC_PACKET_FILTER		0x00000008
21 #define GMAC_HASH_TAB_0_31		0x00000010
22 #define GMAC_HASH_TAB_32_63		0x00000014
23 #define GMAC_RX_FLOW_CTRL		0x00000090
24 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
25 #define GMAC_INT_STATUS			0x000000b0
26 #define GMAC_INT_EN			0x000000b4
27 #define GMAC_AN_CTRL			0x000000e0
28 #define GMAC_AN_STATUS			0x000000e4
29 #define GMAC_AN_ADV			0x000000e8
30 #define GMAC_AN_LPA			0x000000ec
31 #define GMAC_PMT			0x000000c0
32 #define GMAC_VERSION			0x00000110
33 #define GMAC_DEBUG			0x00000114
34 #define GMAC_HW_FEATURE0		0x0000011c
35 #define GMAC_HW_FEATURE1		0x00000120
36 #define GMAC_HW_FEATURE2		0x00000124
37 #define GMAC_MDIO_ADDR			0x00000200
38 #define GMAC_MDIO_DATA			0x00000204
39 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
40 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
41 
42 /* MAC Packet Filtering */
43 #define GMAC_PACKET_FILTER_PR		BIT(0)
44 #define GMAC_PACKET_FILTER_HMC		BIT(2)
45 #define GMAC_PACKET_FILTER_PM		BIT(4)
46 
47 #define GMAC_MAX_PERFECT_ADDRESSES	128
48 
49 /* MAC Flow Control RX */
50 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
51 
52 /* MAC Flow Control TX */
53 #define GMAC_TX_FLOW_CTRL_TFE		BIT(1)
54 #define GMAC_TX_FLOW_CTRL_PT_SHIFT	16
55 
56 /*  MAC Interrupt bitmap*/
57 #define GMAC_INT_PMT_EN			BIT(4)
58 #define GMAC_INT_LPI_EN			BIT(5)
59 
60 enum dwmac4_irq_status {
61 	time_stamp_irq = 0x00001000,
62 	mmc_rx_csum_offload_irq = 0x00000800,
63 	mmc_tx_irq = 0x00000400,
64 	mmc_rx_irq = 0x00000200,
65 	mmc_irq = 0x00000100,
66 	pmt_irq = 0x00000010,
67 	pcs_ane_irq = 0x00000004,
68 	pcs_link_irq = 0x00000002,
69 };
70 
71 /* MAC Auto-Neg bitmap*/
72 #define	GMAC_AN_CTRL_RAN		BIT(9)
73 #define	GMAC_AN_CTRL_ANE		BIT(12)
74 #define GMAC_AN_CTRL_ELE		BIT(14)
75 #define GMAC_AN_FD			BIT(5)
76 #define GMAC_AN_HD			BIT(6)
77 #define GMAC_AN_PSE_MASK		GENMASK(8, 7)
78 #define GMAC_AN_PSE_SHIFT		7
79 
80 /* MAC PMT bitmap */
81 enum power_event {
82 	pointer_reset =	0x80000000,
83 	global_unicast = 0x00000200,
84 	wake_up_rx_frame = 0x00000040,
85 	magic_frame = 0x00000020,
86 	wake_up_frame_en = 0x00000004,
87 	magic_pkt_en = 0x00000002,
88 	power_down = 0x00000001,
89 };
90 
91 /* MAC Debug bitmap */
92 #define GMAC_DEBUG_TFCSTS_MASK		GENMASK(18, 17)
93 #define GMAC_DEBUG_TFCSTS_SHIFT		17
94 #define GMAC_DEBUG_TFCSTS_IDLE		0
95 #define GMAC_DEBUG_TFCSTS_WAIT		1
96 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
97 #define GMAC_DEBUG_TFCSTS_XFER		3
98 #define GMAC_DEBUG_TPESTS		BIT(16)
99 #define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
100 #define GMAC_DEBUG_RFCFCSTS_SHIFT	1
101 #define GMAC_DEBUG_RPESTS		BIT(0)
102 
103 /* MAC config */
104 #define GMAC_CONFIG_IPC			BIT(27)
105 #define GMAC_CONFIG_2K			BIT(22)
106 #define GMAC_CONFIG_ACS			BIT(20)
107 #define GMAC_CONFIG_BE			BIT(18)
108 #define GMAC_CONFIG_JD			BIT(17)
109 #define GMAC_CONFIG_JE			BIT(16)
110 #define GMAC_CONFIG_PS			BIT(15)
111 #define GMAC_CONFIG_FES			BIT(14)
112 #define GMAC_CONFIG_DM			BIT(13)
113 #define GMAC_CONFIG_DCRS		BIT(9)
114 #define GMAC_CONFIG_TE			BIT(1)
115 #define GMAC_CONFIG_RE			BIT(0)
116 
117 /* MAC HW features0 bitmap */
118 #define GMAC_HW_FEAT_ADDMAC		BIT(18)
119 #define GMAC_HW_FEAT_RXCOESEL		BIT(16)
120 #define GMAC_HW_FEAT_TXCOSEL		BIT(14)
121 #define GMAC_HW_FEAT_EEESEL		BIT(13)
122 #define GMAC_HW_FEAT_TSSEL		BIT(12)
123 #define GMAC_HW_FEAT_MMCSEL		BIT(8)
124 #define GMAC_HW_FEAT_MGKSEL		BIT(7)
125 #define GMAC_HW_FEAT_RWKSEL		BIT(6)
126 #define GMAC_HW_FEAT_SMASEL		BIT(5)
127 #define GMAC_HW_FEAT_VLHASH		BIT(4)
128 #define GMAC_HW_FEAT_PCSSEL		BIT(3)
129 #define GMAC_HW_FEAT_HDSEL		BIT(2)
130 #define GMAC_HW_FEAT_GMIISEL		BIT(1)
131 #define GMAC_HW_FEAT_MIISEL		BIT(0)
132 
133 /* MAC HW features1 bitmap */
134 #define GMAC_HW_FEAT_AVSEL		BIT(20)
135 #define GMAC_HW_TSOEN			BIT(18)
136 
137 /* MAC HW features2 bitmap */
138 #define GMAC_HW_FEAT_TXCHCNT		GENMASK(21, 18)
139 #define GMAC_HW_FEAT_RXCHCNT		GENMASK(15, 12)
140 
141 /* MAC HW ADDR regs */
142 #define GMAC_HI_DCS			GENMASK(18, 16)
143 #define GMAC_HI_DCS_SHIFT		16
144 #define GMAC_HI_REG_AE			BIT(31)
145 
146 /*  MTL registers */
147 #define MTL_INT_STATUS			0x00000c20
148 #define MTL_INT_Q0			BIT(0)
149 
150 #define MTL_CHAN_BASE_ADDR		0x00000d00
151 #define MTL_CHAN_BASE_OFFSET		0x40
152 #define MTL_CHANX_BASE_ADDR(x)		(MTL_CHAN_BASE_ADDR + \
153 					(x * MTL_CHAN_BASE_OFFSET))
154 
155 #define MTL_CHAN_TX_OP_MODE(x)		MTL_CHANX_BASE_ADDR(x)
156 #define MTL_CHAN_TX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x8)
157 #define MTL_CHAN_INT_CTRL(x)		(MTL_CHANX_BASE_ADDR(x) + 0x2c)
158 #define MTL_CHAN_RX_OP_MODE(x)		(MTL_CHANX_BASE_ADDR(x) + 0x30)
159 #define MTL_CHAN_RX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x38)
160 
161 #define MTL_OP_MODE_RSF			BIT(5)
162 #define MTL_OP_MODE_TSF			BIT(1)
163 
164 #define MTL_OP_MODE_TTC_MASK		0x70
165 #define MTL_OP_MODE_TTC_SHIFT		4
166 
167 #define MTL_OP_MODE_TTC_32		0
168 #define MTL_OP_MODE_TTC_64		(1 << MTL_OP_MODE_TTC_SHIFT)
169 #define MTL_OP_MODE_TTC_96		(2 << MTL_OP_MODE_TTC_SHIFT)
170 #define MTL_OP_MODE_TTC_128		(3 << MTL_OP_MODE_TTC_SHIFT)
171 #define MTL_OP_MODE_TTC_192		(4 << MTL_OP_MODE_TTC_SHIFT)
172 #define MTL_OP_MODE_TTC_256		(5 << MTL_OP_MODE_TTC_SHIFT)
173 #define MTL_OP_MODE_TTC_384		(6 << MTL_OP_MODE_TTC_SHIFT)
174 #define MTL_OP_MODE_TTC_512		(7 << MTL_OP_MODE_TTC_SHIFT)
175 
176 #define MTL_OP_MODE_RTC_MASK		0x18
177 #define MTL_OP_MODE_RTC_SHIFT		3
178 
179 #define MTL_OP_MODE_RTC_32		(1 << MTL_OP_MODE_RTC_SHIFT)
180 #define MTL_OP_MODE_RTC_64		0
181 #define MTL_OP_MODE_RTC_96		(2 << MTL_OP_MODE_RTC_SHIFT)
182 #define MTL_OP_MODE_RTC_128		(3 << MTL_OP_MODE_RTC_SHIFT)
183 
184 /*  MTL debug */
185 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
186 #define MTL_DEBUG_TXFSTS		BIT(4)
187 #define MTL_DEBUG_TWCSTS		BIT(3)
188 
189 /* MTL debug: Tx FIFO Read Controller Status */
190 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
191 #define MTL_DEBUG_TRCSTS_SHIFT		1
192 #define MTL_DEBUG_TRCSTS_IDLE		0
193 #define MTL_DEBUG_TRCSTS_READ		1
194 #define MTL_DEBUG_TRCSTS_TXW		2
195 #define MTL_DEBUG_TRCSTS_WRITE		3
196 #define MTL_DEBUG_TXPAUSED		BIT(0)
197 
198 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
199 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
200 #define MTL_DEBUG_RXFSTS_SHIFT		4
201 #define MTL_DEBUG_RXFSTS_EMPTY		0
202 #define MTL_DEBUG_RXFSTS_BT		1
203 #define MTL_DEBUG_RXFSTS_AT		2
204 #define MTL_DEBUG_RXFSTS_FULL		3
205 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
206 #define MTL_DEBUG_RRCSTS_SHIFT		1
207 #define MTL_DEBUG_RRCSTS_IDLE		0
208 #define MTL_DEBUG_RRCSTS_RDATA		1
209 #define MTL_DEBUG_RRCSTS_RSTAT		2
210 #define MTL_DEBUG_RRCSTS_FLUSH		3
211 #define MTL_DEBUG_RWCSTS		BIT(0)
212 
213 /*  MTL interrupt */
214 #define MTL_RX_OVERFLOW_INT_EN		BIT(24)
215 #define MTL_RX_OVERFLOW_INT		BIT(16)
216 
217 /* Default operating mode of the MAC */
218 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
219 			GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
220 
221 /* To dump the core regs excluding  the Address Registers */
222 #define	GMAC_REG_NUM	132
223 
224 /*  MTL debug */
225 #define MTL_DEBUG_TXSTSFSTS		BIT(5)
226 #define MTL_DEBUG_TXFSTS		BIT(4)
227 #define MTL_DEBUG_TWCSTS		BIT(3)
228 
229 /* MTL debug: Tx FIFO Read Controller Status */
230 #define MTL_DEBUG_TRCSTS_MASK		GENMASK(2, 1)
231 #define MTL_DEBUG_TRCSTS_SHIFT		1
232 #define MTL_DEBUG_TRCSTS_IDLE		0
233 #define MTL_DEBUG_TRCSTS_READ		1
234 #define MTL_DEBUG_TRCSTS_TXW		2
235 #define MTL_DEBUG_TRCSTS_WRITE		3
236 #define MTL_DEBUG_TXPAUSED		BIT(0)
237 
238 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
239 #define MTL_DEBUG_RXFSTS_MASK		GENMASK(5, 4)
240 #define MTL_DEBUG_RXFSTS_SHIFT		4
241 #define MTL_DEBUG_RXFSTS_EMPTY		0
242 #define MTL_DEBUG_RXFSTS_BT		1
243 #define MTL_DEBUG_RXFSTS_AT		2
244 #define MTL_DEBUG_RXFSTS_FULL		3
245 #define MTL_DEBUG_RRCSTS_MASK		GENMASK(2, 1)
246 #define MTL_DEBUG_RRCSTS_SHIFT		1
247 #define MTL_DEBUG_RRCSTS_IDLE		0
248 #define MTL_DEBUG_RRCSTS_RDATA		1
249 #define MTL_DEBUG_RRCSTS_RSTAT		2
250 #define MTL_DEBUG_RRCSTS_FLUSH		3
251 #define MTL_DEBUG_RWCSTS		BIT(0)
252 
253 extern const struct stmmac_dma_ops dwmac4_dma_ops;
254 extern const struct stmmac_dma_ops dwmac410_dma_ops;
255 #endif /* __DWMAC4_H__ */
256