1 /******************************************************************************* 2 This is the driver for the MAC 10/100 on-chip Ethernet controller 3 currently tested on all the ST boards based on STb7109 and stx7200 SoCs. 4 5 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing 6 this code. 7 8 This only implements the mac core functions for this chip. 9 10 Copyright (C) 2007-2009 STMicroelectronics Ltd 11 12 This program is free software; you can redistribute it and/or modify it 13 under the terms and conditions of the GNU General Public License, 14 version 2, as published by the Free Software Foundation. 15 16 This program is distributed in the hope it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 more details. 20 21 You should have received a copy of the GNU General Public License along with 22 this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 24 25 The full GNU General Public License is included in this distribution in 26 the file called "COPYING". 27 28 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 29 *******************************************************************************/ 30 31 #include <linux/crc32.h> 32 #include <asm/io.h> 33 #include "dwmac100.h" 34 35 static void dwmac100_core_init(struct mac_device_info *hw, int mtu) 36 { 37 void __iomem *ioaddr = hw->pcsr; 38 u32 value = readl(ioaddr + MAC_CONTROL); 39 40 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL); 41 42 #ifdef STMMAC_VLAN_TAG_USED 43 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1); 44 #endif 45 } 46 47 static void dwmac100_dump_mac_regs(struct mac_device_info *hw) 48 { 49 void __iomem *ioaddr = hw->pcsr; 50 pr_info("\t----------------------------------------------\n" 51 "\t DWMAC 100 CSR (base addr = 0x%p)\n" 52 "\t----------------------------------------------\n", ioaddr); 53 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL, 54 readl(ioaddr + MAC_CONTROL)); 55 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH, 56 readl(ioaddr + MAC_ADDR_HIGH)); 57 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW, 58 readl(ioaddr + MAC_ADDR_LOW)); 59 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n", 60 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH)); 61 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n", 62 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW)); 63 pr_info("\tflow control (offset 0x%x): 0x%08x\n", 64 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL)); 65 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1, 66 readl(ioaddr + MAC_VLAN1)); 67 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2, 68 readl(ioaddr + MAC_VLAN2)); 69 } 70 71 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw) 72 { 73 return 0; 74 } 75 76 static int dwmac100_irq_status(struct mac_device_info *hw, 77 struct stmmac_extra_stats *x) 78 { 79 return 0; 80 } 81 82 static void dwmac100_set_umac_addr(struct mac_device_info *hw, 83 unsigned char *addr, 84 unsigned int reg_n) 85 { 86 void __iomem *ioaddr = hw->pcsr; 87 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 88 } 89 90 static void dwmac100_get_umac_addr(struct mac_device_info *hw, 91 unsigned char *addr, 92 unsigned int reg_n) 93 { 94 void __iomem *ioaddr = hw->pcsr; 95 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 96 } 97 98 static void dwmac100_set_filter(struct mac_device_info *hw, 99 struct net_device *dev) 100 { 101 void __iomem *ioaddr = (void __iomem *)dev->base_addr; 102 u32 value = readl(ioaddr + MAC_CONTROL); 103 104 if (dev->flags & IFF_PROMISC) { 105 value |= MAC_CONTROL_PR; 106 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO | 107 MAC_CONTROL_HP); 108 } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE) 109 || (dev->flags & IFF_ALLMULTI)) { 110 value |= MAC_CONTROL_PM; 111 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO); 112 writel(0xffffffff, ioaddr + MAC_HASH_HIGH); 113 writel(0xffffffff, ioaddr + MAC_HASH_LOW); 114 } else if (netdev_mc_empty(dev)) { /* no multicast */ 115 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF | 116 MAC_CONTROL_HO | MAC_CONTROL_HP); 117 } else { 118 u32 mc_filter[2]; 119 struct netdev_hw_addr *ha; 120 121 /* Perfect filter mode for physical address and Hash 122 * filter for multicast 123 */ 124 value |= MAC_CONTROL_HP; 125 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | 126 MAC_CONTROL_IF | MAC_CONTROL_HO); 127 128 memset(mc_filter, 0, sizeof(mc_filter)); 129 netdev_for_each_mc_addr(ha, dev) { 130 /* The upper 6 bits of the calculated CRC are used to 131 * index the contens of the hash table 132 */ 133 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 134 /* The most significant bit determines the register to 135 * use (H/L) while the other 5 bits determine the bit 136 * within the register. 137 */ 138 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 139 } 140 writel(mc_filter[0], ioaddr + MAC_HASH_LOW); 141 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH); 142 } 143 144 writel(value, ioaddr + MAC_CONTROL); 145 } 146 147 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, 148 unsigned int fc, unsigned int pause_time) 149 { 150 void __iomem *ioaddr = hw->pcsr; 151 unsigned int flow = MAC_FLOW_CTRL_ENABLE; 152 153 if (duplex) 154 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT); 155 writel(flow, ioaddr + MAC_FLOW_CTRL); 156 } 157 158 /* No PMT module supported on ST boards with this Eth chip. */ 159 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode) 160 { 161 return; 162 } 163 164 static const struct stmmac_ops dwmac100_ops = { 165 .core_init = dwmac100_core_init, 166 .rx_ipc = dwmac100_rx_ipc_enable, 167 .dump_regs = dwmac100_dump_mac_regs, 168 .host_irq_status = dwmac100_irq_status, 169 .set_filter = dwmac100_set_filter, 170 .flow_ctrl = dwmac100_flow_ctrl, 171 .pmt = dwmac100_pmt, 172 .set_umac_addr = dwmac100_set_umac_addr, 173 .get_umac_addr = dwmac100_get_umac_addr, 174 }; 175 176 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id) 177 { 178 struct mac_device_info *mac; 179 180 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); 181 if (!mac) 182 return NULL; 183 184 pr_info("\tDWMAC100\n"); 185 186 mac->pcsr = ioaddr; 187 mac->mac = &dwmac100_ops; 188 mac->dma = &dwmac100_dma_ops; 189 190 mac->link.port = MAC_CONTROL_PS; 191 mac->link.duplex = MAC_CONTROL_F; 192 mac->link.speed = 0; 193 mac->mii.addr = MAC_MII_ADDR; 194 mac->mii.data = MAC_MII_DATA; 195 /* Synopsys Id is not available on old chips */ 196 *synopsys_id = 0; 197 198 return mac; 199 } 200