1 /******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 The full GNU General Public License is included in this distribution in 14 the file called "COPYING". 15 16 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 17 *******************************************************************************/ 18 #ifndef __DWMAC1000_H__ 19 #define __DWMAC1000_H__ 20 21 #include <linux/phy.h> 22 #include "common.h" 23 24 #define GMAC_CONTROL 0x00000000 /* Configuration */ 25 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 26 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 27 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ 28 #define GMAC_MII_ADDR 0x00000010 /* MII Address */ 29 #define GMAC_MII_DATA 0x00000014 /* MII Data */ 30 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ 31 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ 32 #define GMAC_VERSION 0x00000020 /* GMAC CORE Version */ 33 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */ 34 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 35 36 #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 37 #define GMAC_INT_STATUS_PMT BIT(3) 38 #define GMAC_INT_STATUS_MMCIS BIT(4) 39 #define GMAC_INT_STATUS_MMCRIS BIT(5) 40 #define GMAC_INT_STATUS_MMCTIS BIT(6) 41 #define GMAC_INT_STATUS_MMCCSUM BIT(7) 42 #define GMAC_INT_STATUS_TSTAMP BIT(9) 43 #define GMAC_INT_STATUS_LPIIS BIT(10) 44 45 /* interrupt mask register */ 46 #define GMAC_INT_MASK 0x0000003c 47 #define GMAC_INT_DISABLE_RGMII BIT(0) 48 #define GMAC_INT_DISABLE_PCSLINK BIT(1) 49 #define GMAC_INT_DISABLE_PCSAN BIT(2) 50 #define GMAC_INT_DISABLE_PMT BIT(3) 51 #define GMAC_INT_DISABLE_TIMESTAMP BIT(9) 52 #define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII | \ 53 GMAC_INT_DISABLE_PCSLINK | \ 54 GMAC_INT_DISABLE_PCSAN) 55 #define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP | \ 56 GMAC_INT_DISABLE_PCS) 57 58 /* PMT Control and Status */ 59 #define GMAC_PMT 0x0000002c 60 enum power_event { 61 pointer_reset = 0x80000000, 62 global_unicast = 0x00000200, 63 wake_up_rx_frame = 0x00000040, 64 magic_frame = 0x00000020, 65 wake_up_frame_en = 0x00000004, 66 magic_pkt_en = 0x00000002, 67 power_down = 0x00000001, 68 }; 69 70 /* Energy Efficient Ethernet (EEE) 71 * 72 * LPI status, timer and control register offset 73 */ 74 #define LPI_CTRL_STATUS 0x0030 75 #define LPI_TIMER_CTRL 0x0034 76 77 /* LPI control and status defines */ 78 #define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */ 79 #define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */ 80 #define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */ 81 #define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */ 82 #define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */ 83 #define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */ 84 #define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */ 85 #define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */ 86 #define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */ 87 #define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */ 88 89 /* GMAC HW ADDR regs */ 90 #define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ 91 (reg * 8)) 92 #define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ 93 (reg * 8)) 94 #define GMAC_MAX_PERFECT_ADDRESSES 1 95 96 #define GMAC_PCS_BASE 0x000000c0 /* PCS register base */ 97 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */ 98 99 /* SGMII/RGMII status register */ 100 #define GMAC_RGSMIIIS_LNKMODE BIT(0) 101 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1) 102 #define GMAC_RGSMIIIS_SPEED_SHIFT 1 103 #define GMAC_RGSMIIIS_LNKSTS BIT(3) 104 #define GMAC_RGSMIIIS_JABTO BIT(4) 105 #define GMAC_RGSMIIIS_FALSECARDET BIT(5) 106 #define GMAC_RGSMIIIS_SMIDRXS BIT(16) 107 /* LNKMOD */ 108 #define GMAC_RGSMIIIS_LNKMOD_MASK 0x1 109 /* LNKSPEED */ 110 #define GMAC_RGSMIIIS_SPEED_125 0x2 111 #define GMAC_RGSMIIIS_SPEED_25 0x1 112 #define GMAC_RGSMIIIS_SPEED_2_5 0x0 113 114 /* GMAC Configuration defines */ 115 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */ 116 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ 117 #define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */ 118 #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 119 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 120 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 121 enum inter_frame_gap { 122 GMAC_CONTROL_IFG_88 = 0x00040000, 123 GMAC_CONTROL_IFG_80 = 0x00020000, 124 GMAC_CONTROL_IFG_40 = 0x000e0000, 125 }; 126 #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */ 127 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ 128 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ 129 #define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */ 130 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 131 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ 132 #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 133 #define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */ 134 #define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */ 135 #define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */ 136 #define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */ 137 #define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 138 #define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 139 140 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \ 141 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS) 142 143 /* GMAC Frame Filter defines */ 144 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 145 #define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 146 #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 147 #define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 148 #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 149 #define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 150 #define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 151 #define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 152 #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 153 #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 154 /* GMII ADDR defines */ 155 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ 156 #define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ 157 /* GMAC FLOW CTRL defines */ 158 #define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 159 #define GMAC_FLOW_CTRL_PT_SHIFT 16 160 #define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */ 161 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 162 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 163 #define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 164 165 /* DEBUG Register defines */ 166 /* MTL TxStatus FIFO */ 167 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */ 168 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */ 169 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */ 170 /* MTL Tx FIFO Read Controller Status */ 171 #define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20) 172 #define GMAC_DEBUG_TRCSTS_SHIFT 20 173 #define GMAC_DEBUG_TRCSTS_IDLE 0 174 #define GMAC_DEBUG_TRCSTS_READ 1 175 #define GMAC_DEBUG_TRCSTS_TXW 2 176 #define GMAC_DEBUG_TRCSTS_WRITE 3 177 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */ 178 /* MAC Transmit Frame Controller Status */ 179 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17) 180 #define GMAC_DEBUG_TFCSTS_SHIFT 17 181 #define GMAC_DEBUG_TFCSTS_IDLE 0 182 #define GMAC_DEBUG_TFCSTS_WAIT 1 183 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2 184 #define GMAC_DEBUG_TFCSTS_XFER 3 185 /* MAC GMII or MII Transmit Protocol Engine Status */ 186 #define GMAC_DEBUG_TPESTS BIT(16) 187 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */ 188 #define GMAC_DEBUG_RXFSTS_SHIFT 8 189 #define GMAC_DEBUG_RXFSTS_EMPTY 0 190 #define GMAC_DEBUG_RXFSTS_BT 1 191 #define GMAC_DEBUG_RXFSTS_AT 2 192 #define GMAC_DEBUG_RXFSTS_FULL 3 193 #define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */ 194 #define GMAC_DEBUG_RRCSTS_SHIFT 5 195 #define GMAC_DEBUG_RRCSTS_IDLE 0 196 #define GMAC_DEBUG_RRCSTS_RDATA 1 197 #define GMAC_DEBUG_RRCSTS_RSTAT 2 198 #define GMAC_DEBUG_RRCSTS_FLUSH 3 199 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */ 200 /* MAC Receive Frame Controller FIFO Status */ 201 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1) 202 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1 203 /* MAC GMII or MII Receive Protocol Engine Status */ 204 #define GMAC_DEBUG_RPESTS BIT(0) 205 206 /*--- DMA BLOCK defines ---*/ 207 /* DMA Bus Mode register defines */ 208 #define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */ 209 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 210 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 211 /* Programmable burst length (passed thorugh platform)*/ 212 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 213 #define DMA_BUS_MODE_PBL_SHIFT 8 214 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 215 216 enum rx_tx_priority_ratio { 217 double_ratio = 0x00004000, /* 2:1 */ 218 triple_ratio = 0x00008000, /* 3:1 */ 219 quadruple_ratio = 0x0000c000, /* 4:1 */ 220 }; 221 222 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 223 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */ 224 #define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */ 225 #define DMA_BUS_MODE_RPBL_SHIFT 17 226 #define DMA_BUS_MODE_USP 0x00800000 227 #define DMA_BUS_MODE_MAXPBL 0x01000000 228 #define DMA_BUS_MODE_AAL 0x02000000 229 230 /* DMA CRS Control and Status Register Mapping */ 231 #define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */ 232 #define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */ 233 /* DMA Bus Mode register defines */ 234 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 235 #define DMA_BUS_PR_RATIO_SHIFT 14 236 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 237 238 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ 239 /* Disable Drop TCP/IP csum error */ 240 #define DMA_CONTROL_DT 0x04000000 241 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ 242 #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ 243 /* Threshold for Activating the FC */ 244 enum rfa { 245 act_full_minus_1 = 0x00800000, 246 act_full_minus_2 = 0x00800200, 247 act_full_minus_3 = 0x00800400, 248 act_full_minus_4 = 0x00800600, 249 }; 250 /* Threshold for Deactivating the FC */ 251 enum rfd { 252 deac_full_minus_1 = 0x00400000, 253 deac_full_minus_2 = 0x00400800, 254 deac_full_minus_3 = 0x00401000, 255 deac_full_minus_4 = 0x00401800, 256 }; 257 #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ 258 259 enum ttc_control { 260 DMA_CONTROL_TTC_64 = 0x00000000, 261 DMA_CONTROL_TTC_128 = 0x00004000, 262 DMA_CONTROL_TTC_192 = 0x00008000, 263 DMA_CONTROL_TTC_256 = 0x0000c000, 264 DMA_CONTROL_TTC_40 = 0x00010000, 265 DMA_CONTROL_TTC_32 = 0x00014000, 266 DMA_CONTROL_TTC_24 = 0x00018000, 267 DMA_CONTROL_TTC_16 = 0x0001c000, 268 }; 269 #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff 270 271 #define DMA_CONTROL_EFC 0x00000100 272 #define DMA_CONTROL_FEF 0x00000080 273 #define DMA_CONTROL_FUF 0x00000040 274 275 /* Receive flow control activation field 276 * RFA field in DMA control register, bits 23,10:9 277 */ 278 #define DMA_CONTROL_RFA_MASK 0x00800600 279 280 /* Receive flow control deactivation field 281 * RFD field in DMA control register, bits 22,12:11 282 */ 283 #define DMA_CONTROL_RFD_MASK 0x00401800 284 285 /* RFD and RFA fields are encoded as follows 286 * 287 * Bit Field 288 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled) 289 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled) 290 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled) 291 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled) 292 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled) 293 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled) 294 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled) 295 * 1,11 - Reserved 296 * 297 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work, 298 * but packet throughput performance may not be as expected. 299 * 300 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame 301 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause 302 * Description). 303 * 304 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6), 305 * is set to 0. This allows pause frames with a quanta of 0 to be sent 306 * as an XOFF message to the link peer. 307 */ 308 309 #define RFA_FULL_MINUS_1K 0x00000000 310 #define RFA_FULL_MINUS_2K 0x00000200 311 #define RFA_FULL_MINUS_3K 0x00000400 312 #define RFA_FULL_MINUS_4K 0x00000600 313 #define RFA_FULL_MINUS_5K 0x00800000 314 #define RFA_FULL_MINUS_6K 0x00800200 315 #define RFA_FULL_MINUS_7K 0x00800400 316 317 #define RFD_FULL_MINUS_1K 0x00000000 318 #define RFD_FULL_MINUS_2K 0x00000800 319 #define RFD_FULL_MINUS_3K 0x00001000 320 #define RFD_FULL_MINUS_4K 0x00001800 321 #define RFD_FULL_MINUS_5K 0x00400000 322 #define RFD_FULL_MINUS_6K 0x00400800 323 #define RFD_FULL_MINUS_7K 0x00401000 324 325 enum rtc_control { 326 DMA_CONTROL_RTC_64 = 0x00000000, 327 DMA_CONTROL_RTC_32 = 0x00000008, 328 DMA_CONTROL_RTC_96 = 0x00000010, 329 DMA_CONTROL_RTC_128 = 0x00000018, 330 }; 331 #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 332 333 #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ 334 335 /* MMC registers offset */ 336 #define GMAC_MMC_CTRL 0x100 337 #define GMAC_MMC_RX_INTR 0x104 338 #define GMAC_MMC_TX_INTR 0x108 339 #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 340 #define GMAC_EXTHASH_BASE 0x500 341 342 extern const struct stmmac_dma_ops dwmac1000_dma_ops; 343 #endif /* __DWMAC1000_H__ */ 344