1 /******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 You should have received a copy of the GNU General Public License along with 14 this program; if not, write to the Free Software Foundation, Inc., 15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 17 The full GNU General Public License is included in this distribution in 18 the file called "COPYING". 19 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 21 *******************************************************************************/ 22 #ifndef __DWMAC1000_H__ 23 #define __DWMAC1000_H__ 24 25 #include <linux/phy.h> 26 #include "common.h" 27 28 #define GMAC_CONTROL 0x00000000 /* Configuration */ 29 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 30 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 31 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ 32 #define GMAC_MII_ADDR 0x00000010 /* MII Address */ 33 #define GMAC_MII_DATA 0x00000014 /* MII Data */ 34 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ 35 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ 36 #define GMAC_VERSION 0x00000020 /* GMAC CORE Version */ 37 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 38 39 #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 40 enum dwmac1000_irq_status { 41 lpiis_irq = 0x400, 42 time_stamp_irq = 0x0200, 43 mmc_rx_csum_offload_irq = 0x0080, 44 mmc_tx_irq = 0x0040, 45 mmc_rx_irq = 0x0020, 46 mmc_irq = 0x0010, 47 pmt_irq = 0x0008, 48 pcs_ane_irq = 0x0004, 49 pcs_link_irq = 0x0002, 50 rgmii_irq = 0x0001, 51 }; 52 #define GMAC_INT_MASK 0x0000003c /* interrupt mask register */ 53 54 /* PMT Control and Status */ 55 #define GMAC_PMT 0x0000002c 56 enum power_event { 57 pointer_reset = 0x80000000, 58 global_unicast = 0x00000200, 59 wake_up_rx_frame = 0x00000040, 60 magic_frame = 0x00000020, 61 wake_up_frame_en = 0x00000004, 62 magic_pkt_en = 0x00000002, 63 power_down = 0x00000001, 64 }; 65 66 /* Energy Efficient Ethernet (EEE) 67 * 68 * LPI status, timer and control register offset 69 */ 70 #define LPI_CTRL_STATUS 0x0030 71 #define LPI_TIMER_CTRL 0x0034 72 73 /* LPI control and status defines */ 74 #define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */ 75 #define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */ 76 #define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */ 77 #define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */ 78 #define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */ 79 #define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */ 80 #define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */ 81 #define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */ 82 #define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */ 83 #define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */ 84 85 /* GMAC HW ADDR regs */ 86 #define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ 87 (reg * 8)) 88 #define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ 89 (reg * 8)) 90 #define GMAC_MAX_PERFECT_ADDRESSES 1 91 92 /* PCS registers (AN/TBI/SGMII/RGMII) offset */ 93 #define GMAC_AN_CTRL 0x000000c0 /* AN control */ 94 #define GMAC_AN_STATUS 0x000000c4 /* AN status */ 95 #define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */ 96 #define GMAC_ANE_LPA 0x000000cc /* Auto-Neg. link partener ability */ 97 #define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */ 98 #define GMAC_TBI 0x000000d4 /* TBI extend status */ 99 #define GMAC_S_R_GMII 0x000000d8 /* SGMII RGMII status */ 100 101 /* AN Configuration defines */ 102 #define GMAC_AN_CTRL_RAN 0x00000200 /* Restart Auto-Negotiation */ 103 #define GMAC_AN_CTRL_ANE 0x00001000 /* Auto-Negotiation Enable */ 104 #define GMAC_AN_CTRL_ELE 0x00004000 /* External Loopback Enable */ 105 #define GMAC_AN_CTRL_ECD 0x00010000 /* Enable Comma Detect */ 106 #define GMAC_AN_CTRL_LR 0x00020000 /* Lock to Reference */ 107 #define GMAC_AN_CTRL_SGMRAL 0x00040000 /* SGMII RAL Control */ 108 109 /* AN Status defines */ 110 #define GMAC_AN_STATUS_LS 0x00000004 /* Link Status 0:down 1:up */ 111 #define GMAC_AN_STATUS_ANA 0x00000008 /* Auto-Negotiation Ability */ 112 #define GMAC_AN_STATUS_ANC 0x00000020 /* Auto-Negotiation Complete */ 113 #define GMAC_AN_STATUS_ES 0x00000100 /* Extended Status */ 114 115 /* Register 54 (SGMII/RGMII status register) */ 116 #define GMAC_S_R_GMII_LINK 0x8 117 #define GMAC_S_R_GMII_SPEED 0x5 118 #define GMAC_S_R_GMII_SPEED_SHIFT 0x1 119 #define GMAC_S_R_GMII_MODE 0x1 120 #define GMAC_S_R_GMII_SPEED_125 2 121 #define GMAC_S_R_GMII_SPEED_25 1 122 123 /* Common ADV and LPA defines */ 124 #define GMAC_ANE_FD (1 << 5) 125 #define GMAC_ANE_HD (1 << 6) 126 #define GMAC_ANE_PSE (3 << 7) 127 #define GMAC_ANE_PSE_SHIFT 7 128 129 /* GMAC Configuration defines */ 130 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */ 131 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ 132 #define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */ 133 #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 134 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 135 #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 136 enum inter_frame_gap { 137 GMAC_CONTROL_IFG_88 = 0x00040000, 138 GMAC_CONTROL_IFG_80 = 0x00020000, 139 GMAC_CONTROL_IFG_40 = 0x000e0000, 140 }; 141 #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */ 142 #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ 143 #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ 144 #define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */ 145 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 146 #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ 147 #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 148 #define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */ 149 #define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */ 150 #define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */ 151 #define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */ 152 #define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 153 #define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 154 155 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \ 156 GMAC_CONTROL_BE) 157 158 /* GMAC Frame Filter defines */ 159 #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 160 #define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 161 #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 162 #define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 163 #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 164 #define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 165 #define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 166 #define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 167 #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 168 #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 169 /* GMII ADDR defines */ 170 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ 171 #define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ 172 /* GMAC FLOW CTRL defines */ 173 #define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 174 #define GMAC_FLOW_CTRL_PT_SHIFT 16 175 #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 176 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 177 #define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 178 179 /*--- DMA BLOCK defines ---*/ 180 /* DMA Bus Mode register defines */ 181 #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */ 182 #define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */ 183 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 184 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 185 /* Programmable burst length (passed thorugh platform)*/ 186 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 187 #define DMA_BUS_MODE_PBL_SHIFT 8 188 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 189 190 enum rx_tx_priority_ratio { 191 double_ratio = 0x00004000, /* 2:1 */ 192 triple_ratio = 0x00008000, /* 3:1 */ 193 quadruple_ratio = 0x0000c000, /* 4:1 */ 194 }; 195 196 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 197 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */ 198 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ 199 #define DMA_BUS_MODE_RPBL_SHIFT 17 200 #define DMA_BUS_MODE_USP 0x00800000 201 #define DMA_BUS_MODE_PBL 0x01000000 202 #define DMA_BUS_MODE_AAL 0x02000000 203 204 /* DMA CRS Control and Status Register Mapping */ 205 #define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */ 206 #define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */ 207 /* DMA Bus Mode register defines */ 208 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 209 #define DMA_BUS_PR_RATIO_SHIFT 14 210 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 211 212 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ 213 /* Disable Drop TCP/IP csum error */ 214 #define DMA_CONTROL_DT 0x04000000 215 #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ 216 #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ 217 /* Threshold for Activating the FC */ 218 enum rfa { 219 act_full_minus_1 = 0x00800000, 220 act_full_minus_2 = 0x00800200, 221 act_full_minus_3 = 0x00800400, 222 act_full_minus_4 = 0x00800600, 223 }; 224 /* Threshold for Deactivating the FC */ 225 enum rfd { 226 deac_full_minus_1 = 0x00400000, 227 deac_full_minus_2 = 0x00400800, 228 deac_full_minus_3 = 0x00401000, 229 deac_full_minus_4 = 0x00401800, 230 }; 231 #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ 232 233 enum ttc_control { 234 DMA_CONTROL_TTC_64 = 0x00000000, 235 DMA_CONTROL_TTC_128 = 0x00004000, 236 DMA_CONTROL_TTC_192 = 0x00008000, 237 DMA_CONTROL_TTC_256 = 0x0000c000, 238 DMA_CONTROL_TTC_40 = 0x00010000, 239 DMA_CONTROL_TTC_32 = 0x00014000, 240 DMA_CONTROL_TTC_24 = 0x00018000, 241 DMA_CONTROL_TTC_16 = 0x0001c000, 242 }; 243 #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff 244 245 #define DMA_CONTROL_EFC 0x00000100 246 #define DMA_CONTROL_FEF 0x00000080 247 #define DMA_CONTROL_FUF 0x00000040 248 249 enum rtc_control { 250 DMA_CONTROL_RTC_64 = 0x00000000, 251 DMA_CONTROL_RTC_32 = 0x00000008, 252 DMA_CONTROL_RTC_96 = 0x00000010, 253 DMA_CONTROL_RTC_128 = 0x00000018, 254 }; 255 #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 256 257 #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ 258 259 /* MMC registers offset */ 260 #define GMAC_MMC_CTRL 0x100 261 #define GMAC_MMC_RX_INTR 0x104 262 #define GMAC_MMC_TX_INTR 0x108 263 #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 264 #define GMAC_EXTHASH_BASE 0x500 265 266 extern const struct stmmac_dma_ops dwmac1000_dma_ops; 267 #endif /* __DWMAC1000_H__ */ 268