1 /******************************************************************************* 2 MAC 10/100 Header File 3 4 Copyright (C) 2007-2009 STMicroelectronics Ltd 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 The full GNU General Public License is included in this distribution in 16 the file called "COPYING". 17 18 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 19 *******************************************************************************/ 20 21 #ifndef __DWMAC100_H__ 22 #define __DWMAC100_H__ 23 24 #include <linux/phy.h> 25 #include "common.h" 26 27 /*---------------------------------------------------------------------------- 28 * MAC BLOCK defines 29 *---------------------------------------------------------------------------*/ 30 /* MAC CSR offset */ 31 #define MAC_CONTROL 0x00000000 /* MAC Control */ 32 #define MAC_ADDR_HIGH 0x00000004 /* MAC Address High */ 33 #define MAC_ADDR_LOW 0x00000008 /* MAC Address Low */ 34 #define MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */ 35 #define MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */ 36 #define MAC_MII_ADDR 0x00000014 /* MII Address */ 37 #define MAC_MII_DATA 0x00000018 /* MII Data */ 38 #define MAC_FLOW_CTRL 0x0000001c /* Flow Control */ 39 #define MAC_VLAN1 0x00000020 /* VLAN1 Tag */ 40 #define MAC_VLAN2 0x00000024 /* VLAN2 Tag */ 41 42 /* MAC CTRL defines */ 43 #define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */ 44 #define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */ 45 #define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */ 46 #define MAC_CONTROL_PS 0x08000000 /* Port Select */ 47 #define MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */ 48 #define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */ 49 #define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */ 50 #define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */ 51 #define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */ 52 #define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */ 53 #define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */ 54 #define MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */ 55 #define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */ 56 #define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */ 57 #define MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */ 58 #define MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */ 59 #define MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */ 60 #define MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */ 61 #define MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */ 62 #define MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */ 63 #define MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */ 64 #define MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */ 65 #define MAC_CONTROL_DC 0x00000020 /* Deferral Check */ 66 #define MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 67 #define MAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 68 69 #define MAC_CORE_INIT (MAC_CONTROL_HBD | MAC_CONTROL_ASTP) 70 71 /* MAC FLOW CTRL defines */ 72 #define MAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 73 #define MAC_FLOW_CTRL_PT_SHIFT 16 74 #define MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */ 75 #define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */ 76 #define MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */ 77 78 /* MII ADDR defines */ 79 #define MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ 80 #define MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ 81 82 /*---------------------------------------------------------------------------- 83 * DMA BLOCK defines 84 *---------------------------------------------------------------------------*/ 85 86 /* DMA Bus Mode register defines */ 87 #define DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */ 88 #define DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */ 89 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 90 #define DMA_BUS_MODE_PBL_SHIFT 8 91 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 92 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 93 #define DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */ 94 #define DMA_BUS_MODE_DEFAULT 0x00000000 95 96 /* DMA Control register defines */ 97 #define DMA_CONTROL_SF 0x00200000 /* Store And Forward */ 98 99 /* Transmit Threshold Control */ 100 enum ttc_control { 101 DMA_CONTROL_TTC_DEFAULT = 0x00000000, /* Threshold is 32 DWORDS */ 102 DMA_CONTROL_TTC_64 = 0x00004000, /* Threshold is 64 DWORDS */ 103 DMA_CONTROL_TTC_128 = 0x00008000, /* Threshold is 128 DWORDS */ 104 DMA_CONTROL_TTC_256 = 0x0000c000, /* Threshold is 256 DWORDS */ 105 DMA_CONTROL_TTC_18 = 0x00400000, /* Threshold is 18 DWORDS */ 106 DMA_CONTROL_TTC_24 = 0x00404000, /* Threshold is 24 DWORDS */ 107 DMA_CONTROL_TTC_32 = 0x00408000, /* Threshold is 32 DWORDS */ 108 DMA_CONTROL_TTC_40 = 0x0040c000, /* Threshold is 40 DWORDS */ 109 DMA_CONTROL_SE = 0x00000008, /* Stop On Empty */ 110 DMA_CONTROL_OSF = 0x00000004, /* Operate On 2nd Frame */ 111 }; 112 113 /* STMAC110 DMA Missed Frame Counter register defines */ 114 #define DMA_MISSED_FRAME_OVE 0x10000000 /* FIFO Overflow Overflow */ 115 #define DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000 /* Overflow Frame Counter */ 116 #define DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */ 117 #define DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */ 118 119 extern const struct stmmac_dma_ops dwmac100_dma_ops; 120 121 #endif /* __DWMAC100_H__ */ 122