1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/stmmac.h> 22 23 #include "stmmac.h" 24 #include "stmmac_platform.h" 25 26 /* General notes on dwmac-sun8i: 27 * Locking: no locking is necessary in this file because all necessary locking 28 * is done in the "stmmac files" 29 */ 30 31 /* struct emac_variant - Describe dwmac-sun8i hardware variant 32 * @default_syscon_value: The default value of the EMAC register in syscon 33 * This value is used for disabling properly EMAC 34 * and used as a good starting value in case of the 35 * boot process(uboot) leave some stuff. 36 * @syscon_field reg_field for the syscon's gmac register 37 * @soc_has_internal_phy: Does the MAC embed an internal PHY 38 * @support_mii: Does the MAC handle MII 39 * @support_rmii: Does the MAC handle RMII 40 * @support_rgmii: Does the MAC handle RGMII 41 * 42 * @rx_delay_max: Maximum raw value for RX delay chain 43 * @tx_delay_max: Maximum raw value for TX delay chain 44 * These two also indicate the bitmask for 45 * the RX and TX delay chain registers. A 46 * value of zero indicates this is not supported. 47 */ 48 struct emac_variant { 49 u32 default_syscon_value; 50 const struct reg_field *syscon_field; 51 bool soc_has_internal_phy; 52 bool support_mii; 53 bool support_rmii; 54 bool support_rgmii; 55 u8 rx_delay_max; 56 u8 tx_delay_max; 57 }; 58 59 /* struct sunxi_priv_data - hold all sunxi private data 60 * @tx_clk: reference to MAC TX clock 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @mux_handle: Internal pointer used by mdio-mux lib 68 */ 69 struct sunxi_priv_data { 70 struct clk *tx_clk; 71 struct clk *ephy_clk; 72 struct regulator *regulator; 73 struct reset_control *rst_ephy; 74 const struct emac_variant *variant; 75 struct regmap_field *regmap_field; 76 bool internal_phy_powered; 77 void *mux_handle; 78 }; 79 80 /* EMAC clock register @ 0x30 in the "system control" address range */ 81 static const struct reg_field sun8i_syscon_reg_field = { 82 .reg = 0x30, 83 .lsb = 0, 84 .msb = 31, 85 }; 86 87 /* EMAC clock register @ 0x164 in the CCU address range */ 88 static const struct reg_field sun8i_ccu_reg_field = { 89 .reg = 0x164, 90 .lsb = 0, 91 .msb = 31, 92 }; 93 94 static const struct emac_variant emac_variant_h3 = { 95 .default_syscon_value = 0x58000, 96 .syscon_field = &sun8i_syscon_reg_field, 97 .soc_has_internal_phy = true, 98 .support_mii = true, 99 .support_rmii = true, 100 .support_rgmii = true, 101 .rx_delay_max = 31, 102 .tx_delay_max = 7, 103 }; 104 105 static const struct emac_variant emac_variant_v3s = { 106 .default_syscon_value = 0x38000, 107 .syscon_field = &sun8i_syscon_reg_field, 108 .soc_has_internal_phy = true, 109 .support_mii = true 110 }; 111 112 static const struct emac_variant emac_variant_a83t = { 113 .default_syscon_value = 0, 114 .syscon_field = &sun8i_syscon_reg_field, 115 .soc_has_internal_phy = false, 116 .support_mii = true, 117 .support_rgmii = true, 118 .rx_delay_max = 31, 119 .tx_delay_max = 7, 120 }; 121 122 static const struct emac_variant emac_variant_r40 = { 123 .default_syscon_value = 0, 124 .syscon_field = &sun8i_ccu_reg_field, 125 .support_mii = true, 126 .support_rgmii = true, 127 .rx_delay_max = 7, 128 }; 129 130 static const struct emac_variant emac_variant_a64 = { 131 .default_syscon_value = 0, 132 .syscon_field = &sun8i_syscon_reg_field, 133 .soc_has_internal_phy = false, 134 .support_mii = true, 135 .support_rmii = true, 136 .support_rgmii = true, 137 .rx_delay_max = 31, 138 .tx_delay_max = 7, 139 }; 140 141 static const struct emac_variant emac_variant_h6 = { 142 .default_syscon_value = 0x50000, 143 .syscon_field = &sun8i_syscon_reg_field, 144 /* The "Internal PHY" of H6 is not on the die. It's on the 145 * co-packaged AC200 chip instead. 146 */ 147 .soc_has_internal_phy = false, 148 .support_mii = true, 149 .support_rmii = true, 150 .support_rgmii = true, 151 .rx_delay_max = 31, 152 .tx_delay_max = 7, 153 }; 154 155 #define EMAC_BASIC_CTL0 0x00 156 #define EMAC_BASIC_CTL1 0x04 157 #define EMAC_INT_STA 0x08 158 #define EMAC_INT_EN 0x0C 159 #define EMAC_TX_CTL0 0x10 160 #define EMAC_TX_CTL1 0x14 161 #define EMAC_TX_FLOW_CTL 0x1C 162 #define EMAC_TX_DESC_LIST 0x20 163 #define EMAC_RX_CTL0 0x24 164 #define EMAC_RX_CTL1 0x28 165 #define EMAC_RX_DESC_LIST 0x34 166 #define EMAC_RX_FRM_FLT 0x38 167 #define EMAC_MDIO_CMD 0x48 168 #define EMAC_MDIO_DATA 0x4C 169 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 170 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 171 #define EMAC_TX_DMA_STA 0xB0 172 #define EMAC_TX_CUR_DESC 0xB4 173 #define EMAC_TX_CUR_BUF 0xB8 174 #define EMAC_RX_DMA_STA 0xC0 175 #define EMAC_RX_CUR_DESC 0xC4 176 #define EMAC_RX_CUR_BUF 0xC8 177 178 /* Use in EMAC_BASIC_CTL0 */ 179 #define EMAC_DUPLEX_FULL BIT(0) 180 #define EMAC_LOOPBACK BIT(1) 181 #define EMAC_SPEED_1000 0 182 #define EMAC_SPEED_100 (0x03 << 2) 183 #define EMAC_SPEED_10 (0x02 << 2) 184 185 /* Use in EMAC_BASIC_CTL1 */ 186 #define EMAC_BURSTLEN_SHIFT 24 187 188 /* Used in EMAC_RX_FRM_FLT */ 189 #define EMAC_FRM_FLT_RXALL BIT(0) 190 #define EMAC_FRM_FLT_CTL BIT(13) 191 #define EMAC_FRM_FLT_MULTICAST BIT(16) 192 193 /* Used in RX_CTL1*/ 194 #define EMAC_RX_MD BIT(1) 195 #define EMAC_RX_TH_MASK GENMASK(5, 4) 196 #define EMAC_RX_TH_32 0 197 #define EMAC_RX_TH_64 (0x1 << 4) 198 #define EMAC_RX_TH_96 (0x2 << 4) 199 #define EMAC_RX_TH_128 (0x3 << 4) 200 #define EMAC_RX_DMA_EN BIT(30) 201 #define EMAC_RX_DMA_START BIT(31) 202 203 /* Used in TX_CTL1*/ 204 #define EMAC_TX_MD BIT(1) 205 #define EMAC_TX_NEXT_FRM BIT(2) 206 #define EMAC_TX_TH_MASK GENMASK(10, 8) 207 #define EMAC_TX_TH_64 0 208 #define EMAC_TX_TH_128 (0x1 << 8) 209 #define EMAC_TX_TH_192 (0x2 << 8) 210 #define EMAC_TX_TH_256 (0x3 << 8) 211 #define EMAC_TX_DMA_EN BIT(30) 212 #define EMAC_TX_DMA_START BIT(31) 213 214 /* Used in RX_CTL0 */ 215 #define EMAC_RX_RECEIVER_EN BIT(31) 216 #define EMAC_RX_DO_CRC BIT(27) 217 #define EMAC_RX_FLOW_CTL_EN BIT(16) 218 219 /* Used in TX_CTL0 */ 220 #define EMAC_TX_TRANSMITTER_EN BIT(31) 221 222 /* Used in EMAC_TX_FLOW_CTL */ 223 #define EMAC_TX_FLOW_CTL_EN BIT(0) 224 225 /* Used in EMAC_INT_STA */ 226 #define EMAC_TX_INT BIT(0) 227 #define EMAC_TX_DMA_STOP_INT BIT(1) 228 #define EMAC_TX_BUF_UA_INT BIT(2) 229 #define EMAC_TX_TIMEOUT_INT BIT(3) 230 #define EMAC_TX_UNDERFLOW_INT BIT(4) 231 #define EMAC_TX_EARLY_INT BIT(5) 232 #define EMAC_RX_INT BIT(8) 233 #define EMAC_RX_BUF_UA_INT BIT(9) 234 #define EMAC_RX_DMA_STOP_INT BIT(10) 235 #define EMAC_RX_TIMEOUT_INT BIT(11) 236 #define EMAC_RX_OVERFLOW_INT BIT(12) 237 #define EMAC_RX_EARLY_INT BIT(13) 238 #define EMAC_RGMII_STA_INT BIT(16) 239 240 #define MAC_ADDR_TYPE_DST BIT(31) 241 242 /* H3 specific bits for EPHY */ 243 #define H3_EPHY_ADDR_SHIFT 20 244 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 245 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 246 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 247 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 248 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 249 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 250 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 251 252 /* H3/A64 specific bits */ 253 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 254 255 /* Generic system control EMAC_CLK bits */ 256 #define SYSCON_ETXDC_SHIFT 10 257 #define SYSCON_ERXDC_SHIFT 5 258 /* EMAC PHY Interface Type */ 259 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 260 #define SYSCON_ETCS_MASK GENMASK(1, 0) 261 #define SYSCON_ETCS_MII 0x0 262 #define SYSCON_ETCS_EXT_GMII 0x1 263 #define SYSCON_ETCS_INT_GMII 0x2 264 265 /* sun8i_dwmac_dma_reset() - reset the EMAC 266 * Called from stmmac via stmmac_dma_ops->reset 267 */ 268 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 269 { 270 writel(0, ioaddr + EMAC_RX_CTL1); 271 writel(0, ioaddr + EMAC_TX_CTL1); 272 writel(0, ioaddr + EMAC_RX_FRM_FLT); 273 writel(0, ioaddr + EMAC_RX_DESC_LIST); 274 writel(0, ioaddr + EMAC_TX_DESC_LIST); 275 writel(0, ioaddr + EMAC_INT_EN); 276 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 277 return 0; 278 } 279 280 /* sun8i_dwmac_dma_init() - initialize the EMAC 281 * Called from stmmac via stmmac_dma_ops->init 282 */ 283 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 284 struct stmmac_dma_cfg *dma_cfg, int atds) 285 { 286 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 287 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 288 } 289 290 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 291 struct stmmac_dma_cfg *dma_cfg, 292 dma_addr_t dma_rx_phy, u32 chan) 293 { 294 /* Write RX descriptors address */ 295 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 296 } 297 298 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 299 struct stmmac_dma_cfg *dma_cfg, 300 dma_addr_t dma_tx_phy, u32 chan) 301 { 302 /* Write TX descriptors address */ 303 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 304 } 305 306 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 307 * Called from stmmac_dma_ops->dump_regs 308 * Used for ethtool 309 */ 310 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 311 { 312 int i; 313 314 for (i = 0; i < 0xC8; i += 4) { 315 if (i == 0x32 || i == 0x3C) 316 continue; 317 reg_space[i / 4] = readl(ioaddr + i); 318 } 319 } 320 321 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 322 * Called from stmmac_ops->dump_regs 323 * Used for ethtool 324 */ 325 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 326 u32 *reg_space) 327 { 328 int i; 329 void __iomem *ioaddr = hw->pcsr; 330 331 for (i = 0; i < 0xC8; i += 4) { 332 if (i == 0x32 || i == 0x3C) 333 continue; 334 reg_space[i / 4] = readl(ioaddr + i); 335 } 336 } 337 338 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) 339 { 340 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 341 } 342 343 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 344 { 345 writel(0, ioaddr + EMAC_INT_EN); 346 } 347 348 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 349 { 350 u32 v; 351 352 v = readl(ioaddr + EMAC_TX_CTL1); 353 v |= EMAC_TX_DMA_START; 354 v |= EMAC_TX_DMA_EN; 355 writel(v, ioaddr + EMAC_TX_CTL1); 356 } 357 358 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 359 { 360 u32 v; 361 362 v = readl(ioaddr + EMAC_TX_CTL1); 363 v |= EMAC_TX_DMA_START; 364 v |= EMAC_TX_DMA_EN; 365 writel(v, ioaddr + EMAC_TX_CTL1); 366 } 367 368 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 369 { 370 u32 v; 371 372 v = readl(ioaddr + EMAC_TX_CTL1); 373 v &= ~EMAC_TX_DMA_EN; 374 writel(v, ioaddr + EMAC_TX_CTL1); 375 } 376 377 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 378 { 379 u32 v; 380 381 v = readl(ioaddr + EMAC_RX_CTL1); 382 v |= EMAC_RX_DMA_START; 383 v |= EMAC_RX_DMA_EN; 384 writel(v, ioaddr + EMAC_RX_CTL1); 385 } 386 387 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 388 { 389 u32 v; 390 391 v = readl(ioaddr + EMAC_RX_CTL1); 392 v &= ~EMAC_RX_DMA_EN; 393 writel(v, ioaddr + EMAC_RX_CTL1); 394 } 395 396 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 397 struct stmmac_extra_stats *x, u32 chan) 398 { 399 u32 v; 400 int ret = 0; 401 402 v = readl(ioaddr + EMAC_INT_STA); 403 404 if (v & EMAC_TX_INT) { 405 ret |= handle_tx; 406 x->tx_normal_irq_n++; 407 } 408 409 if (v & EMAC_TX_DMA_STOP_INT) 410 x->tx_process_stopped_irq++; 411 412 if (v & EMAC_TX_BUF_UA_INT) 413 x->tx_process_stopped_irq++; 414 415 if (v & EMAC_TX_TIMEOUT_INT) 416 ret |= tx_hard_error; 417 418 if (v & EMAC_TX_UNDERFLOW_INT) { 419 ret |= tx_hard_error; 420 x->tx_undeflow_irq++; 421 } 422 423 if (v & EMAC_TX_EARLY_INT) 424 x->tx_early_irq++; 425 426 if (v & EMAC_RX_INT) { 427 ret |= handle_rx; 428 x->rx_normal_irq_n++; 429 } 430 431 if (v & EMAC_RX_BUF_UA_INT) 432 x->rx_buf_unav_irq++; 433 434 if (v & EMAC_RX_DMA_STOP_INT) 435 x->rx_process_stopped_irq++; 436 437 if (v & EMAC_RX_TIMEOUT_INT) 438 ret |= tx_hard_error; 439 440 if (v & EMAC_RX_OVERFLOW_INT) { 441 ret |= tx_hard_error; 442 x->rx_overflow_irq++; 443 } 444 445 if (v & EMAC_RX_EARLY_INT) 446 x->rx_early_irq++; 447 448 if (v & EMAC_RGMII_STA_INT) 449 x->irq_rgmii_n++; 450 451 writel(v, ioaddr + EMAC_INT_STA); 452 453 return ret; 454 } 455 456 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 457 u32 channel, int fifosz, u8 qmode) 458 { 459 u32 v; 460 461 v = readl(ioaddr + EMAC_RX_CTL1); 462 if (mode == SF_DMA_MODE) { 463 v |= EMAC_RX_MD; 464 } else { 465 v &= ~EMAC_RX_MD; 466 v &= ~EMAC_RX_TH_MASK; 467 if (mode < 32) 468 v |= EMAC_RX_TH_32; 469 else if (mode < 64) 470 v |= EMAC_RX_TH_64; 471 else if (mode < 96) 472 v |= EMAC_RX_TH_96; 473 else if (mode < 128) 474 v |= EMAC_RX_TH_128; 475 } 476 writel(v, ioaddr + EMAC_RX_CTL1); 477 } 478 479 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 480 u32 channel, int fifosz, u8 qmode) 481 { 482 u32 v; 483 484 v = readl(ioaddr + EMAC_TX_CTL1); 485 if (mode == SF_DMA_MODE) { 486 v |= EMAC_TX_MD; 487 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 488 * comment is 489 * "Operating on second frame increase the performance 490 * especially when transmit store-and-forward is used." 491 */ 492 v |= EMAC_TX_NEXT_FRM; 493 } else { 494 v &= ~EMAC_TX_MD; 495 v &= ~EMAC_TX_TH_MASK; 496 if (mode < 64) 497 v |= EMAC_TX_TH_64; 498 else if (mode < 128) 499 v |= EMAC_TX_TH_128; 500 else if (mode < 192) 501 v |= EMAC_TX_TH_192; 502 else if (mode < 256) 503 v |= EMAC_TX_TH_256; 504 } 505 writel(v, ioaddr + EMAC_TX_CTL1); 506 } 507 508 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 509 .reset = sun8i_dwmac_dma_reset, 510 .init = sun8i_dwmac_dma_init, 511 .init_rx_chan = sun8i_dwmac_dma_init_rx, 512 .init_tx_chan = sun8i_dwmac_dma_init_tx, 513 .dump_regs = sun8i_dwmac_dump_regs, 514 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 515 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 516 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 517 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 518 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 519 .start_tx = sun8i_dwmac_dma_start_tx, 520 .stop_tx = sun8i_dwmac_dma_stop_tx, 521 .start_rx = sun8i_dwmac_dma_start_rx, 522 .stop_rx = sun8i_dwmac_dma_stop_rx, 523 .dma_interrupt = sun8i_dwmac_dma_interrupt, 524 }; 525 526 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 527 { 528 struct sunxi_priv_data *gmac = priv; 529 int ret; 530 531 if (gmac->regulator) { 532 ret = regulator_enable(gmac->regulator); 533 if (ret) { 534 dev_err(&pdev->dev, "Fail to enable regulator\n"); 535 return ret; 536 } 537 } 538 539 ret = clk_prepare_enable(gmac->tx_clk); 540 if (ret) { 541 if (gmac->regulator) 542 regulator_disable(gmac->regulator); 543 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 544 return ret; 545 } 546 547 return 0; 548 } 549 550 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 551 struct net_device *dev) 552 { 553 void __iomem *ioaddr = hw->pcsr; 554 u32 v; 555 556 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 557 writel(v, ioaddr + EMAC_BASIC_CTL1); 558 } 559 560 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 561 { 562 u32 t, r; 563 564 t = readl(ioaddr + EMAC_TX_CTL0); 565 r = readl(ioaddr + EMAC_RX_CTL0); 566 if (enable) { 567 t |= EMAC_TX_TRANSMITTER_EN; 568 r |= EMAC_RX_RECEIVER_EN; 569 } else { 570 t &= ~EMAC_TX_TRANSMITTER_EN; 571 r &= ~EMAC_RX_RECEIVER_EN; 572 } 573 writel(t, ioaddr + EMAC_TX_CTL0); 574 writel(r, ioaddr + EMAC_RX_CTL0); 575 } 576 577 /* Set MAC address at slot reg_n 578 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 579 * If addr is NULL, clear the slot 580 */ 581 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 582 unsigned char *addr, 583 unsigned int reg_n) 584 { 585 void __iomem *ioaddr = hw->pcsr; 586 u32 v; 587 588 if (!addr) { 589 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 590 return; 591 } 592 593 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 594 EMAC_MACADDR_LO(reg_n)); 595 if (reg_n > 0) { 596 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 597 v |= MAC_ADDR_TYPE_DST; 598 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 599 } 600 } 601 602 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 603 unsigned char *addr, 604 unsigned int reg_n) 605 { 606 void __iomem *ioaddr = hw->pcsr; 607 608 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 609 EMAC_MACADDR_LO(reg_n)); 610 } 611 612 /* caution this function must return non 0 to work */ 613 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 614 { 615 void __iomem *ioaddr = hw->pcsr; 616 u32 v; 617 618 v = readl(ioaddr + EMAC_RX_CTL0); 619 v |= EMAC_RX_DO_CRC; 620 writel(v, ioaddr + EMAC_RX_CTL0); 621 622 return 1; 623 } 624 625 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 626 struct net_device *dev) 627 { 628 void __iomem *ioaddr = hw->pcsr; 629 u32 v; 630 int i = 1; 631 struct netdev_hw_addr *ha; 632 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 633 634 v = EMAC_FRM_FLT_CTL; 635 636 if (dev->flags & IFF_PROMISC) { 637 v = EMAC_FRM_FLT_RXALL; 638 } else if (dev->flags & IFF_ALLMULTI) { 639 v |= EMAC_FRM_FLT_MULTICAST; 640 } else if (macaddrs <= hw->unicast_filter_entries) { 641 if (!netdev_mc_empty(dev)) { 642 netdev_for_each_mc_addr(ha, dev) { 643 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 644 i++; 645 } 646 } 647 if (!netdev_uc_empty(dev)) { 648 netdev_for_each_uc_addr(ha, dev) { 649 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 650 i++; 651 } 652 } 653 } else { 654 netdev_info(dev, "Too many address, switching to promiscuous\n"); 655 v = EMAC_FRM_FLT_RXALL; 656 } 657 658 /* Disable unused address filter slots */ 659 while (i < hw->unicast_filter_entries) 660 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 661 662 writel(v, ioaddr + EMAC_RX_FRM_FLT); 663 } 664 665 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 666 unsigned int duplex, unsigned int fc, 667 unsigned int pause_time, u32 tx_cnt) 668 { 669 void __iomem *ioaddr = hw->pcsr; 670 u32 v; 671 672 v = readl(ioaddr + EMAC_RX_CTL0); 673 if (fc == FLOW_AUTO) 674 v |= EMAC_RX_FLOW_CTL_EN; 675 else 676 v &= ~EMAC_RX_FLOW_CTL_EN; 677 writel(v, ioaddr + EMAC_RX_CTL0); 678 679 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 680 if (fc == FLOW_AUTO) 681 v |= EMAC_TX_FLOW_CTL_EN; 682 else 683 v &= ~EMAC_TX_FLOW_CTL_EN; 684 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 685 } 686 687 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 688 { 689 u32 v; 690 int err; 691 692 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 693 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 694 695 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 696 * need more if no cable plugged. 100ms seems OK 697 */ 698 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 699 !(v & 0x01), 100, 100000); 700 701 if (err) { 702 dev_err(priv->device, "EMAC reset timeout\n"); 703 return -EFAULT; 704 } 705 return 0; 706 } 707 708 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 709 static int get_ephy_nodes(struct stmmac_priv *priv) 710 { 711 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 712 struct device_node *mdio_mux, *iphynode; 713 struct device_node *mdio_internal; 714 int ret; 715 716 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 717 if (!mdio_mux) { 718 dev_err(priv->device, "Cannot get mdio-mux node\n"); 719 return -ENODEV; 720 } 721 722 mdio_internal = of_get_compatible_child(mdio_mux, 723 "allwinner,sun8i-h3-mdio-internal"); 724 of_node_put(mdio_mux); 725 if (!mdio_internal) { 726 dev_err(priv->device, "Cannot get internal_mdio node\n"); 727 return -ENODEV; 728 } 729 730 /* Seek for internal PHY */ 731 for_each_child_of_node(mdio_internal, iphynode) { 732 gmac->ephy_clk = of_clk_get(iphynode, 0); 733 if (IS_ERR(gmac->ephy_clk)) 734 continue; 735 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 736 if (IS_ERR(gmac->rst_ephy)) { 737 ret = PTR_ERR(gmac->rst_ephy); 738 if (ret == -EPROBE_DEFER) { 739 of_node_put(iphynode); 740 of_node_put(mdio_internal); 741 return ret; 742 } 743 continue; 744 } 745 dev_info(priv->device, "Found internal PHY node\n"); 746 of_node_put(iphynode); 747 of_node_put(mdio_internal); 748 return 0; 749 } 750 751 of_node_put(mdio_internal); 752 return -ENODEV; 753 } 754 755 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 756 { 757 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 758 int ret; 759 760 if (gmac->internal_phy_powered) { 761 dev_warn(priv->device, "Internal PHY already powered\n"); 762 return 0; 763 } 764 765 dev_info(priv->device, "Powering internal PHY\n"); 766 ret = clk_prepare_enable(gmac->ephy_clk); 767 if (ret) { 768 dev_err(priv->device, "Cannot enable internal PHY\n"); 769 return ret; 770 } 771 772 /* Make sure the EPHY is properly reseted, as U-Boot may leave 773 * it at deasserted state, and thus it may fail to reset EMAC. 774 */ 775 reset_control_assert(gmac->rst_ephy); 776 777 ret = reset_control_deassert(gmac->rst_ephy); 778 if (ret) { 779 dev_err(priv->device, "Cannot deassert internal phy\n"); 780 clk_disable_unprepare(gmac->ephy_clk); 781 return ret; 782 } 783 784 gmac->internal_phy_powered = true; 785 786 return 0; 787 } 788 789 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 790 { 791 if (!gmac->internal_phy_powered) 792 return 0; 793 794 clk_disable_unprepare(gmac->ephy_clk); 795 reset_control_assert(gmac->rst_ephy); 796 gmac->internal_phy_powered = false; 797 return 0; 798 } 799 800 /* MDIO multiplexing switch function 801 * This function is called by the mdio-mux layer when it thinks the mdio bus 802 * multiplexer needs to switch. 803 * 'current_child' is the current value of the mux register 804 * 'desired_child' is the value of the 'reg' property of the target child MDIO 805 * node. 806 * The first time this function is called, current_child == -1. 807 * If current_child == desired_child, then the mux is already set to the 808 * correct bus. 809 */ 810 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 811 void *data) 812 { 813 struct stmmac_priv *priv = data; 814 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 815 u32 reg, val; 816 int ret = 0; 817 bool need_power_ephy = false; 818 819 if (current_child ^ desired_child) { 820 regmap_field_read(gmac->regmap_field, ®); 821 switch (desired_child) { 822 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 823 dev_info(priv->device, "Switch mux to internal PHY"); 824 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 825 826 need_power_ephy = true; 827 break; 828 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 829 dev_info(priv->device, "Switch mux to external PHY"); 830 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 831 need_power_ephy = false; 832 break; 833 default: 834 dev_err(priv->device, "Invalid child ID %x\n", 835 desired_child); 836 return -EINVAL; 837 } 838 regmap_field_write(gmac->regmap_field, val); 839 if (need_power_ephy) { 840 ret = sun8i_dwmac_power_internal_phy(priv); 841 if (ret) 842 return ret; 843 } else { 844 sun8i_dwmac_unpower_internal_phy(gmac); 845 } 846 /* After changing syscon value, the MAC need reset or it will 847 * use the last value (and so the last PHY set). 848 */ 849 ret = sun8i_dwmac_reset(priv); 850 } 851 return ret; 852 } 853 854 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 855 { 856 int ret; 857 struct device_node *mdio_mux; 858 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 859 860 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 861 if (!mdio_mux) 862 return -ENODEV; 863 864 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 865 &gmac->mux_handle, priv, priv->mii); 866 return ret; 867 } 868 869 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 870 { 871 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 872 struct device_node *node = priv->device->of_node; 873 int ret; 874 u32 reg, val; 875 876 ret = regmap_field_read(gmac->regmap_field, &val); 877 if (ret) { 878 dev_err(priv->device, "Fail to read from regmap field.\n"); 879 return ret; 880 } 881 882 reg = gmac->variant->default_syscon_value; 883 if (reg != val) 884 dev_warn(priv->device, 885 "Current syscon value is not the default %x (expect %x)\n", 886 val, reg); 887 888 if (gmac->variant->soc_has_internal_phy) { 889 if (of_property_read_bool(node, "allwinner,leds-active-low")) 890 reg |= H3_EPHY_LED_POL; 891 else 892 reg &= ~H3_EPHY_LED_POL; 893 894 /* Force EPHY xtal frequency to 24MHz. */ 895 reg |= H3_EPHY_CLK_SEL; 896 897 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 898 if (ret < 0) { 899 dev_err(priv->device, "Could not parse MDIO addr\n"); 900 return ret; 901 } 902 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 903 * address. No need to mask it again. 904 */ 905 reg |= 1 << H3_EPHY_ADDR_SHIFT; 906 } else { 907 /* For SoCs without internal PHY the PHY selection bit should be 908 * set to 0 (external PHY). 909 */ 910 reg &= ~H3_EPHY_SELECT; 911 } 912 913 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 914 if (val % 100) { 915 dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 916 return -EINVAL; 917 } 918 val /= 100; 919 dev_dbg(priv->device, "set tx-delay to %x\n", val); 920 if (val <= gmac->variant->tx_delay_max) { 921 reg &= ~(gmac->variant->tx_delay_max << 922 SYSCON_ETXDC_SHIFT); 923 reg |= (val << SYSCON_ETXDC_SHIFT); 924 } else { 925 dev_err(priv->device, "Invalid TX clock delay: %d\n", 926 val); 927 return -EINVAL; 928 } 929 } 930 931 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 932 if (val % 100) { 933 dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 934 return -EINVAL; 935 } 936 val /= 100; 937 dev_dbg(priv->device, "set rx-delay to %x\n", val); 938 if (val <= gmac->variant->rx_delay_max) { 939 reg &= ~(gmac->variant->rx_delay_max << 940 SYSCON_ERXDC_SHIFT); 941 reg |= (val << SYSCON_ERXDC_SHIFT); 942 } else { 943 dev_err(priv->device, "Invalid RX clock delay: %d\n", 944 val); 945 return -EINVAL; 946 } 947 } 948 949 /* Clear interface mode bits */ 950 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 951 if (gmac->variant->support_rmii) 952 reg &= ~SYSCON_RMII_EN; 953 954 switch (priv->plat->interface) { 955 case PHY_INTERFACE_MODE_MII: 956 /* default */ 957 break; 958 case PHY_INTERFACE_MODE_RGMII: 959 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 960 break; 961 case PHY_INTERFACE_MODE_RMII: 962 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 963 break; 964 default: 965 dev_err(priv->device, "Unsupported interface mode: %s", 966 phy_modes(priv->plat->interface)); 967 return -EINVAL; 968 } 969 970 regmap_field_write(gmac->regmap_field, reg); 971 972 return 0; 973 } 974 975 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 976 { 977 u32 reg = gmac->variant->default_syscon_value; 978 979 regmap_field_write(gmac->regmap_field, reg); 980 } 981 982 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 983 { 984 struct sunxi_priv_data *gmac = priv; 985 986 if (gmac->variant->soc_has_internal_phy) { 987 /* sun8i_dwmac_exit could be called with mdiomux uninit */ 988 if (gmac->mux_handle) 989 mdio_mux_uninit(gmac->mux_handle); 990 if (gmac->internal_phy_powered) 991 sun8i_dwmac_unpower_internal_phy(gmac); 992 } 993 994 sun8i_dwmac_unset_syscon(gmac); 995 996 reset_control_put(gmac->rst_ephy); 997 998 clk_disable_unprepare(gmac->tx_clk); 999 1000 if (gmac->regulator) 1001 regulator_disable(gmac->regulator); 1002 } 1003 1004 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1005 { 1006 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1007 1008 if (enable) 1009 value |= EMAC_LOOPBACK; 1010 else 1011 value &= ~EMAC_LOOPBACK; 1012 1013 writel(value, ioaddr + EMAC_BASIC_CTL0); 1014 } 1015 1016 static const struct stmmac_ops sun8i_dwmac_ops = { 1017 .core_init = sun8i_dwmac_core_init, 1018 .set_mac = sun8i_dwmac_set_mac, 1019 .dump_regs = sun8i_dwmac_dump_mac_regs, 1020 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1021 .set_filter = sun8i_dwmac_set_filter, 1022 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1023 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1024 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1025 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1026 }; 1027 1028 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1029 { 1030 struct mac_device_info *mac; 1031 struct stmmac_priv *priv = ppriv; 1032 int ret; 1033 1034 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1035 if (!mac) 1036 return NULL; 1037 1038 ret = sun8i_dwmac_set_syscon(priv); 1039 if (ret) 1040 return NULL; 1041 1042 mac->pcsr = priv->ioaddr; 1043 mac->mac = &sun8i_dwmac_ops; 1044 mac->dma = &sun8i_dwmac_dma_ops; 1045 1046 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1047 1048 /* The loopback bit seems to be re-set when link change 1049 * Simply mask it each time 1050 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1051 */ 1052 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1053 mac->link.speed10 = EMAC_SPEED_10; 1054 mac->link.speed100 = EMAC_SPEED_100; 1055 mac->link.speed1000 = EMAC_SPEED_1000; 1056 mac->link.duplex = EMAC_DUPLEX_FULL; 1057 mac->mii.addr = EMAC_MDIO_CMD; 1058 mac->mii.data = EMAC_MDIO_DATA; 1059 mac->mii.reg_shift = 4; 1060 mac->mii.reg_mask = GENMASK(8, 4); 1061 mac->mii.addr_shift = 12; 1062 mac->mii.addr_mask = GENMASK(16, 12); 1063 mac->mii.clk_csr_shift = 20; 1064 mac->mii.clk_csr_mask = GENMASK(22, 20); 1065 mac->unicast_filter_entries = 8; 1066 1067 /* Synopsys Id is not available */ 1068 priv->synopsys_id = 0; 1069 1070 return mac; 1071 } 1072 1073 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1074 { 1075 struct device_node *syscon_node; 1076 struct platform_device *syscon_pdev; 1077 struct regmap *regmap = NULL; 1078 1079 syscon_node = of_parse_phandle(node, "syscon", 0); 1080 if (!syscon_node) 1081 return ERR_PTR(-ENODEV); 1082 1083 syscon_pdev = of_find_device_by_node(syscon_node); 1084 if (!syscon_pdev) { 1085 /* platform device might not be probed yet */ 1086 regmap = ERR_PTR(-EPROBE_DEFER); 1087 goto out_put_node; 1088 } 1089 1090 /* If no regmap is found then the other device driver is at fault */ 1091 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1092 if (!regmap) 1093 regmap = ERR_PTR(-EINVAL); 1094 1095 platform_device_put(syscon_pdev); 1096 out_put_node: 1097 of_node_put(syscon_node); 1098 return regmap; 1099 } 1100 1101 static int sun8i_dwmac_probe(struct platform_device *pdev) 1102 { 1103 struct plat_stmmacenet_data *plat_dat; 1104 struct stmmac_resources stmmac_res; 1105 struct sunxi_priv_data *gmac; 1106 struct device *dev = &pdev->dev; 1107 int ret; 1108 struct stmmac_priv *priv; 1109 struct net_device *ndev; 1110 struct regmap *regmap; 1111 1112 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1113 if (ret) 1114 return ret; 1115 1116 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1117 if (IS_ERR(plat_dat)) 1118 return PTR_ERR(plat_dat); 1119 1120 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1121 if (!gmac) 1122 return -ENOMEM; 1123 1124 gmac->variant = of_device_get_match_data(&pdev->dev); 1125 if (!gmac->variant) { 1126 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1127 return -EINVAL; 1128 } 1129 1130 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1131 if (IS_ERR(gmac->tx_clk)) { 1132 dev_err(dev, "Could not get TX clock\n"); 1133 return PTR_ERR(gmac->tx_clk); 1134 } 1135 1136 /* Optional regulator for PHY */ 1137 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1138 if (IS_ERR(gmac->regulator)) { 1139 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1140 return -EPROBE_DEFER; 1141 dev_info(dev, "No regulator found\n"); 1142 gmac->regulator = NULL; 1143 } 1144 1145 /* The "GMAC clock control" register might be located in the 1146 * CCU address range (on the R40), or the system control address 1147 * range (on most other sun8i and later SoCs). 1148 * 1149 * The former controls most if not all clocks in the SoC. The 1150 * latter has an SoC identification register, and on some SoCs, 1151 * controls to map device specific SRAM to either the intended 1152 * peripheral, or the CPU address space. 1153 * 1154 * In either case, there should be a coordinated and restricted 1155 * method of accessing the register needed here. This is done by 1156 * having the device export a custom regmap, instead of a generic 1157 * syscon, which grants all access to all registers. 1158 * 1159 * To support old device trees, we fall back to using the syscon 1160 * interface if possible. 1161 */ 1162 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1163 if (IS_ERR(regmap)) 1164 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1165 "syscon"); 1166 if (IS_ERR(regmap)) { 1167 ret = PTR_ERR(regmap); 1168 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1169 return ret; 1170 } 1171 1172 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1173 *gmac->variant->syscon_field); 1174 if (IS_ERR(gmac->regmap_field)) { 1175 ret = PTR_ERR(gmac->regmap_field); 1176 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1177 return ret; 1178 } 1179 1180 ret = of_get_phy_mode(dev->of_node); 1181 if (ret < 0) 1182 return -EINVAL; 1183 plat_dat->interface = ret; 1184 1185 /* platform data specifying hardware features and callbacks. 1186 * hardware features were copied from Allwinner drivers. 1187 */ 1188 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1189 plat_dat->tx_coe = 1; 1190 plat_dat->has_sun8i = true; 1191 plat_dat->bsp_priv = gmac; 1192 plat_dat->init = sun8i_dwmac_init; 1193 plat_dat->exit = sun8i_dwmac_exit; 1194 plat_dat->setup = sun8i_dwmac_setup; 1195 1196 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1197 if (ret) 1198 return ret; 1199 1200 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1201 if (ret) 1202 goto dwmac_exit; 1203 1204 ndev = dev_get_drvdata(&pdev->dev); 1205 priv = netdev_priv(ndev); 1206 /* The mux must be registered after parent MDIO 1207 * so after stmmac_dvr_probe() 1208 */ 1209 if (gmac->variant->soc_has_internal_phy) { 1210 ret = get_ephy_nodes(priv); 1211 if (ret) 1212 goto dwmac_exit; 1213 ret = sun8i_dwmac_register_mdio_mux(priv); 1214 if (ret) { 1215 dev_err(&pdev->dev, "Failed to register mux\n"); 1216 goto dwmac_mux; 1217 } 1218 } else { 1219 ret = sun8i_dwmac_reset(priv); 1220 if (ret) 1221 goto dwmac_exit; 1222 } 1223 1224 return ret; 1225 dwmac_mux: 1226 sun8i_dwmac_unset_syscon(gmac); 1227 dwmac_exit: 1228 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); 1229 return ret; 1230 } 1231 1232 static const struct of_device_id sun8i_dwmac_match[] = { 1233 { .compatible = "allwinner,sun8i-h3-emac", 1234 .data = &emac_variant_h3 }, 1235 { .compatible = "allwinner,sun8i-v3s-emac", 1236 .data = &emac_variant_v3s }, 1237 { .compatible = "allwinner,sun8i-a83t-emac", 1238 .data = &emac_variant_a83t }, 1239 { .compatible = "allwinner,sun8i-r40-gmac", 1240 .data = &emac_variant_r40 }, 1241 { .compatible = "allwinner,sun50i-a64-emac", 1242 .data = &emac_variant_a64 }, 1243 { .compatible = "allwinner,sun50i-h6-emac", 1244 .data = &emac_variant_h6 }, 1245 { } 1246 }; 1247 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1248 1249 static struct platform_driver sun8i_dwmac_driver = { 1250 .probe = sun8i_dwmac_probe, 1251 .remove = stmmac_pltfr_remove, 1252 .driver = { 1253 .name = "dwmac-sun8i", 1254 .pm = &stmmac_pltfr_pm_ops, 1255 .of_match_table = sun8i_dwmac_match, 1256 }, 1257 }; 1258 module_platform_driver(sun8i_dwmac_driver); 1259 1260 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1261 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1262 MODULE_LICENSE("GPL"); 1263