1 /* 2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 3 * 4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/mdio-mux.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/phy.h> 27 #include <linux/platform_device.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/regmap.h> 30 #include <linux/stmmac.h> 31 32 #include "stmmac.h" 33 #include "stmmac_platform.h" 34 35 /* General notes on dwmac-sun8i: 36 * Locking: no locking is necessary in this file because all necessary locking 37 * is done in the "stmmac files" 38 */ 39 40 /* struct emac_variant - Describe dwmac-sun8i hardware variant 41 * @default_syscon_value: The default value of the EMAC register in syscon 42 * This value is used for disabling properly EMAC 43 * and used as a good starting value in case of the 44 * boot process(uboot) leave some stuff. 45 * @syscon_field reg_field for the syscon's gmac register 46 * @soc_has_internal_phy: Does the MAC embed an internal PHY 47 * @support_mii: Does the MAC handle MII 48 * @support_rmii: Does the MAC handle RMII 49 * @support_rgmii: Does the MAC handle RGMII 50 * 51 * @rx_delay_max: Maximum raw value for RX delay chain 52 * @tx_delay_max: Maximum raw value for TX delay chain 53 * These two also indicate the bitmask for 54 * the RX and TX delay chain registers. A 55 * value of zero indicates this is not supported. 56 */ 57 struct emac_variant { 58 u32 default_syscon_value; 59 const struct reg_field *syscon_field; 60 bool soc_has_internal_phy; 61 bool support_mii; 62 bool support_rmii; 63 bool support_rgmii; 64 u8 rx_delay_max; 65 u8 tx_delay_max; 66 }; 67 68 /* struct sunxi_priv_data - hold all sunxi private data 69 * @tx_clk: reference to MAC TX clock 70 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 71 * @regulator: reference to the optional regulator 72 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 73 * @variant: reference to the current board variant 74 * @regmap: regmap for using the syscon 75 * @internal_phy_powered: Does the internal PHY is enabled 76 * @mux_handle: Internal pointer used by mdio-mux lib 77 */ 78 struct sunxi_priv_data { 79 struct clk *tx_clk; 80 struct clk *ephy_clk; 81 struct regulator *regulator; 82 struct reset_control *rst_ephy; 83 const struct emac_variant *variant; 84 struct regmap_field *regmap_field; 85 bool internal_phy_powered; 86 void *mux_handle; 87 }; 88 89 /* EMAC clock register @ 0x30 in the "system control" address range */ 90 static const struct reg_field sun8i_syscon_reg_field = { 91 .reg = 0x30, 92 .lsb = 0, 93 .msb = 31, 94 }; 95 96 /* EMAC clock register @ 0x164 in the CCU address range */ 97 static const struct reg_field sun8i_ccu_reg_field = { 98 .reg = 0x164, 99 .lsb = 0, 100 .msb = 31, 101 }; 102 103 static const struct emac_variant emac_variant_h3 = { 104 .default_syscon_value = 0x58000, 105 .syscon_field = &sun8i_syscon_reg_field, 106 .soc_has_internal_phy = true, 107 .support_mii = true, 108 .support_rmii = true, 109 .support_rgmii = true, 110 .rx_delay_max = 31, 111 .tx_delay_max = 7, 112 }; 113 114 static const struct emac_variant emac_variant_v3s = { 115 .default_syscon_value = 0x38000, 116 .syscon_field = &sun8i_syscon_reg_field, 117 .soc_has_internal_phy = true, 118 .support_mii = true 119 }; 120 121 static const struct emac_variant emac_variant_a83t = { 122 .default_syscon_value = 0, 123 .syscon_field = &sun8i_syscon_reg_field, 124 .soc_has_internal_phy = false, 125 .support_mii = true, 126 .support_rgmii = true, 127 .rx_delay_max = 31, 128 .tx_delay_max = 7, 129 }; 130 131 static const struct emac_variant emac_variant_r40 = { 132 .default_syscon_value = 0, 133 .syscon_field = &sun8i_ccu_reg_field, 134 .support_mii = true, 135 .support_rgmii = true, 136 .rx_delay_max = 7, 137 }; 138 139 static const struct emac_variant emac_variant_a64 = { 140 .default_syscon_value = 0, 141 .syscon_field = &sun8i_syscon_reg_field, 142 .soc_has_internal_phy = false, 143 .support_mii = true, 144 .support_rmii = true, 145 .support_rgmii = true, 146 .rx_delay_max = 31, 147 .tx_delay_max = 7, 148 }; 149 150 #define EMAC_BASIC_CTL0 0x00 151 #define EMAC_BASIC_CTL1 0x04 152 #define EMAC_INT_STA 0x08 153 #define EMAC_INT_EN 0x0C 154 #define EMAC_TX_CTL0 0x10 155 #define EMAC_TX_CTL1 0x14 156 #define EMAC_TX_FLOW_CTL 0x1C 157 #define EMAC_TX_DESC_LIST 0x20 158 #define EMAC_RX_CTL0 0x24 159 #define EMAC_RX_CTL1 0x28 160 #define EMAC_RX_DESC_LIST 0x34 161 #define EMAC_RX_FRM_FLT 0x38 162 #define EMAC_MDIO_CMD 0x48 163 #define EMAC_MDIO_DATA 0x4C 164 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 165 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 166 #define EMAC_TX_DMA_STA 0xB0 167 #define EMAC_TX_CUR_DESC 0xB4 168 #define EMAC_TX_CUR_BUF 0xB8 169 #define EMAC_RX_DMA_STA 0xC0 170 #define EMAC_RX_CUR_DESC 0xC4 171 #define EMAC_RX_CUR_BUF 0xC8 172 173 /* Use in EMAC_BASIC_CTL0 */ 174 #define EMAC_DUPLEX_FULL BIT(0) 175 #define EMAC_LOOPBACK BIT(1) 176 #define EMAC_SPEED_1000 0 177 #define EMAC_SPEED_100 (0x03 << 2) 178 #define EMAC_SPEED_10 (0x02 << 2) 179 180 /* Use in EMAC_BASIC_CTL1 */ 181 #define EMAC_BURSTLEN_SHIFT 24 182 183 /* Used in EMAC_RX_FRM_FLT */ 184 #define EMAC_FRM_FLT_RXALL BIT(0) 185 #define EMAC_FRM_FLT_CTL BIT(13) 186 #define EMAC_FRM_FLT_MULTICAST BIT(16) 187 188 /* Used in RX_CTL1*/ 189 #define EMAC_RX_MD BIT(1) 190 #define EMAC_RX_TH_MASK GENMASK(4, 5) 191 #define EMAC_RX_TH_32 0 192 #define EMAC_RX_TH_64 (0x1 << 4) 193 #define EMAC_RX_TH_96 (0x2 << 4) 194 #define EMAC_RX_TH_128 (0x3 << 4) 195 #define EMAC_RX_DMA_EN BIT(30) 196 #define EMAC_RX_DMA_START BIT(31) 197 198 /* Used in TX_CTL1*/ 199 #define EMAC_TX_MD BIT(1) 200 #define EMAC_TX_NEXT_FRM BIT(2) 201 #define EMAC_TX_TH_MASK GENMASK(8, 10) 202 #define EMAC_TX_TH_64 0 203 #define EMAC_TX_TH_128 (0x1 << 8) 204 #define EMAC_TX_TH_192 (0x2 << 8) 205 #define EMAC_TX_TH_256 (0x3 << 8) 206 #define EMAC_TX_DMA_EN BIT(30) 207 #define EMAC_TX_DMA_START BIT(31) 208 209 /* Used in RX_CTL0 */ 210 #define EMAC_RX_RECEIVER_EN BIT(31) 211 #define EMAC_RX_DO_CRC BIT(27) 212 #define EMAC_RX_FLOW_CTL_EN BIT(16) 213 214 /* Used in TX_CTL0 */ 215 #define EMAC_TX_TRANSMITTER_EN BIT(31) 216 217 /* Used in EMAC_TX_FLOW_CTL */ 218 #define EMAC_TX_FLOW_CTL_EN BIT(0) 219 220 /* Used in EMAC_INT_STA */ 221 #define EMAC_TX_INT BIT(0) 222 #define EMAC_TX_DMA_STOP_INT BIT(1) 223 #define EMAC_TX_BUF_UA_INT BIT(2) 224 #define EMAC_TX_TIMEOUT_INT BIT(3) 225 #define EMAC_TX_UNDERFLOW_INT BIT(4) 226 #define EMAC_TX_EARLY_INT BIT(5) 227 #define EMAC_RX_INT BIT(8) 228 #define EMAC_RX_BUF_UA_INT BIT(9) 229 #define EMAC_RX_DMA_STOP_INT BIT(10) 230 #define EMAC_RX_TIMEOUT_INT BIT(11) 231 #define EMAC_RX_OVERFLOW_INT BIT(12) 232 #define EMAC_RX_EARLY_INT BIT(13) 233 #define EMAC_RGMII_STA_INT BIT(16) 234 235 #define MAC_ADDR_TYPE_DST BIT(31) 236 237 /* H3 specific bits for EPHY */ 238 #define H3_EPHY_ADDR_SHIFT 20 239 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 240 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 241 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 242 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 243 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 244 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 245 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 246 247 /* H3/A64 specific bits */ 248 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 249 250 /* Generic system control EMAC_CLK bits */ 251 #define SYSCON_ETXDC_SHIFT 10 252 #define SYSCON_ERXDC_SHIFT 5 253 /* EMAC PHY Interface Type */ 254 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 255 #define SYSCON_ETCS_MASK GENMASK(1, 0) 256 #define SYSCON_ETCS_MII 0x0 257 #define SYSCON_ETCS_EXT_GMII 0x1 258 #define SYSCON_ETCS_INT_GMII 0x2 259 260 /* sun8i_dwmac_dma_reset() - reset the EMAC 261 * Called from stmmac via stmmac_dma_ops->reset 262 */ 263 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 264 { 265 writel(0, ioaddr + EMAC_RX_CTL1); 266 writel(0, ioaddr + EMAC_TX_CTL1); 267 writel(0, ioaddr + EMAC_RX_FRM_FLT); 268 writel(0, ioaddr + EMAC_RX_DESC_LIST); 269 writel(0, ioaddr + EMAC_TX_DESC_LIST); 270 writel(0, ioaddr + EMAC_INT_EN); 271 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 272 return 0; 273 } 274 275 /* sun8i_dwmac_dma_init() - initialize the EMAC 276 * Called from stmmac via stmmac_dma_ops->init 277 */ 278 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 279 struct stmmac_dma_cfg *dma_cfg, int atds) 280 { 281 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 282 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 283 } 284 285 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 286 struct stmmac_dma_cfg *dma_cfg, 287 u32 dma_rx_phy, u32 chan) 288 { 289 /* Write RX descriptors address */ 290 writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST); 291 } 292 293 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 294 struct stmmac_dma_cfg *dma_cfg, 295 u32 dma_tx_phy, u32 chan) 296 { 297 /* Write TX descriptors address */ 298 writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST); 299 } 300 301 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 302 * Called from stmmac_dma_ops->dump_regs 303 * Used for ethtool 304 */ 305 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 306 { 307 int i; 308 309 for (i = 0; i < 0xC8; i += 4) { 310 if (i == 0x32 || i == 0x3C) 311 continue; 312 reg_space[i / 4] = readl(ioaddr + i); 313 } 314 } 315 316 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 317 * Called from stmmac_ops->dump_regs 318 * Used for ethtool 319 */ 320 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 321 u32 *reg_space) 322 { 323 int i; 324 void __iomem *ioaddr = hw->pcsr; 325 326 for (i = 0; i < 0xC8; i += 4) { 327 if (i == 0x32 || i == 0x3C) 328 continue; 329 reg_space[i / 4] = readl(ioaddr + i); 330 } 331 } 332 333 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) 334 { 335 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 336 } 337 338 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 339 { 340 writel(0, ioaddr + EMAC_INT_EN); 341 } 342 343 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 344 { 345 u32 v; 346 347 v = readl(ioaddr + EMAC_TX_CTL1); 348 v |= EMAC_TX_DMA_START; 349 v |= EMAC_TX_DMA_EN; 350 writel(v, ioaddr + EMAC_TX_CTL1); 351 } 352 353 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 354 { 355 u32 v; 356 357 v = readl(ioaddr + EMAC_TX_CTL1); 358 v |= EMAC_TX_DMA_START; 359 v |= EMAC_TX_DMA_EN; 360 writel(v, ioaddr + EMAC_TX_CTL1); 361 } 362 363 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 364 { 365 u32 v; 366 367 v = readl(ioaddr + EMAC_TX_CTL1); 368 v &= ~EMAC_TX_DMA_EN; 369 writel(v, ioaddr + EMAC_TX_CTL1); 370 } 371 372 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 373 { 374 u32 v; 375 376 v = readl(ioaddr + EMAC_RX_CTL1); 377 v |= EMAC_RX_DMA_START; 378 v |= EMAC_RX_DMA_EN; 379 writel(v, ioaddr + EMAC_RX_CTL1); 380 } 381 382 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 383 { 384 u32 v; 385 386 v = readl(ioaddr + EMAC_RX_CTL1); 387 v &= ~EMAC_RX_DMA_EN; 388 writel(v, ioaddr + EMAC_RX_CTL1); 389 } 390 391 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 392 struct stmmac_extra_stats *x, u32 chan) 393 { 394 u32 v; 395 int ret = 0; 396 397 v = readl(ioaddr + EMAC_INT_STA); 398 399 if (v & EMAC_TX_INT) { 400 ret |= handle_tx; 401 x->tx_normal_irq_n++; 402 } 403 404 if (v & EMAC_TX_DMA_STOP_INT) 405 x->tx_process_stopped_irq++; 406 407 if (v & EMAC_TX_BUF_UA_INT) 408 x->tx_process_stopped_irq++; 409 410 if (v & EMAC_TX_TIMEOUT_INT) 411 ret |= tx_hard_error; 412 413 if (v & EMAC_TX_UNDERFLOW_INT) { 414 ret |= tx_hard_error; 415 x->tx_undeflow_irq++; 416 } 417 418 if (v & EMAC_TX_EARLY_INT) 419 x->tx_early_irq++; 420 421 if (v & EMAC_RX_INT) { 422 ret |= handle_rx; 423 x->rx_normal_irq_n++; 424 } 425 426 if (v & EMAC_RX_BUF_UA_INT) 427 x->rx_buf_unav_irq++; 428 429 if (v & EMAC_RX_DMA_STOP_INT) 430 x->rx_process_stopped_irq++; 431 432 if (v & EMAC_RX_TIMEOUT_INT) 433 ret |= tx_hard_error; 434 435 if (v & EMAC_RX_OVERFLOW_INT) { 436 ret |= tx_hard_error; 437 x->rx_overflow_irq++; 438 } 439 440 if (v & EMAC_RX_EARLY_INT) 441 x->rx_early_irq++; 442 443 if (v & EMAC_RGMII_STA_INT) 444 x->irq_rgmii_n++; 445 446 writel(v, ioaddr + EMAC_INT_STA); 447 448 return ret; 449 } 450 451 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 452 u32 channel, int fifosz, u8 qmode) 453 { 454 u32 v; 455 456 v = readl(ioaddr + EMAC_RX_CTL1); 457 if (mode == SF_DMA_MODE) { 458 v |= EMAC_RX_MD; 459 } else { 460 v &= ~EMAC_RX_MD; 461 v &= ~EMAC_RX_TH_MASK; 462 if (mode < 32) 463 v |= EMAC_RX_TH_32; 464 else if (mode < 64) 465 v |= EMAC_RX_TH_64; 466 else if (mode < 96) 467 v |= EMAC_RX_TH_96; 468 else if (mode < 128) 469 v |= EMAC_RX_TH_128; 470 } 471 writel(v, ioaddr + EMAC_RX_CTL1); 472 } 473 474 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 475 u32 channel, int fifosz, u8 qmode) 476 { 477 u32 v; 478 479 v = readl(ioaddr + EMAC_TX_CTL1); 480 if (mode == SF_DMA_MODE) { 481 v |= EMAC_TX_MD; 482 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 483 * comment is 484 * "Operating on second frame increase the performance 485 * especially when transmit store-and-forward is used." 486 */ 487 v |= EMAC_TX_NEXT_FRM; 488 } else { 489 v &= ~EMAC_TX_MD; 490 v &= ~EMAC_TX_TH_MASK; 491 if (mode < 64) 492 v |= EMAC_TX_TH_64; 493 else if (mode < 128) 494 v |= EMAC_TX_TH_128; 495 else if (mode < 192) 496 v |= EMAC_TX_TH_192; 497 else if (mode < 256) 498 v |= EMAC_TX_TH_256; 499 } 500 writel(v, ioaddr + EMAC_TX_CTL1); 501 } 502 503 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 504 .reset = sun8i_dwmac_dma_reset, 505 .init = sun8i_dwmac_dma_init, 506 .init_rx_chan = sun8i_dwmac_dma_init_rx, 507 .init_tx_chan = sun8i_dwmac_dma_init_tx, 508 .dump_regs = sun8i_dwmac_dump_regs, 509 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 510 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 511 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 512 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 513 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 514 .start_tx = sun8i_dwmac_dma_start_tx, 515 .stop_tx = sun8i_dwmac_dma_stop_tx, 516 .start_rx = sun8i_dwmac_dma_start_rx, 517 .stop_rx = sun8i_dwmac_dma_stop_rx, 518 .dma_interrupt = sun8i_dwmac_dma_interrupt, 519 }; 520 521 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 522 { 523 struct sunxi_priv_data *gmac = priv; 524 int ret; 525 526 if (gmac->regulator) { 527 ret = regulator_enable(gmac->regulator); 528 if (ret) { 529 dev_err(&pdev->dev, "Fail to enable regulator\n"); 530 return ret; 531 } 532 } 533 534 ret = clk_prepare_enable(gmac->tx_clk); 535 if (ret) { 536 if (gmac->regulator) 537 regulator_disable(gmac->regulator); 538 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 539 return ret; 540 } 541 542 return 0; 543 } 544 545 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 546 struct net_device *dev) 547 { 548 void __iomem *ioaddr = hw->pcsr; 549 u32 v; 550 551 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 552 writel(v, ioaddr + EMAC_BASIC_CTL1); 553 } 554 555 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 556 { 557 u32 t, r; 558 559 t = readl(ioaddr + EMAC_TX_CTL0); 560 r = readl(ioaddr + EMAC_RX_CTL0); 561 if (enable) { 562 t |= EMAC_TX_TRANSMITTER_EN; 563 r |= EMAC_RX_RECEIVER_EN; 564 } else { 565 t &= ~EMAC_TX_TRANSMITTER_EN; 566 r &= ~EMAC_RX_RECEIVER_EN; 567 } 568 writel(t, ioaddr + EMAC_TX_CTL0); 569 writel(r, ioaddr + EMAC_RX_CTL0); 570 } 571 572 /* Set MAC address at slot reg_n 573 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 574 * If addr is NULL, clear the slot 575 */ 576 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 577 unsigned char *addr, 578 unsigned int reg_n) 579 { 580 void __iomem *ioaddr = hw->pcsr; 581 u32 v; 582 583 if (!addr) { 584 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 585 return; 586 } 587 588 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 589 EMAC_MACADDR_LO(reg_n)); 590 if (reg_n > 0) { 591 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 592 v |= MAC_ADDR_TYPE_DST; 593 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 594 } 595 } 596 597 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 598 unsigned char *addr, 599 unsigned int reg_n) 600 { 601 void __iomem *ioaddr = hw->pcsr; 602 603 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 604 EMAC_MACADDR_LO(reg_n)); 605 } 606 607 /* caution this function must return non 0 to work */ 608 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 609 { 610 void __iomem *ioaddr = hw->pcsr; 611 u32 v; 612 613 v = readl(ioaddr + EMAC_RX_CTL0); 614 v |= EMAC_RX_DO_CRC; 615 writel(v, ioaddr + EMAC_RX_CTL0); 616 617 return 1; 618 } 619 620 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 621 struct net_device *dev) 622 { 623 void __iomem *ioaddr = hw->pcsr; 624 u32 v; 625 int i = 1; 626 struct netdev_hw_addr *ha; 627 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 628 629 v = EMAC_FRM_FLT_CTL; 630 631 if (dev->flags & IFF_PROMISC) { 632 v = EMAC_FRM_FLT_RXALL; 633 } else if (dev->flags & IFF_ALLMULTI) { 634 v |= EMAC_FRM_FLT_MULTICAST; 635 } else if (macaddrs <= hw->unicast_filter_entries) { 636 if (!netdev_mc_empty(dev)) { 637 netdev_for_each_mc_addr(ha, dev) { 638 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 639 i++; 640 } 641 } 642 if (!netdev_uc_empty(dev)) { 643 netdev_for_each_uc_addr(ha, dev) { 644 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 645 i++; 646 } 647 } 648 } else { 649 netdev_info(dev, "Too many address, switching to promiscuous\n"); 650 v = EMAC_FRM_FLT_RXALL; 651 } 652 653 /* Disable unused address filter slots */ 654 while (i < hw->unicast_filter_entries) 655 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 656 657 writel(v, ioaddr + EMAC_RX_FRM_FLT); 658 } 659 660 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 661 unsigned int duplex, unsigned int fc, 662 unsigned int pause_time, u32 tx_cnt) 663 { 664 void __iomem *ioaddr = hw->pcsr; 665 u32 v; 666 667 v = readl(ioaddr + EMAC_RX_CTL0); 668 if (fc == FLOW_AUTO) 669 v |= EMAC_RX_FLOW_CTL_EN; 670 else 671 v &= ~EMAC_RX_FLOW_CTL_EN; 672 writel(v, ioaddr + EMAC_RX_CTL0); 673 674 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 675 if (fc == FLOW_AUTO) 676 v |= EMAC_TX_FLOW_CTL_EN; 677 else 678 v &= ~EMAC_TX_FLOW_CTL_EN; 679 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 680 } 681 682 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 683 { 684 u32 v; 685 int err; 686 687 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 688 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 689 690 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 691 * need more if no cable plugged. 100ms seems OK 692 */ 693 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 694 !(v & 0x01), 100, 100000); 695 696 if (err) { 697 dev_err(priv->device, "EMAC reset timeout\n"); 698 return -EFAULT; 699 } 700 return 0; 701 } 702 703 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 704 static int get_ephy_nodes(struct stmmac_priv *priv) 705 { 706 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 707 struct device_node *mdio_mux, *iphynode; 708 struct device_node *mdio_internal; 709 int ret; 710 711 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 712 if (!mdio_mux) { 713 dev_err(priv->device, "Cannot get mdio-mux node\n"); 714 return -ENODEV; 715 } 716 717 mdio_internal = of_find_compatible_node(mdio_mux, NULL, 718 "allwinner,sun8i-h3-mdio-internal"); 719 if (!mdio_internal) { 720 dev_err(priv->device, "Cannot get internal_mdio node\n"); 721 return -ENODEV; 722 } 723 724 /* Seek for internal PHY */ 725 for_each_child_of_node(mdio_internal, iphynode) { 726 gmac->ephy_clk = of_clk_get(iphynode, 0); 727 if (IS_ERR(gmac->ephy_clk)) 728 continue; 729 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 730 if (IS_ERR(gmac->rst_ephy)) { 731 ret = PTR_ERR(gmac->rst_ephy); 732 if (ret == -EPROBE_DEFER) 733 return ret; 734 continue; 735 } 736 dev_info(priv->device, "Found internal PHY node\n"); 737 return 0; 738 } 739 return -ENODEV; 740 } 741 742 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 743 { 744 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 745 int ret; 746 747 if (gmac->internal_phy_powered) { 748 dev_warn(priv->device, "Internal PHY already powered\n"); 749 return 0; 750 } 751 752 dev_info(priv->device, "Powering internal PHY\n"); 753 ret = clk_prepare_enable(gmac->ephy_clk); 754 if (ret) { 755 dev_err(priv->device, "Cannot enable internal PHY\n"); 756 return ret; 757 } 758 759 /* Make sure the EPHY is properly reseted, as U-Boot may leave 760 * it at deasserted state, and thus it may fail to reset EMAC. 761 */ 762 reset_control_assert(gmac->rst_ephy); 763 764 ret = reset_control_deassert(gmac->rst_ephy); 765 if (ret) { 766 dev_err(priv->device, "Cannot deassert internal phy\n"); 767 clk_disable_unprepare(gmac->ephy_clk); 768 return ret; 769 } 770 771 gmac->internal_phy_powered = true; 772 773 return 0; 774 } 775 776 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 777 { 778 if (!gmac->internal_phy_powered) 779 return 0; 780 781 clk_disable_unprepare(gmac->ephy_clk); 782 reset_control_assert(gmac->rst_ephy); 783 gmac->internal_phy_powered = false; 784 return 0; 785 } 786 787 /* MDIO multiplexing switch function 788 * This function is called by the mdio-mux layer when it thinks the mdio bus 789 * multiplexer needs to switch. 790 * 'current_child' is the current value of the mux register 791 * 'desired_child' is the value of the 'reg' property of the target child MDIO 792 * node. 793 * The first time this function is called, current_child == -1. 794 * If current_child == desired_child, then the mux is already set to the 795 * correct bus. 796 */ 797 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 798 void *data) 799 { 800 struct stmmac_priv *priv = data; 801 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 802 u32 reg, val; 803 int ret = 0; 804 bool need_power_ephy = false; 805 806 if (current_child ^ desired_child) { 807 regmap_field_read(gmac->regmap_field, ®); 808 switch (desired_child) { 809 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 810 dev_info(priv->device, "Switch mux to internal PHY"); 811 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 812 813 need_power_ephy = true; 814 break; 815 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 816 dev_info(priv->device, "Switch mux to external PHY"); 817 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 818 need_power_ephy = false; 819 break; 820 default: 821 dev_err(priv->device, "Invalid child ID %x\n", 822 desired_child); 823 return -EINVAL; 824 } 825 regmap_field_write(gmac->regmap_field, val); 826 if (need_power_ephy) { 827 ret = sun8i_dwmac_power_internal_phy(priv); 828 if (ret) 829 return ret; 830 } else { 831 sun8i_dwmac_unpower_internal_phy(gmac); 832 } 833 /* After changing syscon value, the MAC need reset or it will 834 * use the last value (and so the last PHY set). 835 */ 836 ret = sun8i_dwmac_reset(priv); 837 } 838 return ret; 839 } 840 841 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 842 { 843 int ret; 844 struct device_node *mdio_mux; 845 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 846 847 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 848 if (!mdio_mux) 849 return -ENODEV; 850 851 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 852 &gmac->mux_handle, priv, priv->mii); 853 return ret; 854 } 855 856 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 857 { 858 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 859 struct device_node *node = priv->device->of_node; 860 int ret; 861 u32 reg, val; 862 863 regmap_field_read(gmac->regmap_field, &val); 864 reg = gmac->variant->default_syscon_value; 865 if (reg != val) 866 dev_warn(priv->device, 867 "Current syscon value is not the default %x (expect %x)\n", 868 val, reg); 869 870 if (gmac->variant->soc_has_internal_phy) { 871 if (of_property_read_bool(node, "allwinner,leds-active-low")) 872 reg |= H3_EPHY_LED_POL; 873 else 874 reg &= ~H3_EPHY_LED_POL; 875 876 /* Force EPHY xtal frequency to 24MHz. */ 877 reg |= H3_EPHY_CLK_SEL; 878 879 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 880 if (ret < 0) { 881 dev_err(priv->device, "Could not parse MDIO addr\n"); 882 return ret; 883 } 884 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 885 * address. No need to mask it again. 886 */ 887 reg |= 1 << H3_EPHY_ADDR_SHIFT; 888 } 889 890 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 891 if (val % 100) { 892 dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 893 return -EINVAL; 894 } 895 val /= 100; 896 dev_dbg(priv->device, "set tx-delay to %x\n", val); 897 if (val <= gmac->variant->tx_delay_max) { 898 reg &= ~(gmac->variant->tx_delay_max << 899 SYSCON_ETXDC_SHIFT); 900 reg |= (val << SYSCON_ETXDC_SHIFT); 901 } else { 902 dev_err(priv->device, "Invalid TX clock delay: %d\n", 903 val); 904 return -EINVAL; 905 } 906 } 907 908 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 909 if (val % 100) { 910 dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 911 return -EINVAL; 912 } 913 val /= 100; 914 dev_dbg(priv->device, "set rx-delay to %x\n", val); 915 if (val <= gmac->variant->rx_delay_max) { 916 reg &= ~(gmac->variant->rx_delay_max << 917 SYSCON_ERXDC_SHIFT); 918 reg |= (val << SYSCON_ERXDC_SHIFT); 919 } else { 920 dev_err(priv->device, "Invalid RX clock delay: %d\n", 921 val); 922 return -EINVAL; 923 } 924 } 925 926 /* Clear interface mode bits */ 927 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 928 if (gmac->variant->support_rmii) 929 reg &= ~SYSCON_RMII_EN; 930 931 switch (priv->plat->interface) { 932 case PHY_INTERFACE_MODE_MII: 933 /* default */ 934 break; 935 case PHY_INTERFACE_MODE_RGMII: 936 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 937 break; 938 case PHY_INTERFACE_MODE_RMII: 939 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 940 break; 941 default: 942 dev_err(priv->device, "Unsupported interface mode: %s", 943 phy_modes(priv->plat->interface)); 944 return -EINVAL; 945 } 946 947 regmap_field_write(gmac->regmap_field, reg); 948 949 return 0; 950 } 951 952 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 953 { 954 u32 reg = gmac->variant->default_syscon_value; 955 956 regmap_field_write(gmac->regmap_field, reg); 957 } 958 959 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 960 { 961 struct sunxi_priv_data *gmac = priv; 962 963 if (gmac->variant->soc_has_internal_phy) { 964 /* sun8i_dwmac_exit could be called with mdiomux uninit */ 965 if (gmac->mux_handle) 966 mdio_mux_uninit(gmac->mux_handle); 967 if (gmac->internal_phy_powered) 968 sun8i_dwmac_unpower_internal_phy(gmac); 969 } 970 971 sun8i_dwmac_unset_syscon(gmac); 972 973 reset_control_put(gmac->rst_ephy); 974 975 clk_disable_unprepare(gmac->tx_clk); 976 977 if (gmac->regulator) 978 regulator_disable(gmac->regulator); 979 } 980 981 static const struct stmmac_ops sun8i_dwmac_ops = { 982 .core_init = sun8i_dwmac_core_init, 983 .set_mac = sun8i_dwmac_set_mac, 984 .dump_regs = sun8i_dwmac_dump_mac_regs, 985 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 986 .set_filter = sun8i_dwmac_set_filter, 987 .flow_ctrl = sun8i_dwmac_flow_ctrl, 988 .set_umac_addr = sun8i_dwmac_set_umac_addr, 989 .get_umac_addr = sun8i_dwmac_get_umac_addr, 990 }; 991 992 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 993 { 994 struct mac_device_info *mac; 995 struct stmmac_priv *priv = ppriv; 996 int ret; 997 998 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 999 if (!mac) 1000 return NULL; 1001 1002 ret = sun8i_dwmac_set_syscon(priv); 1003 if (ret) 1004 return NULL; 1005 1006 mac->pcsr = priv->ioaddr; 1007 mac->mac = &sun8i_dwmac_ops; 1008 mac->dma = &sun8i_dwmac_dma_ops; 1009 1010 /* The loopback bit seems to be re-set when link change 1011 * Simply mask it each time 1012 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1013 */ 1014 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1015 mac->link.speed10 = EMAC_SPEED_10; 1016 mac->link.speed100 = EMAC_SPEED_100; 1017 mac->link.speed1000 = EMAC_SPEED_1000; 1018 mac->link.duplex = EMAC_DUPLEX_FULL; 1019 mac->mii.addr = EMAC_MDIO_CMD; 1020 mac->mii.data = EMAC_MDIO_DATA; 1021 mac->mii.reg_shift = 4; 1022 mac->mii.reg_mask = GENMASK(8, 4); 1023 mac->mii.addr_shift = 12; 1024 mac->mii.addr_mask = GENMASK(16, 12); 1025 mac->mii.clk_csr_shift = 20; 1026 mac->mii.clk_csr_mask = GENMASK(22, 20); 1027 mac->unicast_filter_entries = 8; 1028 1029 /* Synopsys Id is not available */ 1030 priv->synopsys_id = 0; 1031 1032 return mac; 1033 } 1034 1035 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1036 { 1037 struct device_node *syscon_node; 1038 struct platform_device *syscon_pdev; 1039 struct regmap *regmap = NULL; 1040 1041 syscon_node = of_parse_phandle(node, "syscon", 0); 1042 if (!syscon_node) 1043 return ERR_PTR(-ENODEV); 1044 1045 syscon_pdev = of_find_device_by_node(syscon_node); 1046 if (!syscon_pdev) { 1047 /* platform device might not be probed yet */ 1048 regmap = ERR_PTR(-EPROBE_DEFER); 1049 goto out_put_node; 1050 } 1051 1052 /* If no regmap is found then the other device driver is at fault */ 1053 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1054 if (!regmap) 1055 regmap = ERR_PTR(-EINVAL); 1056 1057 platform_device_put(syscon_pdev); 1058 out_put_node: 1059 of_node_put(syscon_node); 1060 return regmap; 1061 } 1062 1063 static int sun8i_dwmac_probe(struct platform_device *pdev) 1064 { 1065 struct plat_stmmacenet_data *plat_dat; 1066 struct stmmac_resources stmmac_res; 1067 struct sunxi_priv_data *gmac; 1068 struct device *dev = &pdev->dev; 1069 int ret; 1070 struct stmmac_priv *priv; 1071 struct net_device *ndev; 1072 struct regmap *regmap; 1073 1074 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1075 if (ret) 1076 return ret; 1077 1078 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1079 if (IS_ERR(plat_dat)) 1080 return PTR_ERR(plat_dat); 1081 1082 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1083 if (!gmac) 1084 return -ENOMEM; 1085 1086 gmac->variant = of_device_get_match_data(&pdev->dev); 1087 if (!gmac->variant) { 1088 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1089 return -EINVAL; 1090 } 1091 1092 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1093 if (IS_ERR(gmac->tx_clk)) { 1094 dev_err(dev, "Could not get TX clock\n"); 1095 return PTR_ERR(gmac->tx_clk); 1096 } 1097 1098 /* Optional regulator for PHY */ 1099 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1100 if (IS_ERR(gmac->regulator)) { 1101 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1102 return -EPROBE_DEFER; 1103 dev_info(dev, "No regulator found\n"); 1104 gmac->regulator = NULL; 1105 } 1106 1107 /* The "GMAC clock control" register might be located in the 1108 * CCU address range (on the R40), or the system control address 1109 * range (on most other sun8i and later SoCs). 1110 * 1111 * The former controls most if not all clocks in the SoC. The 1112 * latter has an SoC identification register, and on some SoCs, 1113 * controls to map device specific SRAM to either the intended 1114 * peripheral, or the CPU address space. 1115 * 1116 * In either case, there should be a coordinated and restricted 1117 * method of accessing the register needed here. This is done by 1118 * having the device export a custom regmap, instead of a generic 1119 * syscon, which grants all access to all registers. 1120 * 1121 * To support old device trees, we fall back to using the syscon 1122 * interface if possible. 1123 */ 1124 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1125 if (IS_ERR(regmap)) 1126 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1127 "syscon"); 1128 if (IS_ERR(regmap)) { 1129 ret = PTR_ERR(regmap); 1130 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1131 return ret; 1132 } 1133 1134 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1135 *gmac->variant->syscon_field); 1136 if (IS_ERR(gmac->regmap_field)) { 1137 ret = PTR_ERR(gmac->regmap_field); 1138 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1139 return ret; 1140 } 1141 1142 plat_dat->interface = of_get_phy_mode(dev->of_node); 1143 1144 /* platform data specifying hardware features and callbacks. 1145 * hardware features were copied from Allwinner drivers. 1146 */ 1147 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1148 plat_dat->tx_coe = 1; 1149 plat_dat->has_sun8i = true; 1150 plat_dat->bsp_priv = gmac; 1151 plat_dat->init = sun8i_dwmac_init; 1152 plat_dat->exit = sun8i_dwmac_exit; 1153 plat_dat->setup = sun8i_dwmac_setup; 1154 1155 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1156 if (ret) 1157 return ret; 1158 1159 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1160 if (ret) 1161 goto dwmac_exit; 1162 1163 ndev = dev_get_drvdata(&pdev->dev); 1164 priv = netdev_priv(ndev); 1165 /* The mux must be registered after parent MDIO 1166 * so after stmmac_dvr_probe() 1167 */ 1168 if (gmac->variant->soc_has_internal_phy) { 1169 ret = get_ephy_nodes(priv); 1170 if (ret) 1171 goto dwmac_exit; 1172 ret = sun8i_dwmac_register_mdio_mux(priv); 1173 if (ret) { 1174 dev_err(&pdev->dev, "Failed to register mux\n"); 1175 goto dwmac_mux; 1176 } 1177 } else { 1178 ret = sun8i_dwmac_reset(priv); 1179 if (ret) 1180 goto dwmac_exit; 1181 } 1182 1183 return ret; 1184 dwmac_mux: 1185 sun8i_dwmac_unset_syscon(gmac); 1186 dwmac_exit: 1187 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); 1188 return ret; 1189 } 1190 1191 static const struct of_device_id sun8i_dwmac_match[] = { 1192 { .compatible = "allwinner,sun8i-h3-emac", 1193 .data = &emac_variant_h3 }, 1194 { .compatible = "allwinner,sun8i-v3s-emac", 1195 .data = &emac_variant_v3s }, 1196 { .compatible = "allwinner,sun8i-a83t-emac", 1197 .data = &emac_variant_a83t }, 1198 { .compatible = "allwinner,sun8i-r40-gmac", 1199 .data = &emac_variant_r40 }, 1200 { .compatible = "allwinner,sun50i-a64-emac", 1201 .data = &emac_variant_a64 }, 1202 { } 1203 }; 1204 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1205 1206 static struct platform_driver sun8i_dwmac_driver = { 1207 .probe = sun8i_dwmac_probe, 1208 .remove = stmmac_pltfr_remove, 1209 .driver = { 1210 .name = "dwmac-sun8i", 1211 .pm = &stmmac_pltfr_pm_ops, 1212 .of_match_table = sun8i_dwmac_match, 1213 }, 1214 }; 1215 module_platform_driver(sun8i_dwmac_driver); 1216 1217 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1218 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1219 MODULE_LICENSE("GPL"); 1220