1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/regmap.h> 22 #include <linux/stmmac.h> 23 24 #include "stmmac.h" 25 #include "stmmac_platform.h" 26 27 /* General notes on dwmac-sun8i: 28 * Locking: no locking is necessary in this file because all necessary locking 29 * is done in the "stmmac files" 30 */ 31 32 /* struct emac_variant - Describe dwmac-sun8i hardware variant 33 * @default_syscon_value: The default value of the EMAC register in syscon 34 * This value is used for disabling properly EMAC 35 * and used as a good starting value in case of the 36 * boot process(uboot) leave some stuff. 37 * @syscon_field reg_field for the syscon's gmac register 38 * @soc_has_internal_phy: Does the MAC embed an internal PHY 39 * @support_mii: Does the MAC handle MII 40 * @support_rmii: Does the MAC handle RMII 41 * @support_rgmii: Does the MAC handle RGMII 42 * 43 * @rx_delay_max: Maximum raw value for RX delay chain 44 * @tx_delay_max: Maximum raw value for TX delay chain 45 * These two also indicate the bitmask for 46 * the RX and TX delay chain registers. A 47 * value of zero indicates this is not supported. 48 */ 49 struct emac_variant { 50 u32 default_syscon_value; 51 const struct reg_field *syscon_field; 52 bool soc_has_internal_phy; 53 bool support_mii; 54 bool support_rmii; 55 bool support_rgmii; 56 u8 rx_delay_max; 57 u8 tx_delay_max; 58 }; 59 60 /* struct sunxi_priv_data - hold all sunxi private data 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @use_internal_phy: Is the internal PHY selected for use 68 * @mux_handle: Internal pointer used by mdio-mux lib 69 */ 70 struct sunxi_priv_data { 71 struct clk *ephy_clk; 72 struct regulator *regulator; 73 struct reset_control *rst_ephy; 74 const struct emac_variant *variant; 75 struct regmap_field *regmap_field; 76 bool internal_phy_powered; 77 bool use_internal_phy; 78 void *mux_handle; 79 }; 80 81 /* EMAC clock register @ 0x30 in the "system control" address range */ 82 static const struct reg_field sun8i_syscon_reg_field = { 83 .reg = 0x30, 84 .lsb = 0, 85 .msb = 31, 86 }; 87 88 /* EMAC clock register @ 0x164 in the CCU address range */ 89 static const struct reg_field sun8i_ccu_reg_field = { 90 .reg = 0x164, 91 .lsb = 0, 92 .msb = 31, 93 }; 94 95 static const struct emac_variant emac_variant_h3 = { 96 .default_syscon_value = 0x58000, 97 .syscon_field = &sun8i_syscon_reg_field, 98 .soc_has_internal_phy = true, 99 .support_mii = true, 100 .support_rmii = true, 101 .support_rgmii = true, 102 .rx_delay_max = 31, 103 .tx_delay_max = 7, 104 }; 105 106 static const struct emac_variant emac_variant_v3s = { 107 .default_syscon_value = 0x38000, 108 .syscon_field = &sun8i_syscon_reg_field, 109 .soc_has_internal_phy = true, 110 .support_mii = true 111 }; 112 113 static const struct emac_variant emac_variant_a83t = { 114 .default_syscon_value = 0, 115 .syscon_field = &sun8i_syscon_reg_field, 116 .soc_has_internal_phy = false, 117 .support_mii = true, 118 .support_rgmii = true, 119 .rx_delay_max = 31, 120 .tx_delay_max = 7, 121 }; 122 123 static const struct emac_variant emac_variant_r40 = { 124 .default_syscon_value = 0, 125 .syscon_field = &sun8i_ccu_reg_field, 126 .support_mii = true, 127 .support_rgmii = true, 128 .rx_delay_max = 7, 129 }; 130 131 static const struct emac_variant emac_variant_a64 = { 132 .default_syscon_value = 0, 133 .syscon_field = &sun8i_syscon_reg_field, 134 .soc_has_internal_phy = false, 135 .support_mii = true, 136 .support_rmii = true, 137 .support_rgmii = true, 138 .rx_delay_max = 31, 139 .tx_delay_max = 7, 140 }; 141 142 static const struct emac_variant emac_variant_h6 = { 143 .default_syscon_value = 0x50000, 144 .syscon_field = &sun8i_syscon_reg_field, 145 /* The "Internal PHY" of H6 is not on the die. It's on the 146 * co-packaged AC200 chip instead. 147 */ 148 .soc_has_internal_phy = false, 149 .support_mii = true, 150 .support_rmii = true, 151 .support_rgmii = true, 152 .rx_delay_max = 31, 153 .tx_delay_max = 7, 154 }; 155 156 #define EMAC_BASIC_CTL0 0x00 157 #define EMAC_BASIC_CTL1 0x04 158 #define EMAC_INT_STA 0x08 159 #define EMAC_INT_EN 0x0C 160 #define EMAC_TX_CTL0 0x10 161 #define EMAC_TX_CTL1 0x14 162 #define EMAC_TX_FLOW_CTL 0x1C 163 #define EMAC_TX_DESC_LIST 0x20 164 #define EMAC_RX_CTL0 0x24 165 #define EMAC_RX_CTL1 0x28 166 #define EMAC_RX_DESC_LIST 0x34 167 #define EMAC_RX_FRM_FLT 0x38 168 #define EMAC_MDIO_CMD 0x48 169 #define EMAC_MDIO_DATA 0x4C 170 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 171 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 172 #define EMAC_TX_DMA_STA 0xB0 173 #define EMAC_TX_CUR_DESC 0xB4 174 #define EMAC_TX_CUR_BUF 0xB8 175 #define EMAC_RX_DMA_STA 0xC0 176 #define EMAC_RX_CUR_DESC 0xC4 177 #define EMAC_RX_CUR_BUF 0xC8 178 179 /* Use in EMAC_BASIC_CTL0 */ 180 #define EMAC_DUPLEX_FULL BIT(0) 181 #define EMAC_LOOPBACK BIT(1) 182 #define EMAC_SPEED_1000 0 183 #define EMAC_SPEED_100 (0x03 << 2) 184 #define EMAC_SPEED_10 (0x02 << 2) 185 186 /* Use in EMAC_BASIC_CTL1 */ 187 #define EMAC_BURSTLEN_SHIFT 24 188 189 /* Used in EMAC_RX_FRM_FLT */ 190 #define EMAC_FRM_FLT_RXALL BIT(0) 191 #define EMAC_FRM_FLT_CTL BIT(13) 192 #define EMAC_FRM_FLT_MULTICAST BIT(16) 193 194 /* Used in RX_CTL1*/ 195 #define EMAC_RX_MD BIT(1) 196 #define EMAC_RX_TH_MASK GENMASK(5, 4) 197 #define EMAC_RX_TH_32 0 198 #define EMAC_RX_TH_64 (0x1 << 4) 199 #define EMAC_RX_TH_96 (0x2 << 4) 200 #define EMAC_RX_TH_128 (0x3 << 4) 201 #define EMAC_RX_DMA_EN BIT(30) 202 #define EMAC_RX_DMA_START BIT(31) 203 204 /* Used in TX_CTL1*/ 205 #define EMAC_TX_MD BIT(1) 206 #define EMAC_TX_NEXT_FRM BIT(2) 207 #define EMAC_TX_TH_MASK GENMASK(10, 8) 208 #define EMAC_TX_TH_64 0 209 #define EMAC_TX_TH_128 (0x1 << 8) 210 #define EMAC_TX_TH_192 (0x2 << 8) 211 #define EMAC_TX_TH_256 (0x3 << 8) 212 #define EMAC_TX_DMA_EN BIT(30) 213 #define EMAC_TX_DMA_START BIT(31) 214 215 /* Used in RX_CTL0 */ 216 #define EMAC_RX_RECEIVER_EN BIT(31) 217 #define EMAC_RX_DO_CRC BIT(27) 218 #define EMAC_RX_FLOW_CTL_EN BIT(16) 219 220 /* Used in TX_CTL0 */ 221 #define EMAC_TX_TRANSMITTER_EN BIT(31) 222 223 /* Used in EMAC_TX_FLOW_CTL */ 224 #define EMAC_TX_FLOW_CTL_EN BIT(0) 225 226 /* Used in EMAC_INT_STA */ 227 #define EMAC_TX_INT BIT(0) 228 #define EMAC_TX_DMA_STOP_INT BIT(1) 229 #define EMAC_TX_BUF_UA_INT BIT(2) 230 #define EMAC_TX_TIMEOUT_INT BIT(3) 231 #define EMAC_TX_UNDERFLOW_INT BIT(4) 232 #define EMAC_TX_EARLY_INT BIT(5) 233 #define EMAC_RX_INT BIT(8) 234 #define EMAC_RX_BUF_UA_INT BIT(9) 235 #define EMAC_RX_DMA_STOP_INT BIT(10) 236 #define EMAC_RX_TIMEOUT_INT BIT(11) 237 #define EMAC_RX_OVERFLOW_INT BIT(12) 238 #define EMAC_RX_EARLY_INT BIT(13) 239 #define EMAC_RGMII_STA_INT BIT(16) 240 241 #define EMAC_INT_MSK_COMMON EMAC_RGMII_STA_INT 242 #define EMAC_INT_MSK_TX (EMAC_TX_INT | \ 243 EMAC_TX_DMA_STOP_INT | \ 244 EMAC_TX_BUF_UA_INT | \ 245 EMAC_TX_TIMEOUT_INT | \ 246 EMAC_TX_UNDERFLOW_INT | \ 247 EMAC_TX_EARLY_INT |\ 248 EMAC_INT_MSK_COMMON) 249 #define EMAC_INT_MSK_RX (EMAC_RX_INT | \ 250 EMAC_RX_BUF_UA_INT | \ 251 EMAC_RX_DMA_STOP_INT | \ 252 EMAC_RX_TIMEOUT_INT | \ 253 EMAC_RX_OVERFLOW_INT | \ 254 EMAC_RX_EARLY_INT | \ 255 EMAC_INT_MSK_COMMON) 256 257 #define MAC_ADDR_TYPE_DST BIT(31) 258 259 /* H3 specific bits for EPHY */ 260 #define H3_EPHY_ADDR_SHIFT 20 261 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 262 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 263 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 264 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 265 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 266 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 267 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 268 269 /* H3/A64 specific bits */ 270 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 271 272 /* Generic system control EMAC_CLK bits */ 273 #define SYSCON_ETXDC_SHIFT 10 274 #define SYSCON_ERXDC_SHIFT 5 275 /* EMAC PHY Interface Type */ 276 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 277 #define SYSCON_ETCS_MASK GENMASK(1, 0) 278 #define SYSCON_ETCS_MII 0x0 279 #define SYSCON_ETCS_EXT_GMII 0x1 280 #define SYSCON_ETCS_INT_GMII 0x2 281 282 /* sun8i_dwmac_dma_reset() - reset the EMAC 283 * Called from stmmac via stmmac_dma_ops->reset 284 */ 285 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 286 { 287 writel(0, ioaddr + EMAC_RX_CTL1); 288 writel(0, ioaddr + EMAC_TX_CTL1); 289 writel(0, ioaddr + EMAC_RX_FRM_FLT); 290 writel(0, ioaddr + EMAC_RX_DESC_LIST); 291 writel(0, ioaddr + EMAC_TX_DESC_LIST); 292 writel(0, ioaddr + EMAC_INT_EN); 293 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 294 return 0; 295 } 296 297 /* sun8i_dwmac_dma_init() - initialize the EMAC 298 * Called from stmmac via stmmac_dma_ops->init 299 */ 300 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 301 struct stmmac_dma_cfg *dma_cfg, int atds) 302 { 303 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 304 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 305 } 306 307 static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv, 308 void __iomem *ioaddr, 309 struct stmmac_dma_cfg *dma_cfg, 310 dma_addr_t dma_rx_phy, u32 chan) 311 { 312 /* Write RX descriptors address */ 313 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 314 } 315 316 static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv, 317 void __iomem *ioaddr, 318 struct stmmac_dma_cfg *dma_cfg, 319 dma_addr_t dma_tx_phy, u32 chan) 320 { 321 /* Write TX descriptors address */ 322 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 323 } 324 325 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 326 * Called from stmmac_dma_ops->dump_regs 327 * Used for ethtool 328 */ 329 static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv, 330 void __iomem *ioaddr, u32 *reg_space) 331 { 332 int i; 333 334 for (i = 0; i < 0xC8; i += 4) { 335 if (i == 0x32 || i == 0x3C) 336 continue; 337 reg_space[i / 4] = readl(ioaddr + i); 338 } 339 } 340 341 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 342 * Called from stmmac_ops->dump_regs 343 * Used for ethtool 344 */ 345 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 346 u32 *reg_space) 347 { 348 int i; 349 void __iomem *ioaddr = hw->pcsr; 350 351 for (i = 0; i < 0xC8; i += 4) { 352 if (i == 0x32 || i == 0x3C) 353 continue; 354 reg_space[i / 4] = readl(ioaddr + i); 355 } 356 } 357 358 static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv, 359 void __iomem *ioaddr, u32 chan, 360 bool rx, bool tx) 361 { 362 u32 value = readl(ioaddr + EMAC_INT_EN); 363 364 if (rx) 365 value |= EMAC_RX_INT; 366 if (tx) 367 value |= EMAC_TX_INT; 368 369 writel(value, ioaddr + EMAC_INT_EN); 370 } 371 372 static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv, 373 void __iomem *ioaddr, u32 chan, 374 bool rx, bool tx) 375 { 376 u32 value = readl(ioaddr + EMAC_INT_EN); 377 378 if (rx) 379 value &= ~EMAC_RX_INT; 380 if (tx) 381 value &= ~EMAC_TX_INT; 382 383 writel(value, ioaddr + EMAC_INT_EN); 384 } 385 386 static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv, 387 void __iomem *ioaddr, u32 chan) 388 { 389 u32 v; 390 391 v = readl(ioaddr + EMAC_TX_CTL1); 392 v |= EMAC_TX_DMA_START; 393 v |= EMAC_TX_DMA_EN; 394 writel(v, ioaddr + EMAC_TX_CTL1); 395 } 396 397 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 398 { 399 u32 v; 400 401 v = readl(ioaddr + EMAC_TX_CTL1); 402 v |= EMAC_TX_DMA_START; 403 v |= EMAC_TX_DMA_EN; 404 writel(v, ioaddr + EMAC_TX_CTL1); 405 } 406 407 static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv, 408 void __iomem *ioaddr, u32 chan) 409 { 410 u32 v; 411 412 v = readl(ioaddr + EMAC_TX_CTL1); 413 v &= ~EMAC_TX_DMA_EN; 414 writel(v, ioaddr + EMAC_TX_CTL1); 415 } 416 417 static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv, 418 void __iomem *ioaddr, u32 chan) 419 { 420 u32 v; 421 422 v = readl(ioaddr + EMAC_RX_CTL1); 423 v |= EMAC_RX_DMA_START; 424 v |= EMAC_RX_DMA_EN; 425 writel(v, ioaddr + EMAC_RX_CTL1); 426 } 427 428 static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv, 429 void __iomem *ioaddr, u32 chan) 430 { 431 u32 v; 432 433 v = readl(ioaddr + EMAC_RX_CTL1); 434 v &= ~EMAC_RX_DMA_EN; 435 writel(v, ioaddr + EMAC_RX_CTL1); 436 } 437 438 static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv, 439 void __iomem *ioaddr, 440 struct stmmac_extra_stats *x, u32 chan, 441 u32 dir) 442 { 443 u32 v; 444 int ret = 0; 445 446 v = readl(ioaddr + EMAC_INT_STA); 447 448 if (dir == DMA_DIR_RX) 449 v &= EMAC_INT_MSK_RX; 450 else if (dir == DMA_DIR_TX) 451 v &= EMAC_INT_MSK_TX; 452 453 if (v & EMAC_TX_INT) { 454 ret |= handle_tx; 455 x->tx_normal_irq_n++; 456 } 457 458 if (v & EMAC_TX_DMA_STOP_INT) 459 x->tx_process_stopped_irq++; 460 461 if (v & EMAC_TX_BUF_UA_INT) 462 x->tx_process_stopped_irq++; 463 464 if (v & EMAC_TX_TIMEOUT_INT) 465 ret |= tx_hard_error; 466 467 if (v & EMAC_TX_UNDERFLOW_INT) { 468 ret |= tx_hard_error; 469 x->tx_undeflow_irq++; 470 } 471 472 if (v & EMAC_TX_EARLY_INT) 473 x->tx_early_irq++; 474 475 if (v & EMAC_RX_INT) { 476 ret |= handle_rx; 477 x->rx_normal_irq_n++; 478 } 479 480 if (v & EMAC_RX_BUF_UA_INT) 481 x->rx_buf_unav_irq++; 482 483 if (v & EMAC_RX_DMA_STOP_INT) 484 x->rx_process_stopped_irq++; 485 486 if (v & EMAC_RX_TIMEOUT_INT) 487 ret |= tx_hard_error; 488 489 if (v & EMAC_RX_OVERFLOW_INT) { 490 ret |= tx_hard_error; 491 x->rx_overflow_irq++; 492 } 493 494 if (v & EMAC_RX_EARLY_INT) 495 x->rx_early_irq++; 496 497 if (v & EMAC_RGMII_STA_INT) 498 x->irq_rgmii_n++; 499 500 writel(v, ioaddr + EMAC_INT_STA); 501 502 return ret; 503 } 504 505 static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv, 506 void __iomem *ioaddr, int mode, 507 u32 channel, int fifosz, u8 qmode) 508 { 509 u32 v; 510 511 v = readl(ioaddr + EMAC_RX_CTL1); 512 if (mode == SF_DMA_MODE) { 513 v |= EMAC_RX_MD; 514 } else { 515 v &= ~EMAC_RX_MD; 516 v &= ~EMAC_RX_TH_MASK; 517 if (mode < 32) 518 v |= EMAC_RX_TH_32; 519 else if (mode < 64) 520 v |= EMAC_RX_TH_64; 521 else if (mode < 96) 522 v |= EMAC_RX_TH_96; 523 else if (mode < 128) 524 v |= EMAC_RX_TH_128; 525 } 526 writel(v, ioaddr + EMAC_RX_CTL1); 527 } 528 529 static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv, 530 void __iomem *ioaddr, int mode, 531 u32 channel, int fifosz, u8 qmode) 532 { 533 u32 v; 534 535 v = readl(ioaddr + EMAC_TX_CTL1); 536 if (mode == SF_DMA_MODE) { 537 v |= EMAC_TX_MD; 538 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 539 * comment is 540 * "Operating on second frame increase the performance 541 * especially when transmit store-and-forward is used." 542 */ 543 v |= EMAC_TX_NEXT_FRM; 544 } else { 545 v &= ~EMAC_TX_MD; 546 v &= ~EMAC_TX_TH_MASK; 547 if (mode < 64) 548 v |= EMAC_TX_TH_64; 549 else if (mode < 128) 550 v |= EMAC_TX_TH_128; 551 else if (mode < 192) 552 v |= EMAC_TX_TH_192; 553 else if (mode < 256) 554 v |= EMAC_TX_TH_256; 555 } 556 writel(v, ioaddr + EMAC_TX_CTL1); 557 } 558 559 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 560 .reset = sun8i_dwmac_dma_reset, 561 .init = sun8i_dwmac_dma_init, 562 .init_rx_chan = sun8i_dwmac_dma_init_rx, 563 .init_tx_chan = sun8i_dwmac_dma_init_tx, 564 .dump_regs = sun8i_dwmac_dump_regs, 565 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 566 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 567 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 568 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 569 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 570 .start_tx = sun8i_dwmac_dma_start_tx, 571 .stop_tx = sun8i_dwmac_dma_stop_tx, 572 .start_rx = sun8i_dwmac_dma_start_rx, 573 .stop_rx = sun8i_dwmac_dma_stop_rx, 574 .dma_interrupt = sun8i_dwmac_dma_interrupt, 575 }; 576 577 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); 578 579 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 580 { 581 struct net_device *ndev = platform_get_drvdata(pdev); 582 struct sunxi_priv_data *gmac = priv; 583 int ret; 584 585 if (gmac->regulator) { 586 ret = regulator_enable(gmac->regulator); 587 if (ret) { 588 dev_err(&pdev->dev, "Fail to enable regulator\n"); 589 return ret; 590 } 591 } 592 593 if (gmac->use_internal_phy) { 594 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); 595 if (ret) 596 goto err_disable_regulator; 597 } 598 599 return 0; 600 601 err_disable_regulator: 602 if (gmac->regulator) 603 regulator_disable(gmac->regulator); 604 605 return ret; 606 } 607 608 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 609 struct net_device *dev) 610 { 611 void __iomem *ioaddr = hw->pcsr; 612 u32 v; 613 614 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 615 writel(v, ioaddr + EMAC_BASIC_CTL1); 616 } 617 618 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 619 { 620 u32 t, r; 621 622 t = readl(ioaddr + EMAC_TX_CTL0); 623 r = readl(ioaddr + EMAC_RX_CTL0); 624 if (enable) { 625 t |= EMAC_TX_TRANSMITTER_EN; 626 r |= EMAC_RX_RECEIVER_EN; 627 } else { 628 t &= ~EMAC_TX_TRANSMITTER_EN; 629 r &= ~EMAC_RX_RECEIVER_EN; 630 } 631 writel(t, ioaddr + EMAC_TX_CTL0); 632 writel(r, ioaddr + EMAC_RX_CTL0); 633 } 634 635 /* Set MAC address at slot reg_n 636 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 637 * If addr is NULL, clear the slot 638 */ 639 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 640 const unsigned char *addr, 641 unsigned int reg_n) 642 { 643 void __iomem *ioaddr = hw->pcsr; 644 u32 v; 645 646 if (!addr) { 647 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 648 return; 649 } 650 651 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 652 EMAC_MACADDR_LO(reg_n)); 653 if (reg_n > 0) { 654 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 655 v |= MAC_ADDR_TYPE_DST; 656 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 657 } 658 } 659 660 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 661 unsigned char *addr, 662 unsigned int reg_n) 663 { 664 void __iomem *ioaddr = hw->pcsr; 665 666 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 667 EMAC_MACADDR_LO(reg_n)); 668 } 669 670 /* caution this function must return non 0 to work */ 671 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 672 { 673 void __iomem *ioaddr = hw->pcsr; 674 u32 v; 675 676 v = readl(ioaddr + EMAC_RX_CTL0); 677 v |= EMAC_RX_DO_CRC; 678 writel(v, ioaddr + EMAC_RX_CTL0); 679 680 return 1; 681 } 682 683 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 684 struct net_device *dev) 685 { 686 void __iomem *ioaddr = hw->pcsr; 687 u32 v; 688 int i = 1; 689 struct netdev_hw_addr *ha; 690 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 691 692 v = EMAC_FRM_FLT_CTL; 693 694 if (dev->flags & IFF_PROMISC) { 695 v = EMAC_FRM_FLT_RXALL; 696 } else if (dev->flags & IFF_ALLMULTI) { 697 v |= EMAC_FRM_FLT_MULTICAST; 698 } else if (macaddrs <= hw->unicast_filter_entries) { 699 if (!netdev_mc_empty(dev)) { 700 netdev_for_each_mc_addr(ha, dev) { 701 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 702 i++; 703 } 704 } 705 if (!netdev_uc_empty(dev)) { 706 netdev_for_each_uc_addr(ha, dev) { 707 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 708 i++; 709 } 710 } 711 } else { 712 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 713 netdev_info(dev, "Too many address, switching to promiscuous\n"); 714 v = EMAC_FRM_FLT_RXALL; 715 } 716 717 /* Disable unused address filter slots */ 718 while (i < hw->unicast_filter_entries) 719 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 720 721 writel(v, ioaddr + EMAC_RX_FRM_FLT); 722 } 723 724 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 725 unsigned int duplex, unsigned int fc, 726 unsigned int pause_time, u32 tx_cnt) 727 { 728 void __iomem *ioaddr = hw->pcsr; 729 u32 v; 730 731 v = readl(ioaddr + EMAC_RX_CTL0); 732 if (fc == FLOW_AUTO) 733 v |= EMAC_RX_FLOW_CTL_EN; 734 else 735 v &= ~EMAC_RX_FLOW_CTL_EN; 736 writel(v, ioaddr + EMAC_RX_CTL0); 737 738 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 739 if (fc == FLOW_AUTO) 740 v |= EMAC_TX_FLOW_CTL_EN; 741 else 742 v &= ~EMAC_TX_FLOW_CTL_EN; 743 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 744 } 745 746 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 747 { 748 u32 v; 749 int err; 750 751 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 752 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 753 754 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 755 * need more if no cable plugged. 100ms seems OK 756 */ 757 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 758 !(v & 0x01), 100, 100000); 759 760 if (err) { 761 dev_err(priv->device, "EMAC reset timeout\n"); 762 return err; 763 } 764 return 0; 765 } 766 767 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 768 static int get_ephy_nodes(struct stmmac_priv *priv) 769 { 770 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 771 struct device_node *mdio_mux, *iphynode; 772 struct device_node *mdio_internal; 773 int ret; 774 775 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 776 if (!mdio_mux) { 777 dev_err(priv->device, "Cannot get mdio-mux node\n"); 778 return -ENODEV; 779 } 780 781 mdio_internal = of_get_compatible_child(mdio_mux, 782 "allwinner,sun8i-h3-mdio-internal"); 783 of_node_put(mdio_mux); 784 if (!mdio_internal) { 785 dev_err(priv->device, "Cannot get internal_mdio node\n"); 786 return -ENODEV; 787 } 788 789 /* Seek for internal PHY */ 790 for_each_child_of_node(mdio_internal, iphynode) { 791 gmac->ephy_clk = of_clk_get(iphynode, 0); 792 if (IS_ERR(gmac->ephy_clk)) 793 continue; 794 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 795 if (IS_ERR(gmac->rst_ephy)) { 796 ret = PTR_ERR(gmac->rst_ephy); 797 if (ret == -EPROBE_DEFER) { 798 of_node_put(iphynode); 799 of_node_put(mdio_internal); 800 return ret; 801 } 802 continue; 803 } 804 dev_info(priv->device, "Found internal PHY node\n"); 805 of_node_put(iphynode); 806 of_node_put(mdio_internal); 807 return 0; 808 } 809 810 of_node_put(mdio_internal); 811 return -ENODEV; 812 } 813 814 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 815 { 816 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 817 int ret; 818 819 if (gmac->internal_phy_powered) { 820 dev_warn(priv->device, "Internal PHY already powered\n"); 821 return 0; 822 } 823 824 dev_info(priv->device, "Powering internal PHY\n"); 825 ret = clk_prepare_enable(gmac->ephy_clk); 826 if (ret) { 827 dev_err(priv->device, "Cannot enable internal PHY\n"); 828 return ret; 829 } 830 831 /* Make sure the EPHY is properly reseted, as U-Boot may leave 832 * it at deasserted state, and thus it may fail to reset EMAC. 833 * 834 * This assumes the driver has exclusive access to the EPHY reset. 835 */ 836 ret = reset_control_reset(gmac->rst_ephy); 837 if (ret) { 838 dev_err(priv->device, "Cannot reset internal PHY\n"); 839 clk_disable_unprepare(gmac->ephy_clk); 840 return ret; 841 } 842 843 gmac->internal_phy_powered = true; 844 845 return 0; 846 } 847 848 static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 849 { 850 if (!gmac->internal_phy_powered) 851 return; 852 853 clk_disable_unprepare(gmac->ephy_clk); 854 reset_control_assert(gmac->rst_ephy); 855 gmac->internal_phy_powered = false; 856 } 857 858 /* MDIO multiplexing switch function 859 * This function is called by the mdio-mux layer when it thinks the mdio bus 860 * multiplexer needs to switch. 861 * 'current_child' is the current value of the mux register 862 * 'desired_child' is the value of the 'reg' property of the target child MDIO 863 * node. 864 * The first time this function is called, current_child == -1. 865 * If current_child == desired_child, then the mux is already set to the 866 * correct bus. 867 */ 868 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 869 void *data) 870 { 871 struct stmmac_priv *priv = data; 872 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 873 u32 reg, val; 874 int ret = 0; 875 876 if (current_child ^ desired_child) { 877 regmap_field_read(gmac->regmap_field, ®); 878 switch (desired_child) { 879 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 880 dev_info(priv->device, "Switch mux to internal PHY"); 881 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 882 gmac->use_internal_phy = true; 883 break; 884 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 885 dev_info(priv->device, "Switch mux to external PHY"); 886 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 887 gmac->use_internal_phy = false; 888 break; 889 default: 890 dev_err(priv->device, "Invalid child ID %x\n", 891 desired_child); 892 return -EINVAL; 893 } 894 regmap_field_write(gmac->regmap_field, val); 895 if (gmac->use_internal_phy) { 896 ret = sun8i_dwmac_power_internal_phy(priv); 897 if (ret) 898 return ret; 899 } else { 900 sun8i_dwmac_unpower_internal_phy(gmac); 901 } 902 /* After changing syscon value, the MAC need reset or it will 903 * use the last value (and so the last PHY set). 904 */ 905 ret = sun8i_dwmac_reset(priv); 906 } 907 return ret; 908 } 909 910 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 911 { 912 int ret; 913 struct device_node *mdio_mux; 914 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 915 916 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 917 if (!mdio_mux) 918 return -ENODEV; 919 920 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 921 &gmac->mux_handle, priv, priv->mii); 922 of_node_put(mdio_mux); 923 return ret; 924 } 925 926 static int sun8i_dwmac_set_syscon(struct device *dev, 927 struct plat_stmmacenet_data *plat) 928 { 929 struct sunxi_priv_data *gmac = plat->bsp_priv; 930 struct device_node *node = dev->of_node; 931 int ret; 932 u32 reg, val; 933 934 ret = regmap_field_read(gmac->regmap_field, &val); 935 if (ret) { 936 dev_err(dev, "Fail to read from regmap field.\n"); 937 return ret; 938 } 939 940 reg = gmac->variant->default_syscon_value; 941 if (reg != val) 942 dev_warn(dev, 943 "Current syscon value is not the default %x (expect %x)\n", 944 val, reg); 945 946 if (gmac->variant->soc_has_internal_phy) { 947 if (of_property_read_bool(node, "allwinner,leds-active-low")) 948 reg |= H3_EPHY_LED_POL; 949 else 950 reg &= ~H3_EPHY_LED_POL; 951 952 /* Force EPHY xtal frequency to 24MHz. */ 953 reg |= H3_EPHY_CLK_SEL; 954 955 ret = of_mdio_parse_addr(dev, plat->phy_node); 956 if (ret < 0) { 957 dev_err(dev, "Could not parse MDIO addr\n"); 958 return ret; 959 } 960 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 961 * address. No need to mask it again. 962 */ 963 reg |= 1 << H3_EPHY_ADDR_SHIFT; 964 } else { 965 /* For SoCs without internal PHY the PHY selection bit should be 966 * set to 0 (external PHY). 967 */ 968 reg &= ~H3_EPHY_SELECT; 969 } 970 971 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 972 if (val % 100) { 973 dev_err(dev, "tx-delay must be a multiple of 100\n"); 974 return -EINVAL; 975 } 976 val /= 100; 977 dev_dbg(dev, "set tx-delay to %x\n", val); 978 if (val <= gmac->variant->tx_delay_max) { 979 reg &= ~(gmac->variant->tx_delay_max << 980 SYSCON_ETXDC_SHIFT); 981 reg |= (val << SYSCON_ETXDC_SHIFT); 982 } else { 983 dev_err(dev, "Invalid TX clock delay: %d\n", 984 val); 985 return -EINVAL; 986 } 987 } 988 989 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 990 if (val % 100) { 991 dev_err(dev, "rx-delay must be a multiple of 100\n"); 992 return -EINVAL; 993 } 994 val /= 100; 995 dev_dbg(dev, "set rx-delay to %x\n", val); 996 if (val <= gmac->variant->rx_delay_max) { 997 reg &= ~(gmac->variant->rx_delay_max << 998 SYSCON_ERXDC_SHIFT); 999 reg |= (val << SYSCON_ERXDC_SHIFT); 1000 } else { 1001 dev_err(dev, "Invalid RX clock delay: %d\n", 1002 val); 1003 return -EINVAL; 1004 } 1005 } 1006 1007 /* Clear interface mode bits */ 1008 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 1009 if (gmac->variant->support_rmii) 1010 reg &= ~SYSCON_RMII_EN; 1011 1012 switch (plat->interface) { 1013 case PHY_INTERFACE_MODE_MII: 1014 /* default */ 1015 break; 1016 case PHY_INTERFACE_MODE_RGMII: 1017 case PHY_INTERFACE_MODE_RGMII_ID: 1018 case PHY_INTERFACE_MODE_RGMII_RXID: 1019 case PHY_INTERFACE_MODE_RGMII_TXID: 1020 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 1021 break; 1022 case PHY_INTERFACE_MODE_RMII: 1023 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 1024 break; 1025 default: 1026 dev_err(dev, "Unsupported interface mode: %s", 1027 phy_modes(plat->interface)); 1028 return -EINVAL; 1029 } 1030 1031 regmap_field_write(gmac->regmap_field, reg); 1032 1033 return 0; 1034 } 1035 1036 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 1037 { 1038 u32 reg = gmac->variant->default_syscon_value; 1039 1040 regmap_field_write(gmac->regmap_field, reg); 1041 } 1042 1043 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 1044 { 1045 struct sunxi_priv_data *gmac = priv; 1046 1047 if (gmac->variant->soc_has_internal_phy) 1048 sun8i_dwmac_unpower_internal_phy(gmac); 1049 1050 if (gmac->regulator) 1051 regulator_disable(gmac->regulator); 1052 } 1053 1054 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1055 { 1056 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1057 1058 if (enable) 1059 value |= EMAC_LOOPBACK; 1060 else 1061 value &= ~EMAC_LOOPBACK; 1062 1063 writel(value, ioaddr + EMAC_BASIC_CTL0); 1064 } 1065 1066 static const struct stmmac_ops sun8i_dwmac_ops = { 1067 .core_init = sun8i_dwmac_core_init, 1068 .set_mac = sun8i_dwmac_set_mac, 1069 .dump_regs = sun8i_dwmac_dump_mac_regs, 1070 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1071 .set_filter = sun8i_dwmac_set_filter, 1072 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1073 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1074 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1075 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1076 }; 1077 1078 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1079 { 1080 struct mac_device_info *mac; 1081 struct stmmac_priv *priv = ppriv; 1082 1083 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1084 if (!mac) 1085 return NULL; 1086 1087 mac->pcsr = priv->ioaddr; 1088 mac->mac = &sun8i_dwmac_ops; 1089 mac->dma = &sun8i_dwmac_dma_ops; 1090 1091 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1092 1093 /* The loopback bit seems to be re-set when link change 1094 * Simply mask it each time 1095 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1096 */ 1097 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1098 mac->link.speed10 = EMAC_SPEED_10; 1099 mac->link.speed100 = EMAC_SPEED_100; 1100 mac->link.speed1000 = EMAC_SPEED_1000; 1101 mac->link.duplex = EMAC_DUPLEX_FULL; 1102 mac->mii.addr = EMAC_MDIO_CMD; 1103 mac->mii.data = EMAC_MDIO_DATA; 1104 mac->mii.reg_shift = 4; 1105 mac->mii.reg_mask = GENMASK(8, 4); 1106 mac->mii.addr_shift = 12; 1107 mac->mii.addr_mask = GENMASK(16, 12); 1108 mac->mii.clk_csr_shift = 20; 1109 mac->mii.clk_csr_mask = GENMASK(22, 20); 1110 mac->unicast_filter_entries = 8; 1111 1112 /* Synopsys Id is not available */ 1113 priv->synopsys_id = 0; 1114 1115 return mac; 1116 } 1117 1118 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1119 { 1120 struct device_node *syscon_node; 1121 struct platform_device *syscon_pdev; 1122 struct regmap *regmap = NULL; 1123 1124 syscon_node = of_parse_phandle(node, "syscon", 0); 1125 if (!syscon_node) 1126 return ERR_PTR(-ENODEV); 1127 1128 syscon_pdev = of_find_device_by_node(syscon_node); 1129 if (!syscon_pdev) { 1130 /* platform device might not be probed yet */ 1131 regmap = ERR_PTR(-EPROBE_DEFER); 1132 goto out_put_node; 1133 } 1134 1135 /* If no regmap is found then the other device driver is at fault */ 1136 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1137 if (!regmap) 1138 regmap = ERR_PTR(-EINVAL); 1139 1140 platform_device_put(syscon_pdev); 1141 out_put_node: 1142 of_node_put(syscon_node); 1143 return regmap; 1144 } 1145 1146 static int sun8i_dwmac_probe(struct platform_device *pdev) 1147 { 1148 struct plat_stmmacenet_data *plat_dat; 1149 struct stmmac_resources stmmac_res; 1150 struct sunxi_priv_data *gmac; 1151 struct device *dev = &pdev->dev; 1152 phy_interface_t interface; 1153 int ret; 1154 struct stmmac_priv *priv; 1155 struct net_device *ndev; 1156 struct regmap *regmap; 1157 1158 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1159 if (ret) 1160 return ret; 1161 1162 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1163 if (!gmac) 1164 return -ENOMEM; 1165 1166 gmac->variant = of_device_get_match_data(&pdev->dev); 1167 if (!gmac->variant) { 1168 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1169 return -EINVAL; 1170 } 1171 1172 /* Optional regulator for PHY */ 1173 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1174 if (IS_ERR(gmac->regulator)) { 1175 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1176 return -EPROBE_DEFER; 1177 dev_info(dev, "No regulator found\n"); 1178 gmac->regulator = NULL; 1179 } 1180 1181 /* The "GMAC clock control" register might be located in the 1182 * CCU address range (on the R40), or the system control address 1183 * range (on most other sun8i and later SoCs). 1184 * 1185 * The former controls most if not all clocks in the SoC. The 1186 * latter has an SoC identification register, and on some SoCs, 1187 * controls to map device specific SRAM to either the intended 1188 * peripheral, or the CPU address space. 1189 * 1190 * In either case, there should be a coordinated and restricted 1191 * method of accessing the register needed here. This is done by 1192 * having the device export a custom regmap, instead of a generic 1193 * syscon, which grants all access to all registers. 1194 * 1195 * To support old device trees, we fall back to using the syscon 1196 * interface if possible. 1197 */ 1198 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1199 if (IS_ERR(regmap)) 1200 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1201 "syscon"); 1202 if (IS_ERR(regmap)) { 1203 ret = PTR_ERR(regmap); 1204 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1205 return ret; 1206 } 1207 1208 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1209 *gmac->variant->syscon_field); 1210 if (IS_ERR(gmac->regmap_field)) { 1211 ret = PTR_ERR(gmac->regmap_field); 1212 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1213 return ret; 1214 } 1215 1216 ret = of_get_phy_mode(dev->of_node, &interface); 1217 if (ret) 1218 return -EINVAL; 1219 1220 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 1221 if (IS_ERR(plat_dat)) 1222 return PTR_ERR(plat_dat); 1223 1224 /* platform data specifying hardware features and callbacks. 1225 * hardware features were copied from Allwinner drivers. 1226 */ 1227 plat_dat->interface = interface; 1228 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1229 plat_dat->tx_coe = 1; 1230 plat_dat->has_sun8i = true; 1231 plat_dat->bsp_priv = gmac; 1232 plat_dat->init = sun8i_dwmac_init; 1233 plat_dat->exit = sun8i_dwmac_exit; 1234 plat_dat->setup = sun8i_dwmac_setup; 1235 plat_dat->tx_fifo_size = 4096; 1236 plat_dat->rx_fifo_size = 16384; 1237 1238 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); 1239 if (ret) 1240 goto dwmac_deconfig; 1241 1242 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1243 if (ret) 1244 goto dwmac_syscon; 1245 1246 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1247 if (ret) 1248 goto dwmac_exit; 1249 1250 ndev = dev_get_drvdata(&pdev->dev); 1251 priv = netdev_priv(ndev); 1252 1253 /* the MAC is runtime suspended after stmmac_dvr_probe(), so we 1254 * need to ensure the MAC resume back before other operations such 1255 * as reset. 1256 */ 1257 pm_runtime_get_sync(&pdev->dev); 1258 1259 /* The mux must be registered after parent MDIO 1260 * so after stmmac_dvr_probe() 1261 */ 1262 if (gmac->variant->soc_has_internal_phy) { 1263 ret = get_ephy_nodes(priv); 1264 if (ret) 1265 goto dwmac_remove; 1266 ret = sun8i_dwmac_register_mdio_mux(priv); 1267 if (ret) { 1268 dev_err(&pdev->dev, "Failed to register mux\n"); 1269 goto dwmac_mux; 1270 } 1271 } else { 1272 ret = sun8i_dwmac_reset(priv); 1273 if (ret) 1274 goto dwmac_remove; 1275 } 1276 1277 pm_runtime_put(&pdev->dev); 1278 1279 return 0; 1280 1281 dwmac_mux: 1282 reset_control_put(gmac->rst_ephy); 1283 clk_put(gmac->ephy_clk); 1284 dwmac_remove: 1285 pm_runtime_put_noidle(&pdev->dev); 1286 stmmac_dvr_remove(&pdev->dev); 1287 dwmac_exit: 1288 sun8i_dwmac_exit(pdev, gmac); 1289 dwmac_syscon: 1290 sun8i_dwmac_unset_syscon(gmac); 1291 dwmac_deconfig: 1292 stmmac_remove_config_dt(pdev, plat_dat); 1293 1294 return ret; 1295 } 1296 1297 static void sun8i_dwmac_remove(struct platform_device *pdev) 1298 { 1299 struct net_device *ndev = platform_get_drvdata(pdev); 1300 struct stmmac_priv *priv = netdev_priv(ndev); 1301 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1302 1303 if (gmac->variant->soc_has_internal_phy) { 1304 mdio_mux_uninit(gmac->mux_handle); 1305 sun8i_dwmac_unpower_internal_phy(gmac); 1306 reset_control_put(gmac->rst_ephy); 1307 clk_put(gmac->ephy_clk); 1308 } 1309 1310 stmmac_pltfr_remove(pdev); 1311 sun8i_dwmac_unset_syscon(gmac); 1312 } 1313 1314 static void sun8i_dwmac_shutdown(struct platform_device *pdev) 1315 { 1316 struct net_device *ndev = platform_get_drvdata(pdev); 1317 struct stmmac_priv *priv = netdev_priv(ndev); 1318 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1319 1320 sun8i_dwmac_exit(pdev, gmac); 1321 } 1322 1323 static const struct of_device_id sun8i_dwmac_match[] = { 1324 { .compatible = "allwinner,sun8i-h3-emac", 1325 .data = &emac_variant_h3 }, 1326 { .compatible = "allwinner,sun8i-v3s-emac", 1327 .data = &emac_variant_v3s }, 1328 { .compatible = "allwinner,sun8i-a83t-emac", 1329 .data = &emac_variant_a83t }, 1330 { .compatible = "allwinner,sun8i-r40-gmac", 1331 .data = &emac_variant_r40 }, 1332 { .compatible = "allwinner,sun50i-a64-emac", 1333 .data = &emac_variant_a64 }, 1334 { .compatible = "allwinner,sun50i-h6-emac", 1335 .data = &emac_variant_h6 }, 1336 { } 1337 }; 1338 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1339 1340 static struct platform_driver sun8i_dwmac_driver = { 1341 .probe = sun8i_dwmac_probe, 1342 .remove_new = sun8i_dwmac_remove, 1343 .shutdown = sun8i_dwmac_shutdown, 1344 .driver = { 1345 .name = "dwmac-sun8i", 1346 .pm = &stmmac_pltfr_pm_ops, 1347 .of_match_table = sun8i_dwmac_match, 1348 }, 1349 }; 1350 module_platform_driver(sun8i_dwmac_driver); 1351 1352 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1353 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1354 MODULE_LICENSE("GPL"); 1355