1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
4  *
5  * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/mdio-mux.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_mdio.h>
16 #include <linux/of_net.h>
17 #include <linux/of_platform.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/regmap.h>
23 #include <linux/stmmac.h>
24 
25 #include "stmmac.h"
26 #include "stmmac_platform.h"
27 
28 /* General notes on dwmac-sun8i:
29  * Locking: no locking is necessary in this file because all necessary locking
30  *		is done in the "stmmac files"
31  */
32 
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
34  * @default_syscon_value:	The default value of the EMAC register in syscon
35  *				This value is used for disabling properly EMAC
36  *				and used as a good starting value in case of the
37  *				boot process(uboot) leave some stuff.
38  * @syscon_field		reg_field for the syscon's gmac register
39  * @soc_has_internal_phy:	Does the MAC embed an internal PHY
40  * @support_mii:		Does the MAC handle MII
41  * @support_rmii:		Does the MAC handle RMII
42  * @support_rgmii:		Does the MAC handle RGMII
43  *
44  * @rx_delay_max:		Maximum raw value for RX delay chain
45  * @tx_delay_max:		Maximum raw value for TX delay chain
46  *				These two also indicate the bitmask for
47  *				the RX and TX delay chain registers. A
48  *				value of zero indicates this is not supported.
49  */
50 struct emac_variant {
51 	u32 default_syscon_value;
52 	const struct reg_field *syscon_field;
53 	bool soc_has_internal_phy;
54 	bool support_mii;
55 	bool support_rmii;
56 	bool support_rgmii;
57 	u8 rx_delay_max;
58 	u8 tx_delay_max;
59 };
60 
61 /* struct sunxi_priv_data - hold all sunxi private data
62  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
63  * @regulator:	reference to the optional regulator
64  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
65  * @variant:	reference to the current board variant
66  * @regmap:	regmap for using the syscon
67  * @internal_phy_powered: Does the internal PHY is enabled
68  * @use_internal_phy: Is the internal PHY selected for use
69  * @mux_handle:	Internal pointer used by mdio-mux lib
70  */
71 struct sunxi_priv_data {
72 	struct clk *ephy_clk;
73 	struct regulator *regulator;
74 	struct reset_control *rst_ephy;
75 	const struct emac_variant *variant;
76 	struct regmap_field *regmap_field;
77 	bool internal_phy_powered;
78 	bool use_internal_phy;
79 	void *mux_handle;
80 };
81 
82 /* EMAC clock register @ 0x30 in the "system control" address range */
83 static const struct reg_field sun8i_syscon_reg_field = {
84 	.reg = 0x30,
85 	.lsb = 0,
86 	.msb = 31,
87 };
88 
89 /* EMAC clock register @ 0x164 in the CCU address range */
90 static const struct reg_field sun8i_ccu_reg_field = {
91 	.reg = 0x164,
92 	.lsb = 0,
93 	.msb = 31,
94 };
95 
96 static const struct emac_variant emac_variant_h3 = {
97 	.default_syscon_value = 0x58000,
98 	.syscon_field = &sun8i_syscon_reg_field,
99 	.soc_has_internal_phy = true,
100 	.support_mii = true,
101 	.support_rmii = true,
102 	.support_rgmii = true,
103 	.rx_delay_max = 31,
104 	.tx_delay_max = 7,
105 };
106 
107 static const struct emac_variant emac_variant_v3s = {
108 	.default_syscon_value = 0x38000,
109 	.syscon_field = &sun8i_syscon_reg_field,
110 	.soc_has_internal_phy = true,
111 	.support_mii = true
112 };
113 
114 static const struct emac_variant emac_variant_a83t = {
115 	.default_syscon_value = 0,
116 	.syscon_field = &sun8i_syscon_reg_field,
117 	.soc_has_internal_phy = false,
118 	.support_mii = true,
119 	.support_rgmii = true,
120 	.rx_delay_max = 31,
121 	.tx_delay_max = 7,
122 };
123 
124 static const struct emac_variant emac_variant_r40 = {
125 	.default_syscon_value = 0,
126 	.syscon_field = &sun8i_ccu_reg_field,
127 	.support_mii = true,
128 	.support_rgmii = true,
129 	.rx_delay_max = 7,
130 };
131 
132 static const struct emac_variant emac_variant_a64 = {
133 	.default_syscon_value = 0,
134 	.syscon_field = &sun8i_syscon_reg_field,
135 	.soc_has_internal_phy = false,
136 	.support_mii = true,
137 	.support_rmii = true,
138 	.support_rgmii = true,
139 	.rx_delay_max = 31,
140 	.tx_delay_max = 7,
141 };
142 
143 static const struct emac_variant emac_variant_h6 = {
144 	.default_syscon_value = 0x50000,
145 	.syscon_field = &sun8i_syscon_reg_field,
146 	/* The "Internal PHY" of H6 is not on the die. It's on the
147 	 * co-packaged AC200 chip instead.
148 	 */
149 	.soc_has_internal_phy = false,
150 	.support_mii = true,
151 	.support_rmii = true,
152 	.support_rgmii = true,
153 	.rx_delay_max = 31,
154 	.tx_delay_max = 7,
155 };
156 
157 #define EMAC_BASIC_CTL0 0x00
158 #define EMAC_BASIC_CTL1 0x04
159 #define EMAC_INT_STA    0x08
160 #define EMAC_INT_EN     0x0C
161 #define EMAC_TX_CTL0    0x10
162 #define EMAC_TX_CTL1    0x14
163 #define EMAC_TX_FLOW_CTL        0x1C
164 #define EMAC_TX_DESC_LIST 0x20
165 #define EMAC_RX_CTL0    0x24
166 #define EMAC_RX_CTL1    0x28
167 #define EMAC_RX_DESC_LIST 0x34
168 #define EMAC_RX_FRM_FLT 0x38
169 #define EMAC_MDIO_CMD   0x48
170 #define EMAC_MDIO_DATA  0x4C
171 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
172 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
173 #define EMAC_TX_DMA_STA 0xB0
174 #define EMAC_TX_CUR_DESC        0xB4
175 #define EMAC_TX_CUR_BUF 0xB8
176 #define EMAC_RX_DMA_STA 0xC0
177 #define EMAC_RX_CUR_DESC        0xC4
178 #define EMAC_RX_CUR_BUF 0xC8
179 
180 /* Use in EMAC_BASIC_CTL0 */
181 #define EMAC_DUPLEX_FULL	BIT(0)
182 #define EMAC_LOOPBACK		BIT(1)
183 #define EMAC_SPEED_1000 0
184 #define EMAC_SPEED_100 (0x03 << 2)
185 #define EMAC_SPEED_10 (0x02 << 2)
186 
187 /* Use in EMAC_BASIC_CTL1 */
188 #define EMAC_BURSTLEN_SHIFT		24
189 
190 /* Used in EMAC_RX_FRM_FLT */
191 #define EMAC_FRM_FLT_RXALL              BIT(0)
192 #define EMAC_FRM_FLT_CTL                BIT(13)
193 #define EMAC_FRM_FLT_MULTICAST          BIT(16)
194 
195 /* Used in RX_CTL1*/
196 #define EMAC_RX_MD              BIT(1)
197 #define EMAC_RX_TH_MASK		GENMASK(5, 4)
198 #define EMAC_RX_TH_32		0
199 #define EMAC_RX_TH_64		(0x1 << 4)
200 #define EMAC_RX_TH_96		(0x2 << 4)
201 #define EMAC_RX_TH_128		(0x3 << 4)
202 #define EMAC_RX_DMA_EN  BIT(30)
203 #define EMAC_RX_DMA_START       BIT(31)
204 
205 /* Used in TX_CTL1*/
206 #define EMAC_TX_MD              BIT(1)
207 #define EMAC_TX_NEXT_FRM        BIT(2)
208 #define EMAC_TX_TH_MASK		GENMASK(10, 8)
209 #define EMAC_TX_TH_64		0
210 #define EMAC_TX_TH_128		(0x1 << 8)
211 #define EMAC_TX_TH_192		(0x2 << 8)
212 #define EMAC_TX_TH_256		(0x3 << 8)
213 #define EMAC_TX_DMA_EN  BIT(30)
214 #define EMAC_TX_DMA_START       BIT(31)
215 
216 /* Used in RX_CTL0 */
217 #define EMAC_RX_RECEIVER_EN             BIT(31)
218 #define EMAC_RX_DO_CRC BIT(27)
219 #define EMAC_RX_FLOW_CTL_EN             BIT(16)
220 
221 /* Used in TX_CTL0 */
222 #define EMAC_TX_TRANSMITTER_EN  BIT(31)
223 
224 /* Used in EMAC_TX_FLOW_CTL */
225 #define EMAC_TX_FLOW_CTL_EN             BIT(0)
226 
227 /* Used in EMAC_INT_STA */
228 #define EMAC_TX_INT             BIT(0)
229 #define EMAC_TX_DMA_STOP_INT    BIT(1)
230 #define EMAC_TX_BUF_UA_INT      BIT(2)
231 #define EMAC_TX_TIMEOUT_INT     BIT(3)
232 #define EMAC_TX_UNDERFLOW_INT   BIT(4)
233 #define EMAC_TX_EARLY_INT       BIT(5)
234 #define EMAC_RX_INT             BIT(8)
235 #define EMAC_RX_BUF_UA_INT      BIT(9)
236 #define EMAC_RX_DMA_STOP_INT    BIT(10)
237 #define EMAC_RX_TIMEOUT_INT     BIT(11)
238 #define EMAC_RX_OVERFLOW_INT    BIT(12)
239 #define EMAC_RX_EARLY_INT       BIT(13)
240 #define EMAC_RGMII_STA_INT      BIT(16)
241 
242 #define EMAC_INT_MSK_COMMON	EMAC_RGMII_STA_INT
243 #define EMAC_INT_MSK_TX		(EMAC_TX_INT | \
244 				 EMAC_TX_DMA_STOP_INT | \
245 				 EMAC_TX_BUF_UA_INT | \
246 				 EMAC_TX_TIMEOUT_INT | \
247 				 EMAC_TX_UNDERFLOW_INT | \
248 				 EMAC_TX_EARLY_INT |\
249 				 EMAC_INT_MSK_COMMON)
250 #define EMAC_INT_MSK_RX		(EMAC_RX_INT | \
251 				 EMAC_RX_BUF_UA_INT | \
252 				 EMAC_RX_DMA_STOP_INT | \
253 				 EMAC_RX_TIMEOUT_INT | \
254 				 EMAC_RX_OVERFLOW_INT | \
255 				 EMAC_RX_EARLY_INT | \
256 				 EMAC_INT_MSK_COMMON)
257 
258 #define MAC_ADDR_TYPE_DST BIT(31)
259 
260 /* H3 specific bits for EPHY */
261 #define H3_EPHY_ADDR_SHIFT	20
262 #define H3_EPHY_CLK_SEL		BIT(18) /* 1: 24MHz, 0: 25MHz */
263 #define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
264 #define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
265 #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
266 #define H3_EPHY_MUX_MASK	(H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
267 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID	1
268 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID	2
269 
270 /* H3/A64 specific bits */
271 #define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
272 
273 /* Generic system control EMAC_CLK bits */
274 #define SYSCON_ETXDC_SHIFT		10
275 #define SYSCON_ERXDC_SHIFT		5
276 /* EMAC PHY Interface Type */
277 #define SYSCON_EPIT			BIT(2) /* 1: RGMII, 0: MII */
278 #define SYSCON_ETCS_MASK		GENMASK(1, 0)
279 #define SYSCON_ETCS_MII		0x0
280 #define SYSCON_ETCS_EXT_GMII	0x1
281 #define SYSCON_ETCS_INT_GMII	0x2
282 
283 /* sun8i_dwmac_dma_reset() - reset the EMAC
284  * Called from stmmac via stmmac_dma_ops->reset
285  */
286 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
287 {
288 	writel(0, ioaddr + EMAC_RX_CTL1);
289 	writel(0, ioaddr + EMAC_TX_CTL1);
290 	writel(0, ioaddr + EMAC_RX_FRM_FLT);
291 	writel(0, ioaddr + EMAC_RX_DESC_LIST);
292 	writel(0, ioaddr + EMAC_TX_DESC_LIST);
293 	writel(0, ioaddr + EMAC_INT_EN);
294 	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
295 	return 0;
296 }
297 
298 /* sun8i_dwmac_dma_init() - initialize the EMAC
299  * Called from stmmac via stmmac_dma_ops->init
300  */
301 static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
302 				 struct stmmac_dma_cfg *dma_cfg, int atds)
303 {
304 	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
305 	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
306 }
307 
308 static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv,
309 				    void __iomem *ioaddr,
310 				    struct stmmac_dma_cfg *dma_cfg,
311 				    dma_addr_t dma_rx_phy, u32 chan)
312 {
313 	/* Write RX descriptors address */
314 	writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
315 }
316 
317 static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv,
318 				    void __iomem *ioaddr,
319 				    struct stmmac_dma_cfg *dma_cfg,
320 				    dma_addr_t dma_tx_phy, u32 chan)
321 {
322 	/* Write TX descriptors address */
323 	writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
324 }
325 
326 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
327  * Called from stmmac_dma_ops->dump_regs
328  * Used for ethtool
329  */
330 static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv,
331 				  void __iomem *ioaddr, u32 *reg_space)
332 {
333 	int i;
334 
335 	for (i = 0; i < 0xC8; i += 4) {
336 		if (i == 0x32 || i == 0x3C)
337 			continue;
338 		reg_space[i / 4] = readl(ioaddr + i);
339 	}
340 }
341 
342 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
343  * Called from stmmac_ops->dump_regs
344  * Used for ethtool
345  */
346 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
347 				      u32 *reg_space)
348 {
349 	int i;
350 	void __iomem *ioaddr = hw->pcsr;
351 
352 	for (i = 0; i < 0xC8; i += 4) {
353 		if (i == 0x32 || i == 0x3C)
354 			continue;
355 		reg_space[i / 4] = readl(ioaddr + i);
356 	}
357 }
358 
359 static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv,
360 				       void __iomem *ioaddr, u32 chan,
361 				       bool rx, bool tx)
362 {
363 	u32 value = readl(ioaddr + EMAC_INT_EN);
364 
365 	if (rx)
366 		value |= EMAC_RX_INT;
367 	if (tx)
368 		value |= EMAC_TX_INT;
369 
370 	writel(value, ioaddr + EMAC_INT_EN);
371 }
372 
373 static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv,
374 					void __iomem *ioaddr, u32 chan,
375 					bool rx, bool tx)
376 {
377 	u32 value = readl(ioaddr + EMAC_INT_EN);
378 
379 	if (rx)
380 		value &= ~EMAC_RX_INT;
381 	if (tx)
382 		value &= ~EMAC_TX_INT;
383 
384 	writel(value, ioaddr + EMAC_INT_EN);
385 }
386 
387 static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
388 				     void __iomem *ioaddr, u32 chan)
389 {
390 	u32 v;
391 
392 	v = readl(ioaddr + EMAC_TX_CTL1);
393 	v |= EMAC_TX_DMA_START;
394 	v |= EMAC_TX_DMA_EN;
395 	writel(v, ioaddr + EMAC_TX_CTL1);
396 }
397 
398 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
399 {
400 	u32 v;
401 
402 	v = readl(ioaddr + EMAC_TX_CTL1);
403 	v |= EMAC_TX_DMA_START;
404 	v |= EMAC_TX_DMA_EN;
405 	writel(v, ioaddr + EMAC_TX_CTL1);
406 }
407 
408 static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv,
409 				    void __iomem *ioaddr, u32 chan)
410 {
411 	u32 v;
412 
413 	v = readl(ioaddr + EMAC_TX_CTL1);
414 	v &= ~EMAC_TX_DMA_EN;
415 	writel(v, ioaddr + EMAC_TX_CTL1);
416 }
417 
418 static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv,
419 				     void __iomem *ioaddr, u32 chan)
420 {
421 	u32 v;
422 
423 	v = readl(ioaddr + EMAC_RX_CTL1);
424 	v |= EMAC_RX_DMA_START;
425 	v |= EMAC_RX_DMA_EN;
426 	writel(v, ioaddr + EMAC_RX_CTL1);
427 }
428 
429 static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv,
430 				    void __iomem *ioaddr, u32 chan)
431 {
432 	u32 v;
433 
434 	v = readl(ioaddr + EMAC_RX_CTL1);
435 	v &= ~EMAC_RX_DMA_EN;
436 	writel(v, ioaddr + EMAC_RX_CTL1);
437 }
438 
439 static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv,
440 				     void __iomem *ioaddr,
441 				     struct stmmac_extra_stats *x, u32 chan,
442 				     u32 dir)
443 {
444 	struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats);
445 	int ret = 0;
446 	u32 v;
447 
448 	v = readl(ioaddr + EMAC_INT_STA);
449 
450 	if (dir == DMA_DIR_RX)
451 		v &= EMAC_INT_MSK_RX;
452 	else if (dir == DMA_DIR_TX)
453 		v &= EMAC_INT_MSK_TX;
454 
455 	if (v & EMAC_TX_INT) {
456 		ret |= handle_tx;
457 		u64_stats_update_begin(&stats->syncp);
458 		u64_stats_inc(&stats->tx_normal_irq_n[chan]);
459 		u64_stats_update_end(&stats->syncp);
460 	}
461 
462 	if (v & EMAC_TX_DMA_STOP_INT)
463 		x->tx_process_stopped_irq++;
464 
465 	if (v & EMAC_TX_BUF_UA_INT)
466 		x->tx_process_stopped_irq++;
467 
468 	if (v & EMAC_TX_TIMEOUT_INT)
469 		ret |= tx_hard_error;
470 
471 	if (v & EMAC_TX_UNDERFLOW_INT) {
472 		ret |= tx_hard_error;
473 		x->tx_undeflow_irq++;
474 	}
475 
476 	if (v & EMAC_TX_EARLY_INT)
477 		x->tx_early_irq++;
478 
479 	if (v & EMAC_RX_INT) {
480 		ret |= handle_rx;
481 		u64_stats_update_begin(&stats->syncp);
482 		u64_stats_inc(&stats->rx_normal_irq_n[chan]);
483 		u64_stats_update_end(&stats->syncp);
484 	}
485 
486 	if (v & EMAC_RX_BUF_UA_INT)
487 		x->rx_buf_unav_irq++;
488 
489 	if (v & EMAC_RX_DMA_STOP_INT)
490 		x->rx_process_stopped_irq++;
491 
492 	if (v & EMAC_RX_TIMEOUT_INT)
493 		ret |= tx_hard_error;
494 
495 	if (v & EMAC_RX_OVERFLOW_INT) {
496 		ret |= tx_hard_error;
497 		x->rx_overflow_irq++;
498 	}
499 
500 	if (v & EMAC_RX_EARLY_INT)
501 		x->rx_early_irq++;
502 
503 	if (v & EMAC_RGMII_STA_INT)
504 		x->irq_rgmii_n++;
505 
506 	writel(v, ioaddr + EMAC_INT_STA);
507 
508 	return ret;
509 }
510 
511 static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv,
512 					      void __iomem *ioaddr, int mode,
513 					      u32 channel, int fifosz, u8 qmode)
514 {
515 	u32 v;
516 
517 	v = readl(ioaddr + EMAC_RX_CTL1);
518 	if (mode == SF_DMA_MODE) {
519 		v |= EMAC_RX_MD;
520 	} else {
521 		v &= ~EMAC_RX_MD;
522 		v &= ~EMAC_RX_TH_MASK;
523 		if (mode < 32)
524 			v |= EMAC_RX_TH_32;
525 		else if (mode < 64)
526 			v |= EMAC_RX_TH_64;
527 		else if (mode < 96)
528 			v |= EMAC_RX_TH_96;
529 		else if (mode < 128)
530 			v |= EMAC_RX_TH_128;
531 	}
532 	writel(v, ioaddr + EMAC_RX_CTL1);
533 }
534 
535 static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv,
536 					      void __iomem *ioaddr, int mode,
537 					      u32 channel, int fifosz, u8 qmode)
538 {
539 	u32 v;
540 
541 	v = readl(ioaddr + EMAC_TX_CTL1);
542 	if (mode == SF_DMA_MODE) {
543 		v |= EMAC_TX_MD;
544 		/* Undocumented bit (called TX_NEXT_FRM in BSP), the original
545 		 * comment is
546 		 * "Operating on second frame increase the performance
547 		 * especially when transmit store-and-forward is used."
548 		 */
549 		v |= EMAC_TX_NEXT_FRM;
550 	} else {
551 		v &= ~EMAC_TX_MD;
552 		v &= ~EMAC_TX_TH_MASK;
553 		if (mode < 64)
554 			v |= EMAC_TX_TH_64;
555 		else if (mode < 128)
556 			v |= EMAC_TX_TH_128;
557 		else if (mode < 192)
558 			v |= EMAC_TX_TH_192;
559 		else if (mode < 256)
560 			v |= EMAC_TX_TH_256;
561 	}
562 	writel(v, ioaddr + EMAC_TX_CTL1);
563 }
564 
565 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
566 	.reset = sun8i_dwmac_dma_reset,
567 	.init = sun8i_dwmac_dma_init,
568 	.init_rx_chan = sun8i_dwmac_dma_init_rx,
569 	.init_tx_chan = sun8i_dwmac_dma_init_tx,
570 	.dump_regs = sun8i_dwmac_dump_regs,
571 	.dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,
572 	.dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,
573 	.enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
574 	.enable_dma_irq = sun8i_dwmac_enable_dma_irq,
575 	.disable_dma_irq = sun8i_dwmac_disable_dma_irq,
576 	.start_tx = sun8i_dwmac_dma_start_tx,
577 	.stop_tx = sun8i_dwmac_dma_stop_tx,
578 	.start_rx = sun8i_dwmac_dma_start_rx,
579 	.stop_rx = sun8i_dwmac_dma_stop_rx,
580 	.dma_interrupt = sun8i_dwmac_dma_interrupt,
581 };
582 
583 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv);
584 
585 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
586 {
587 	struct net_device *ndev = platform_get_drvdata(pdev);
588 	struct sunxi_priv_data *gmac = priv;
589 	int ret;
590 
591 	if (gmac->regulator) {
592 		ret = regulator_enable(gmac->regulator);
593 		if (ret) {
594 			dev_err(&pdev->dev, "Fail to enable regulator\n");
595 			return ret;
596 		}
597 	}
598 
599 	if (gmac->use_internal_phy) {
600 		ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev));
601 		if (ret)
602 			goto err_disable_regulator;
603 	}
604 
605 	return 0;
606 
607 err_disable_regulator:
608 	if (gmac->regulator)
609 		regulator_disable(gmac->regulator);
610 
611 	return ret;
612 }
613 
614 static void sun8i_dwmac_core_init(struct mac_device_info *hw,
615 				  struct net_device *dev)
616 {
617 	void __iomem *ioaddr = hw->pcsr;
618 	u32 v;
619 
620 	v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
621 	writel(v, ioaddr + EMAC_BASIC_CTL1);
622 }
623 
624 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
625 {
626 	u32 t, r;
627 
628 	t = readl(ioaddr + EMAC_TX_CTL0);
629 	r = readl(ioaddr + EMAC_RX_CTL0);
630 	if (enable) {
631 		t |= EMAC_TX_TRANSMITTER_EN;
632 		r |= EMAC_RX_RECEIVER_EN;
633 	} else {
634 		t &= ~EMAC_TX_TRANSMITTER_EN;
635 		r &= ~EMAC_RX_RECEIVER_EN;
636 	}
637 	writel(t, ioaddr + EMAC_TX_CTL0);
638 	writel(r, ioaddr + EMAC_RX_CTL0);
639 }
640 
641 /* Set MAC address at slot reg_n
642  * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
643  * If addr is NULL, clear the slot
644  */
645 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
646 				      const unsigned char *addr,
647 				      unsigned int reg_n)
648 {
649 	void __iomem *ioaddr = hw->pcsr;
650 	u32 v;
651 
652 	if (!addr) {
653 		writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
654 		return;
655 	}
656 
657 	stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
658 			    EMAC_MACADDR_LO(reg_n));
659 	if (reg_n > 0) {
660 		v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
661 		v |= MAC_ADDR_TYPE_DST;
662 		writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
663 	}
664 }
665 
666 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
667 				      unsigned char *addr,
668 				      unsigned int reg_n)
669 {
670 	void __iomem *ioaddr = hw->pcsr;
671 
672 	stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
673 			    EMAC_MACADDR_LO(reg_n));
674 }
675 
676 /* caution this function must return non 0 to work */
677 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
678 {
679 	void __iomem *ioaddr = hw->pcsr;
680 	u32 v;
681 
682 	v = readl(ioaddr + EMAC_RX_CTL0);
683 	v |= EMAC_RX_DO_CRC;
684 	writel(v, ioaddr + EMAC_RX_CTL0);
685 
686 	return 1;
687 }
688 
689 static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
690 				   struct net_device *dev)
691 {
692 	void __iomem *ioaddr = hw->pcsr;
693 	u32 v;
694 	int i = 1;
695 	struct netdev_hw_addr *ha;
696 	int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
697 
698 	v = EMAC_FRM_FLT_CTL;
699 
700 	if (dev->flags & IFF_PROMISC) {
701 		v = EMAC_FRM_FLT_RXALL;
702 	} else if (dev->flags & IFF_ALLMULTI) {
703 		v |= EMAC_FRM_FLT_MULTICAST;
704 	} else if (macaddrs <= hw->unicast_filter_entries) {
705 		if (!netdev_mc_empty(dev)) {
706 			netdev_for_each_mc_addr(ha, dev) {
707 				sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
708 				i++;
709 			}
710 		}
711 		if (!netdev_uc_empty(dev)) {
712 			netdev_for_each_uc_addr(ha, dev) {
713 				sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
714 				i++;
715 			}
716 		}
717 	} else {
718 		if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL))
719 			netdev_info(dev, "Too many address, switching to promiscuous\n");
720 		v = EMAC_FRM_FLT_RXALL;
721 	}
722 
723 	/* Disable unused address filter slots */
724 	while (i < hw->unicast_filter_entries)
725 		sun8i_dwmac_set_umac_addr(hw, NULL, i++);
726 
727 	writel(v, ioaddr + EMAC_RX_FRM_FLT);
728 }
729 
730 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
731 				  unsigned int duplex, unsigned int fc,
732 				  unsigned int pause_time, u32 tx_cnt)
733 {
734 	void __iomem *ioaddr = hw->pcsr;
735 	u32 v;
736 
737 	v = readl(ioaddr + EMAC_RX_CTL0);
738 	if (fc == FLOW_AUTO)
739 		v |= EMAC_RX_FLOW_CTL_EN;
740 	else
741 		v &= ~EMAC_RX_FLOW_CTL_EN;
742 	writel(v, ioaddr + EMAC_RX_CTL0);
743 
744 	v = readl(ioaddr + EMAC_TX_FLOW_CTL);
745 	if (fc == FLOW_AUTO)
746 		v |= EMAC_TX_FLOW_CTL_EN;
747 	else
748 		v &= ~EMAC_TX_FLOW_CTL_EN;
749 	writel(v, ioaddr + EMAC_TX_FLOW_CTL);
750 }
751 
752 static int sun8i_dwmac_reset(struct stmmac_priv *priv)
753 {
754 	u32 v;
755 	int err;
756 
757 	v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
758 	writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
759 
760 	/* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
761 	 * need more if no cable plugged. 100ms seems OK
762 	 */
763 	err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
764 				 !(v & 0x01), 100, 100000);
765 
766 	if (err) {
767 		dev_err(priv->device, "EMAC reset timeout\n");
768 		return err;
769 	}
770 	return 0;
771 }
772 
773 /* Search in mdio-mux node for internal PHY node and get its clk/reset */
774 static int get_ephy_nodes(struct stmmac_priv *priv)
775 {
776 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
777 	struct device_node *mdio_mux, *iphynode;
778 	struct device_node *mdio_internal;
779 	int ret;
780 
781 	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
782 	if (!mdio_mux) {
783 		dev_err(priv->device, "Cannot get mdio-mux node\n");
784 		return -ENODEV;
785 	}
786 
787 	mdio_internal = of_get_compatible_child(mdio_mux,
788 						"allwinner,sun8i-h3-mdio-internal");
789 	of_node_put(mdio_mux);
790 	if (!mdio_internal) {
791 		dev_err(priv->device, "Cannot get internal_mdio node\n");
792 		return -ENODEV;
793 	}
794 
795 	/* Seek for internal PHY */
796 	for_each_child_of_node(mdio_internal, iphynode) {
797 		gmac->ephy_clk = of_clk_get(iphynode, 0);
798 		if (IS_ERR(gmac->ephy_clk))
799 			continue;
800 		gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
801 		if (IS_ERR(gmac->rst_ephy)) {
802 			ret = PTR_ERR(gmac->rst_ephy);
803 			if (ret == -EPROBE_DEFER) {
804 				of_node_put(iphynode);
805 				of_node_put(mdio_internal);
806 				return ret;
807 			}
808 			continue;
809 		}
810 		dev_info(priv->device, "Found internal PHY node\n");
811 		of_node_put(iphynode);
812 		of_node_put(mdio_internal);
813 		return 0;
814 	}
815 
816 	of_node_put(mdio_internal);
817 	return -ENODEV;
818 }
819 
820 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
821 {
822 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
823 	int ret;
824 
825 	if (gmac->internal_phy_powered) {
826 		dev_warn(priv->device, "Internal PHY already powered\n");
827 		return 0;
828 	}
829 
830 	dev_info(priv->device, "Powering internal PHY\n");
831 	ret = clk_prepare_enable(gmac->ephy_clk);
832 	if (ret) {
833 		dev_err(priv->device, "Cannot enable internal PHY\n");
834 		return ret;
835 	}
836 
837 	/* Make sure the EPHY is properly reseted, as U-Boot may leave
838 	 * it at deasserted state, and thus it may fail to reset EMAC.
839 	 *
840 	 * This assumes the driver has exclusive access to the EPHY reset.
841 	 */
842 	ret = reset_control_reset(gmac->rst_ephy);
843 	if (ret) {
844 		dev_err(priv->device, "Cannot reset internal PHY\n");
845 		clk_disable_unprepare(gmac->ephy_clk);
846 		return ret;
847 	}
848 
849 	gmac->internal_phy_powered = true;
850 
851 	return 0;
852 }
853 
854 static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
855 {
856 	if (!gmac->internal_phy_powered)
857 		return;
858 
859 	clk_disable_unprepare(gmac->ephy_clk);
860 	reset_control_assert(gmac->rst_ephy);
861 	gmac->internal_phy_powered = false;
862 }
863 
864 /* MDIO multiplexing switch function
865  * This function is called by the mdio-mux layer when it thinks the mdio bus
866  * multiplexer needs to switch.
867  * 'current_child' is the current value of the mux register
868  * 'desired_child' is the value of the 'reg' property of the target child MDIO
869  * node.
870  * The first time this function is called, current_child == -1.
871  * If current_child == desired_child, then the mux is already set to the
872  * correct bus.
873  */
874 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
875 				     void *data)
876 {
877 	struct stmmac_priv *priv = data;
878 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
879 	u32 reg, val;
880 	int ret = 0;
881 
882 	if (current_child ^ desired_child) {
883 		regmap_field_read(gmac->regmap_field, &reg);
884 		switch (desired_child) {
885 		case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
886 			dev_info(priv->device, "Switch mux to internal PHY");
887 			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
888 			gmac->use_internal_phy = true;
889 			break;
890 		case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
891 			dev_info(priv->device, "Switch mux to external PHY");
892 			val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
893 			gmac->use_internal_phy = false;
894 			break;
895 		default:
896 			dev_err(priv->device, "Invalid child ID %x\n",
897 				desired_child);
898 			return -EINVAL;
899 		}
900 		regmap_field_write(gmac->regmap_field, val);
901 		if (gmac->use_internal_phy) {
902 			ret = sun8i_dwmac_power_internal_phy(priv);
903 			if (ret)
904 				return ret;
905 		} else {
906 			sun8i_dwmac_unpower_internal_phy(gmac);
907 		}
908 		/* After changing syscon value, the MAC need reset or it will
909 		 * use the last value (and so the last PHY set).
910 		 */
911 		ret = sun8i_dwmac_reset(priv);
912 	}
913 	return ret;
914 }
915 
916 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
917 {
918 	int ret;
919 	struct device_node *mdio_mux;
920 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
921 
922 	mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
923 	if (!mdio_mux)
924 		return -ENODEV;
925 
926 	ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
927 			    &gmac->mux_handle, priv, priv->mii);
928 	of_node_put(mdio_mux);
929 	return ret;
930 }
931 
932 static int sun8i_dwmac_set_syscon(struct device *dev,
933 				  struct plat_stmmacenet_data *plat)
934 {
935 	struct sunxi_priv_data *gmac = plat->bsp_priv;
936 	struct device_node *node = dev->of_node;
937 	int ret;
938 	u32 reg, val;
939 
940 	ret = regmap_field_read(gmac->regmap_field, &val);
941 	if (ret) {
942 		dev_err(dev, "Fail to read from regmap field.\n");
943 		return ret;
944 	}
945 
946 	reg = gmac->variant->default_syscon_value;
947 	if (reg != val)
948 		dev_warn(dev,
949 			 "Current syscon value is not the default %x (expect %x)\n",
950 			 val, reg);
951 
952 	if (gmac->variant->soc_has_internal_phy) {
953 		if (of_property_read_bool(node, "allwinner,leds-active-low"))
954 			reg |= H3_EPHY_LED_POL;
955 		else
956 			reg &= ~H3_EPHY_LED_POL;
957 
958 		/* Force EPHY xtal frequency to 24MHz. */
959 		reg |= H3_EPHY_CLK_SEL;
960 
961 		ret = of_mdio_parse_addr(dev, plat->phy_node);
962 		if (ret < 0) {
963 			dev_err(dev, "Could not parse MDIO addr\n");
964 			return ret;
965 		}
966 		/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
967 		 * address. No need to mask it again.
968 		 */
969 		reg |= 1 << H3_EPHY_ADDR_SHIFT;
970 	} else {
971 		/* For SoCs without internal PHY the PHY selection bit should be
972 		 * set to 0 (external PHY).
973 		 */
974 		reg &= ~H3_EPHY_SELECT;
975 	}
976 
977 	if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
978 		if (val % 100) {
979 			dev_err(dev, "tx-delay must be a multiple of 100\n");
980 			return -EINVAL;
981 		}
982 		val /= 100;
983 		dev_dbg(dev, "set tx-delay to %x\n", val);
984 		if (val <= gmac->variant->tx_delay_max) {
985 			reg &= ~(gmac->variant->tx_delay_max <<
986 				 SYSCON_ETXDC_SHIFT);
987 			reg |= (val << SYSCON_ETXDC_SHIFT);
988 		} else {
989 			dev_err(dev, "Invalid TX clock delay: %d\n",
990 				val);
991 			return -EINVAL;
992 		}
993 	}
994 
995 	if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
996 		if (val % 100) {
997 			dev_err(dev, "rx-delay must be a multiple of 100\n");
998 			return -EINVAL;
999 		}
1000 		val /= 100;
1001 		dev_dbg(dev, "set rx-delay to %x\n", val);
1002 		if (val <= gmac->variant->rx_delay_max) {
1003 			reg &= ~(gmac->variant->rx_delay_max <<
1004 				 SYSCON_ERXDC_SHIFT);
1005 			reg |= (val << SYSCON_ERXDC_SHIFT);
1006 		} else {
1007 			dev_err(dev, "Invalid RX clock delay: %d\n",
1008 				val);
1009 			return -EINVAL;
1010 		}
1011 	}
1012 
1013 	/* Clear interface mode bits */
1014 	reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
1015 	if (gmac->variant->support_rmii)
1016 		reg &= ~SYSCON_RMII_EN;
1017 
1018 	switch (plat->mac_interface) {
1019 	case PHY_INTERFACE_MODE_MII:
1020 		/* default */
1021 		break;
1022 	case PHY_INTERFACE_MODE_RGMII:
1023 	case PHY_INTERFACE_MODE_RGMII_ID:
1024 	case PHY_INTERFACE_MODE_RGMII_RXID:
1025 	case PHY_INTERFACE_MODE_RGMII_TXID:
1026 		reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
1027 		break;
1028 	case PHY_INTERFACE_MODE_RMII:
1029 		reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
1030 		break;
1031 	default:
1032 		dev_err(dev, "Unsupported interface mode: %s",
1033 			phy_modes(plat->mac_interface));
1034 		return -EINVAL;
1035 	}
1036 
1037 	regmap_field_write(gmac->regmap_field, reg);
1038 
1039 	return 0;
1040 }
1041 
1042 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
1043 {
1044 	u32 reg = gmac->variant->default_syscon_value;
1045 
1046 	regmap_field_write(gmac->regmap_field, reg);
1047 }
1048 
1049 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
1050 {
1051 	struct sunxi_priv_data *gmac = priv;
1052 
1053 	if (gmac->variant->soc_has_internal_phy)
1054 		sun8i_dwmac_unpower_internal_phy(gmac);
1055 
1056 	if (gmac->regulator)
1057 		regulator_disable(gmac->regulator);
1058 }
1059 
1060 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
1061 {
1062 	u32 value = readl(ioaddr + EMAC_BASIC_CTL0);
1063 
1064 	if (enable)
1065 		value |= EMAC_LOOPBACK;
1066 	else
1067 		value &= ~EMAC_LOOPBACK;
1068 
1069 	writel(value, ioaddr + EMAC_BASIC_CTL0);
1070 }
1071 
1072 static const struct stmmac_ops sun8i_dwmac_ops = {
1073 	.core_init = sun8i_dwmac_core_init,
1074 	.set_mac = sun8i_dwmac_set_mac,
1075 	.dump_regs = sun8i_dwmac_dump_mac_regs,
1076 	.rx_ipc = sun8i_dwmac_rx_ipc_enable,
1077 	.set_filter = sun8i_dwmac_set_filter,
1078 	.flow_ctrl = sun8i_dwmac_flow_ctrl,
1079 	.set_umac_addr = sun8i_dwmac_set_umac_addr,
1080 	.get_umac_addr = sun8i_dwmac_get_umac_addr,
1081 	.set_mac_loopback = sun8i_dwmac_set_mac_loopback,
1082 };
1083 
1084 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
1085 {
1086 	struct mac_device_info *mac;
1087 	struct stmmac_priv *priv = ppriv;
1088 
1089 	mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
1090 	if (!mac)
1091 		return NULL;
1092 
1093 	mac->pcsr = priv->ioaddr;
1094 	mac->mac = &sun8i_dwmac_ops;
1095 	mac->dma = &sun8i_dwmac_dma_ops;
1096 
1097 	priv->dev->priv_flags |= IFF_UNICAST_FLT;
1098 
1099 	/* The loopback bit seems to be re-set when link change
1100 	 * Simply mask it each time
1101 	 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
1102 	 */
1103 	mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
1104 	mac->link.speed10 = EMAC_SPEED_10;
1105 	mac->link.speed100 = EMAC_SPEED_100;
1106 	mac->link.speed1000 = EMAC_SPEED_1000;
1107 	mac->link.duplex = EMAC_DUPLEX_FULL;
1108 	mac->mii.addr = EMAC_MDIO_CMD;
1109 	mac->mii.data = EMAC_MDIO_DATA;
1110 	mac->mii.reg_shift = 4;
1111 	mac->mii.reg_mask = GENMASK(8, 4);
1112 	mac->mii.addr_shift = 12;
1113 	mac->mii.addr_mask = GENMASK(16, 12);
1114 	mac->mii.clk_csr_shift = 20;
1115 	mac->mii.clk_csr_mask = GENMASK(22, 20);
1116 	mac->unicast_filter_entries = 8;
1117 
1118 	/* Synopsys Id is not available */
1119 	priv->synopsys_id = 0;
1120 
1121 	return mac;
1122 }
1123 
1124 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)
1125 {
1126 	struct device_node *syscon_node;
1127 	struct platform_device *syscon_pdev;
1128 	struct regmap *regmap = NULL;
1129 
1130 	syscon_node = of_parse_phandle(node, "syscon", 0);
1131 	if (!syscon_node)
1132 		return ERR_PTR(-ENODEV);
1133 
1134 	syscon_pdev = of_find_device_by_node(syscon_node);
1135 	if (!syscon_pdev) {
1136 		/* platform device might not be probed yet */
1137 		regmap = ERR_PTR(-EPROBE_DEFER);
1138 		goto out_put_node;
1139 	}
1140 
1141 	/* If no regmap is found then the other device driver is at fault */
1142 	regmap = dev_get_regmap(&syscon_pdev->dev, NULL);
1143 	if (!regmap)
1144 		regmap = ERR_PTR(-EINVAL);
1145 
1146 	platform_device_put(syscon_pdev);
1147 out_put_node:
1148 	of_node_put(syscon_node);
1149 	return regmap;
1150 }
1151 
1152 static int sun8i_dwmac_probe(struct platform_device *pdev)
1153 {
1154 	struct plat_stmmacenet_data *plat_dat;
1155 	struct stmmac_resources stmmac_res;
1156 	struct sunxi_priv_data *gmac;
1157 	struct device *dev = &pdev->dev;
1158 	phy_interface_t interface;
1159 	int ret;
1160 	struct stmmac_priv *priv;
1161 	struct net_device *ndev;
1162 	struct regmap *regmap;
1163 
1164 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1165 	if (ret)
1166 		return ret;
1167 
1168 	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1169 	if (!gmac)
1170 		return -ENOMEM;
1171 
1172 	gmac->variant = of_device_get_match_data(&pdev->dev);
1173 	if (!gmac->variant) {
1174 		dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
1175 		return -EINVAL;
1176 	}
1177 
1178 	/* Optional regulator for PHY */
1179 	gmac->regulator = devm_regulator_get_optional(dev, "phy");
1180 	if (IS_ERR(gmac->regulator)) {
1181 		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1182 			return -EPROBE_DEFER;
1183 		dev_info(dev, "No regulator found\n");
1184 		gmac->regulator = NULL;
1185 	}
1186 
1187 	/* The "GMAC clock control" register might be located in the
1188 	 * CCU address range (on the R40), or the system control address
1189 	 * range (on most other sun8i and later SoCs).
1190 	 *
1191 	 * The former controls most if not all clocks in the SoC. The
1192 	 * latter has an SoC identification register, and on some SoCs,
1193 	 * controls to map device specific SRAM to either the intended
1194 	 * peripheral, or the CPU address space.
1195 	 *
1196 	 * In either case, there should be a coordinated and restricted
1197 	 * method of accessing the register needed here. This is done by
1198 	 * having the device export a custom regmap, instead of a generic
1199 	 * syscon, which grants all access to all registers.
1200 	 *
1201 	 * To support old device trees, we fall back to using the syscon
1202 	 * interface if possible.
1203 	 */
1204 	regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node);
1205 	if (IS_ERR(regmap))
1206 		regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1207 							 "syscon");
1208 	if (IS_ERR(regmap)) {
1209 		ret = PTR_ERR(regmap);
1210 		dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1211 		return ret;
1212 	}
1213 
1214 	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
1215 						     *gmac->variant->syscon_field);
1216 	if (IS_ERR(gmac->regmap_field)) {
1217 		ret = PTR_ERR(gmac->regmap_field);
1218 		dev_err(dev, "Unable to map syscon register: %d\n", ret);
1219 		return ret;
1220 	}
1221 
1222 	ret = of_get_phy_mode(dev->of_node, &interface);
1223 	if (ret)
1224 		return -EINVAL;
1225 
1226 	plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
1227 	if (IS_ERR(plat_dat))
1228 		return PTR_ERR(plat_dat);
1229 
1230 	/* platform data specifying hardware features and callbacks.
1231 	 * hardware features were copied from Allwinner drivers.
1232 	 */
1233 	plat_dat->mac_interface = interface;
1234 	plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1235 	plat_dat->tx_coe = 1;
1236 	plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
1237 	plat_dat->bsp_priv = gmac;
1238 	plat_dat->init = sun8i_dwmac_init;
1239 	plat_dat->exit = sun8i_dwmac_exit;
1240 	plat_dat->setup = sun8i_dwmac_setup;
1241 	plat_dat->tx_fifo_size = 4096;
1242 	plat_dat->rx_fifo_size = 16384;
1243 
1244 	ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat);
1245 	if (ret)
1246 		goto dwmac_deconfig;
1247 
1248 	ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1249 	if (ret)
1250 		goto dwmac_syscon;
1251 
1252 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1253 	if (ret)
1254 		goto dwmac_exit;
1255 
1256 	ndev = dev_get_drvdata(&pdev->dev);
1257 	priv = netdev_priv(ndev);
1258 
1259 	/* the MAC is runtime suspended after stmmac_dvr_probe(), so we
1260 	 * need to ensure the MAC resume back before other operations such
1261 	 * as reset.
1262 	 */
1263 	pm_runtime_get_sync(&pdev->dev);
1264 
1265 	/* The mux must be registered after parent MDIO
1266 	 * so after stmmac_dvr_probe()
1267 	 */
1268 	if (gmac->variant->soc_has_internal_phy) {
1269 		ret = get_ephy_nodes(priv);
1270 		if (ret)
1271 			goto dwmac_remove;
1272 		ret = sun8i_dwmac_register_mdio_mux(priv);
1273 		if (ret) {
1274 			dev_err(&pdev->dev, "Failed to register mux\n");
1275 			goto dwmac_mux;
1276 		}
1277 	} else {
1278 		ret = sun8i_dwmac_reset(priv);
1279 		if (ret)
1280 			goto dwmac_remove;
1281 	}
1282 
1283 	pm_runtime_put(&pdev->dev);
1284 
1285 	return 0;
1286 
1287 dwmac_mux:
1288 	reset_control_put(gmac->rst_ephy);
1289 	clk_put(gmac->ephy_clk);
1290 dwmac_remove:
1291 	pm_runtime_put_noidle(&pdev->dev);
1292 	stmmac_dvr_remove(&pdev->dev);
1293 dwmac_exit:
1294 	sun8i_dwmac_exit(pdev, gmac);
1295 dwmac_syscon:
1296 	sun8i_dwmac_unset_syscon(gmac);
1297 dwmac_deconfig:
1298 	stmmac_remove_config_dt(pdev, plat_dat);
1299 
1300 	return ret;
1301 }
1302 
1303 static void sun8i_dwmac_remove(struct platform_device *pdev)
1304 {
1305 	struct net_device *ndev = platform_get_drvdata(pdev);
1306 	struct stmmac_priv *priv = netdev_priv(ndev);
1307 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1308 
1309 	if (gmac->variant->soc_has_internal_phy) {
1310 		mdio_mux_uninit(gmac->mux_handle);
1311 		sun8i_dwmac_unpower_internal_phy(gmac);
1312 		reset_control_put(gmac->rst_ephy);
1313 		clk_put(gmac->ephy_clk);
1314 	}
1315 
1316 	stmmac_pltfr_remove(pdev);
1317 	sun8i_dwmac_unset_syscon(gmac);
1318 }
1319 
1320 static void sun8i_dwmac_shutdown(struct platform_device *pdev)
1321 {
1322 	struct net_device *ndev = platform_get_drvdata(pdev);
1323 	struct stmmac_priv *priv = netdev_priv(ndev);
1324 	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
1325 
1326 	sun8i_dwmac_exit(pdev, gmac);
1327 }
1328 
1329 static const struct of_device_id sun8i_dwmac_match[] = {
1330 	{ .compatible = "allwinner,sun8i-h3-emac",
1331 		.data = &emac_variant_h3 },
1332 	{ .compatible = "allwinner,sun8i-v3s-emac",
1333 		.data = &emac_variant_v3s },
1334 	{ .compatible = "allwinner,sun8i-a83t-emac",
1335 		.data = &emac_variant_a83t },
1336 	{ .compatible = "allwinner,sun8i-r40-gmac",
1337 		.data = &emac_variant_r40 },
1338 	{ .compatible = "allwinner,sun50i-a64-emac",
1339 		.data = &emac_variant_a64 },
1340 	{ .compatible = "allwinner,sun50i-h6-emac",
1341 		.data = &emac_variant_h6 },
1342 	{ }
1343 };
1344 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1345 
1346 static struct platform_driver sun8i_dwmac_driver = {
1347 	.probe  = sun8i_dwmac_probe,
1348 	.remove_new = sun8i_dwmac_remove,
1349 	.shutdown = sun8i_dwmac_shutdown,
1350 	.driver = {
1351 		.name           = "dwmac-sun8i",
1352 		.pm		= &stmmac_pltfr_pm_ops,
1353 		.of_match_table = sun8i_dwmac_match,
1354 	},
1355 };
1356 module_platform_driver(sun8i_dwmac_driver);
1357 
1358 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1359 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1360 MODULE_LICENSE("GPL");
1361