1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/stmmac.h> 22 23 #include "stmmac.h" 24 #include "stmmac_platform.h" 25 26 /* General notes on dwmac-sun8i: 27 * Locking: no locking is necessary in this file because all necessary locking 28 * is done in the "stmmac files" 29 */ 30 31 /* struct emac_variant - Describe dwmac-sun8i hardware variant 32 * @default_syscon_value: The default value of the EMAC register in syscon 33 * This value is used for disabling properly EMAC 34 * and used as a good starting value in case of the 35 * boot process(uboot) leave some stuff. 36 * @syscon_field reg_field for the syscon's gmac register 37 * @soc_has_internal_phy: Does the MAC embed an internal PHY 38 * @support_mii: Does the MAC handle MII 39 * @support_rmii: Does the MAC handle RMII 40 * @support_rgmii: Does the MAC handle RGMII 41 * 42 * @rx_delay_max: Maximum raw value for RX delay chain 43 * @tx_delay_max: Maximum raw value for TX delay chain 44 * These two also indicate the bitmask for 45 * the RX and TX delay chain registers. A 46 * value of zero indicates this is not supported. 47 */ 48 struct emac_variant { 49 u32 default_syscon_value; 50 const struct reg_field *syscon_field; 51 bool soc_has_internal_phy; 52 bool support_mii; 53 bool support_rmii; 54 bool support_rgmii; 55 u8 rx_delay_max; 56 u8 tx_delay_max; 57 }; 58 59 /* struct sunxi_priv_data - hold all sunxi private data 60 * @tx_clk: reference to MAC TX clock 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @use_internal_phy: Is the internal PHY selected for use 68 * @mux_handle: Internal pointer used by mdio-mux lib 69 */ 70 struct sunxi_priv_data { 71 struct clk *tx_clk; 72 struct clk *ephy_clk; 73 struct regulator *regulator; 74 struct reset_control *rst_ephy; 75 const struct emac_variant *variant; 76 struct regmap_field *regmap_field; 77 bool internal_phy_powered; 78 bool use_internal_phy; 79 void *mux_handle; 80 }; 81 82 /* EMAC clock register @ 0x30 in the "system control" address range */ 83 static const struct reg_field sun8i_syscon_reg_field = { 84 .reg = 0x30, 85 .lsb = 0, 86 .msb = 31, 87 }; 88 89 /* EMAC clock register @ 0x164 in the CCU address range */ 90 static const struct reg_field sun8i_ccu_reg_field = { 91 .reg = 0x164, 92 .lsb = 0, 93 .msb = 31, 94 }; 95 96 static const struct emac_variant emac_variant_h3 = { 97 .default_syscon_value = 0x58000, 98 .syscon_field = &sun8i_syscon_reg_field, 99 .soc_has_internal_phy = true, 100 .support_mii = true, 101 .support_rmii = true, 102 .support_rgmii = true, 103 .rx_delay_max = 31, 104 .tx_delay_max = 7, 105 }; 106 107 static const struct emac_variant emac_variant_v3s = { 108 .default_syscon_value = 0x38000, 109 .syscon_field = &sun8i_syscon_reg_field, 110 .soc_has_internal_phy = true, 111 .support_mii = true 112 }; 113 114 static const struct emac_variant emac_variant_a83t = { 115 .default_syscon_value = 0, 116 .syscon_field = &sun8i_syscon_reg_field, 117 .soc_has_internal_phy = false, 118 .support_mii = true, 119 .support_rgmii = true, 120 .rx_delay_max = 31, 121 .tx_delay_max = 7, 122 }; 123 124 static const struct emac_variant emac_variant_r40 = { 125 .default_syscon_value = 0, 126 .syscon_field = &sun8i_ccu_reg_field, 127 .support_mii = true, 128 .support_rgmii = true, 129 .rx_delay_max = 7, 130 }; 131 132 static const struct emac_variant emac_variant_a64 = { 133 .default_syscon_value = 0, 134 .syscon_field = &sun8i_syscon_reg_field, 135 .soc_has_internal_phy = false, 136 .support_mii = true, 137 .support_rmii = true, 138 .support_rgmii = true, 139 .rx_delay_max = 31, 140 .tx_delay_max = 7, 141 }; 142 143 static const struct emac_variant emac_variant_h6 = { 144 .default_syscon_value = 0x50000, 145 .syscon_field = &sun8i_syscon_reg_field, 146 /* The "Internal PHY" of H6 is not on the die. It's on the 147 * co-packaged AC200 chip instead. 148 */ 149 .soc_has_internal_phy = false, 150 .support_mii = true, 151 .support_rmii = true, 152 .support_rgmii = true, 153 .rx_delay_max = 31, 154 .tx_delay_max = 7, 155 }; 156 157 #define EMAC_BASIC_CTL0 0x00 158 #define EMAC_BASIC_CTL1 0x04 159 #define EMAC_INT_STA 0x08 160 #define EMAC_INT_EN 0x0C 161 #define EMAC_TX_CTL0 0x10 162 #define EMAC_TX_CTL1 0x14 163 #define EMAC_TX_FLOW_CTL 0x1C 164 #define EMAC_TX_DESC_LIST 0x20 165 #define EMAC_RX_CTL0 0x24 166 #define EMAC_RX_CTL1 0x28 167 #define EMAC_RX_DESC_LIST 0x34 168 #define EMAC_RX_FRM_FLT 0x38 169 #define EMAC_MDIO_CMD 0x48 170 #define EMAC_MDIO_DATA 0x4C 171 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 172 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 173 #define EMAC_TX_DMA_STA 0xB0 174 #define EMAC_TX_CUR_DESC 0xB4 175 #define EMAC_TX_CUR_BUF 0xB8 176 #define EMAC_RX_DMA_STA 0xC0 177 #define EMAC_RX_CUR_DESC 0xC4 178 #define EMAC_RX_CUR_BUF 0xC8 179 180 /* Use in EMAC_BASIC_CTL0 */ 181 #define EMAC_DUPLEX_FULL BIT(0) 182 #define EMAC_LOOPBACK BIT(1) 183 #define EMAC_SPEED_1000 0 184 #define EMAC_SPEED_100 (0x03 << 2) 185 #define EMAC_SPEED_10 (0x02 << 2) 186 187 /* Use in EMAC_BASIC_CTL1 */ 188 #define EMAC_BURSTLEN_SHIFT 24 189 190 /* Used in EMAC_RX_FRM_FLT */ 191 #define EMAC_FRM_FLT_RXALL BIT(0) 192 #define EMAC_FRM_FLT_CTL BIT(13) 193 #define EMAC_FRM_FLT_MULTICAST BIT(16) 194 195 /* Used in RX_CTL1*/ 196 #define EMAC_RX_MD BIT(1) 197 #define EMAC_RX_TH_MASK GENMASK(5, 4) 198 #define EMAC_RX_TH_32 0 199 #define EMAC_RX_TH_64 (0x1 << 4) 200 #define EMAC_RX_TH_96 (0x2 << 4) 201 #define EMAC_RX_TH_128 (0x3 << 4) 202 #define EMAC_RX_DMA_EN BIT(30) 203 #define EMAC_RX_DMA_START BIT(31) 204 205 /* Used in TX_CTL1*/ 206 #define EMAC_TX_MD BIT(1) 207 #define EMAC_TX_NEXT_FRM BIT(2) 208 #define EMAC_TX_TH_MASK GENMASK(10, 8) 209 #define EMAC_TX_TH_64 0 210 #define EMAC_TX_TH_128 (0x1 << 8) 211 #define EMAC_TX_TH_192 (0x2 << 8) 212 #define EMAC_TX_TH_256 (0x3 << 8) 213 #define EMAC_TX_DMA_EN BIT(30) 214 #define EMAC_TX_DMA_START BIT(31) 215 216 /* Used in RX_CTL0 */ 217 #define EMAC_RX_RECEIVER_EN BIT(31) 218 #define EMAC_RX_DO_CRC BIT(27) 219 #define EMAC_RX_FLOW_CTL_EN BIT(16) 220 221 /* Used in TX_CTL0 */ 222 #define EMAC_TX_TRANSMITTER_EN BIT(31) 223 224 /* Used in EMAC_TX_FLOW_CTL */ 225 #define EMAC_TX_FLOW_CTL_EN BIT(0) 226 227 /* Used in EMAC_INT_STA */ 228 #define EMAC_TX_INT BIT(0) 229 #define EMAC_TX_DMA_STOP_INT BIT(1) 230 #define EMAC_TX_BUF_UA_INT BIT(2) 231 #define EMAC_TX_TIMEOUT_INT BIT(3) 232 #define EMAC_TX_UNDERFLOW_INT BIT(4) 233 #define EMAC_TX_EARLY_INT BIT(5) 234 #define EMAC_RX_INT BIT(8) 235 #define EMAC_RX_BUF_UA_INT BIT(9) 236 #define EMAC_RX_DMA_STOP_INT BIT(10) 237 #define EMAC_RX_TIMEOUT_INT BIT(11) 238 #define EMAC_RX_OVERFLOW_INT BIT(12) 239 #define EMAC_RX_EARLY_INT BIT(13) 240 #define EMAC_RGMII_STA_INT BIT(16) 241 242 #define MAC_ADDR_TYPE_DST BIT(31) 243 244 /* H3 specific bits for EPHY */ 245 #define H3_EPHY_ADDR_SHIFT 20 246 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 247 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 248 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 249 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 250 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 251 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 252 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 253 254 /* H3/A64 specific bits */ 255 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 256 257 /* Generic system control EMAC_CLK bits */ 258 #define SYSCON_ETXDC_SHIFT 10 259 #define SYSCON_ERXDC_SHIFT 5 260 /* EMAC PHY Interface Type */ 261 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 262 #define SYSCON_ETCS_MASK GENMASK(1, 0) 263 #define SYSCON_ETCS_MII 0x0 264 #define SYSCON_ETCS_EXT_GMII 0x1 265 #define SYSCON_ETCS_INT_GMII 0x2 266 267 /* sun8i_dwmac_dma_reset() - reset the EMAC 268 * Called from stmmac via stmmac_dma_ops->reset 269 */ 270 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 271 { 272 writel(0, ioaddr + EMAC_RX_CTL1); 273 writel(0, ioaddr + EMAC_TX_CTL1); 274 writel(0, ioaddr + EMAC_RX_FRM_FLT); 275 writel(0, ioaddr + EMAC_RX_DESC_LIST); 276 writel(0, ioaddr + EMAC_TX_DESC_LIST); 277 writel(0, ioaddr + EMAC_INT_EN); 278 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 279 return 0; 280 } 281 282 /* sun8i_dwmac_dma_init() - initialize the EMAC 283 * Called from stmmac via stmmac_dma_ops->init 284 */ 285 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 286 struct stmmac_dma_cfg *dma_cfg, int atds) 287 { 288 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 289 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 290 } 291 292 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 293 struct stmmac_dma_cfg *dma_cfg, 294 dma_addr_t dma_rx_phy, u32 chan) 295 { 296 /* Write RX descriptors address */ 297 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 298 } 299 300 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 301 struct stmmac_dma_cfg *dma_cfg, 302 dma_addr_t dma_tx_phy, u32 chan) 303 { 304 /* Write TX descriptors address */ 305 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 306 } 307 308 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 309 * Called from stmmac_dma_ops->dump_regs 310 * Used for ethtool 311 */ 312 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 313 { 314 int i; 315 316 for (i = 0; i < 0xC8; i += 4) { 317 if (i == 0x32 || i == 0x3C) 318 continue; 319 reg_space[i / 4] = readl(ioaddr + i); 320 } 321 } 322 323 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 324 * Called from stmmac_ops->dump_regs 325 * Used for ethtool 326 */ 327 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 328 u32 *reg_space) 329 { 330 int i; 331 void __iomem *ioaddr = hw->pcsr; 332 333 for (i = 0; i < 0xC8; i += 4) { 334 if (i == 0x32 || i == 0x3C) 335 continue; 336 reg_space[i / 4] = readl(ioaddr + i); 337 } 338 } 339 340 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, 341 bool rx, bool tx) 342 { 343 u32 value = readl(ioaddr + EMAC_INT_EN); 344 345 if (rx) 346 value |= EMAC_RX_INT; 347 if (tx) 348 value |= EMAC_TX_INT; 349 350 writel(value, ioaddr + EMAC_INT_EN); 351 } 352 353 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, 354 bool rx, bool tx) 355 { 356 u32 value = readl(ioaddr + EMAC_INT_EN); 357 358 if (rx) 359 value &= ~EMAC_RX_INT; 360 if (tx) 361 value &= ~EMAC_TX_INT; 362 363 writel(value, ioaddr + EMAC_INT_EN); 364 } 365 366 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 367 { 368 u32 v; 369 370 v = readl(ioaddr + EMAC_TX_CTL1); 371 v |= EMAC_TX_DMA_START; 372 v |= EMAC_TX_DMA_EN; 373 writel(v, ioaddr + EMAC_TX_CTL1); 374 } 375 376 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 377 { 378 u32 v; 379 380 v = readl(ioaddr + EMAC_TX_CTL1); 381 v |= EMAC_TX_DMA_START; 382 v |= EMAC_TX_DMA_EN; 383 writel(v, ioaddr + EMAC_TX_CTL1); 384 } 385 386 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 387 { 388 u32 v; 389 390 v = readl(ioaddr + EMAC_TX_CTL1); 391 v &= ~EMAC_TX_DMA_EN; 392 writel(v, ioaddr + EMAC_TX_CTL1); 393 } 394 395 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 396 { 397 u32 v; 398 399 v = readl(ioaddr + EMAC_RX_CTL1); 400 v |= EMAC_RX_DMA_START; 401 v |= EMAC_RX_DMA_EN; 402 writel(v, ioaddr + EMAC_RX_CTL1); 403 } 404 405 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 406 { 407 u32 v; 408 409 v = readl(ioaddr + EMAC_RX_CTL1); 410 v &= ~EMAC_RX_DMA_EN; 411 writel(v, ioaddr + EMAC_RX_CTL1); 412 } 413 414 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 415 struct stmmac_extra_stats *x, u32 chan) 416 { 417 u32 v; 418 int ret = 0; 419 420 v = readl(ioaddr + EMAC_INT_STA); 421 422 if (v & EMAC_TX_INT) { 423 ret |= handle_tx; 424 x->tx_normal_irq_n++; 425 } 426 427 if (v & EMAC_TX_DMA_STOP_INT) 428 x->tx_process_stopped_irq++; 429 430 if (v & EMAC_TX_BUF_UA_INT) 431 x->tx_process_stopped_irq++; 432 433 if (v & EMAC_TX_TIMEOUT_INT) 434 ret |= tx_hard_error; 435 436 if (v & EMAC_TX_UNDERFLOW_INT) { 437 ret |= tx_hard_error; 438 x->tx_undeflow_irq++; 439 } 440 441 if (v & EMAC_TX_EARLY_INT) 442 x->tx_early_irq++; 443 444 if (v & EMAC_RX_INT) { 445 ret |= handle_rx; 446 x->rx_normal_irq_n++; 447 } 448 449 if (v & EMAC_RX_BUF_UA_INT) 450 x->rx_buf_unav_irq++; 451 452 if (v & EMAC_RX_DMA_STOP_INT) 453 x->rx_process_stopped_irq++; 454 455 if (v & EMAC_RX_TIMEOUT_INT) 456 ret |= tx_hard_error; 457 458 if (v & EMAC_RX_OVERFLOW_INT) { 459 ret |= tx_hard_error; 460 x->rx_overflow_irq++; 461 } 462 463 if (v & EMAC_RX_EARLY_INT) 464 x->rx_early_irq++; 465 466 if (v & EMAC_RGMII_STA_INT) 467 x->irq_rgmii_n++; 468 469 writel(v, ioaddr + EMAC_INT_STA); 470 471 return ret; 472 } 473 474 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 475 u32 channel, int fifosz, u8 qmode) 476 { 477 u32 v; 478 479 v = readl(ioaddr + EMAC_RX_CTL1); 480 if (mode == SF_DMA_MODE) { 481 v |= EMAC_RX_MD; 482 } else { 483 v &= ~EMAC_RX_MD; 484 v &= ~EMAC_RX_TH_MASK; 485 if (mode < 32) 486 v |= EMAC_RX_TH_32; 487 else if (mode < 64) 488 v |= EMAC_RX_TH_64; 489 else if (mode < 96) 490 v |= EMAC_RX_TH_96; 491 else if (mode < 128) 492 v |= EMAC_RX_TH_128; 493 } 494 writel(v, ioaddr + EMAC_RX_CTL1); 495 } 496 497 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 498 u32 channel, int fifosz, u8 qmode) 499 { 500 u32 v; 501 502 v = readl(ioaddr + EMAC_TX_CTL1); 503 if (mode == SF_DMA_MODE) { 504 v |= EMAC_TX_MD; 505 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 506 * comment is 507 * "Operating on second frame increase the performance 508 * especially when transmit store-and-forward is used." 509 */ 510 v |= EMAC_TX_NEXT_FRM; 511 } else { 512 v &= ~EMAC_TX_MD; 513 v &= ~EMAC_TX_TH_MASK; 514 if (mode < 64) 515 v |= EMAC_TX_TH_64; 516 else if (mode < 128) 517 v |= EMAC_TX_TH_128; 518 else if (mode < 192) 519 v |= EMAC_TX_TH_192; 520 else if (mode < 256) 521 v |= EMAC_TX_TH_256; 522 } 523 writel(v, ioaddr + EMAC_TX_CTL1); 524 } 525 526 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 527 .reset = sun8i_dwmac_dma_reset, 528 .init = sun8i_dwmac_dma_init, 529 .init_rx_chan = sun8i_dwmac_dma_init_rx, 530 .init_tx_chan = sun8i_dwmac_dma_init_tx, 531 .dump_regs = sun8i_dwmac_dump_regs, 532 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 533 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 534 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 535 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 536 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 537 .start_tx = sun8i_dwmac_dma_start_tx, 538 .stop_tx = sun8i_dwmac_dma_stop_tx, 539 .start_rx = sun8i_dwmac_dma_start_rx, 540 .stop_rx = sun8i_dwmac_dma_stop_rx, 541 .dma_interrupt = sun8i_dwmac_dma_interrupt, 542 }; 543 544 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); 545 546 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 547 { 548 struct net_device *ndev = platform_get_drvdata(pdev); 549 struct sunxi_priv_data *gmac = priv; 550 int ret; 551 552 if (gmac->regulator) { 553 ret = regulator_enable(gmac->regulator); 554 if (ret) { 555 dev_err(&pdev->dev, "Fail to enable regulator\n"); 556 return ret; 557 } 558 } 559 560 ret = clk_prepare_enable(gmac->tx_clk); 561 if (ret) { 562 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 563 goto err_disable_regulator; 564 } 565 566 if (gmac->use_internal_phy) { 567 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); 568 if (ret) 569 goto err_disable_clk; 570 } 571 572 return 0; 573 574 err_disable_clk: 575 clk_disable_unprepare(gmac->tx_clk); 576 err_disable_regulator: 577 if (gmac->regulator) 578 regulator_disable(gmac->regulator); 579 580 return ret; 581 } 582 583 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 584 struct net_device *dev) 585 { 586 void __iomem *ioaddr = hw->pcsr; 587 u32 v; 588 589 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 590 writel(v, ioaddr + EMAC_BASIC_CTL1); 591 } 592 593 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 594 { 595 u32 t, r; 596 597 t = readl(ioaddr + EMAC_TX_CTL0); 598 r = readl(ioaddr + EMAC_RX_CTL0); 599 if (enable) { 600 t |= EMAC_TX_TRANSMITTER_EN; 601 r |= EMAC_RX_RECEIVER_EN; 602 } else { 603 t &= ~EMAC_TX_TRANSMITTER_EN; 604 r &= ~EMAC_RX_RECEIVER_EN; 605 } 606 writel(t, ioaddr + EMAC_TX_CTL0); 607 writel(r, ioaddr + EMAC_RX_CTL0); 608 } 609 610 /* Set MAC address at slot reg_n 611 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 612 * If addr is NULL, clear the slot 613 */ 614 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 615 unsigned char *addr, 616 unsigned int reg_n) 617 { 618 void __iomem *ioaddr = hw->pcsr; 619 u32 v; 620 621 if (!addr) { 622 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 623 return; 624 } 625 626 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 627 EMAC_MACADDR_LO(reg_n)); 628 if (reg_n > 0) { 629 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 630 v |= MAC_ADDR_TYPE_DST; 631 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 632 } 633 } 634 635 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 636 unsigned char *addr, 637 unsigned int reg_n) 638 { 639 void __iomem *ioaddr = hw->pcsr; 640 641 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 642 EMAC_MACADDR_LO(reg_n)); 643 } 644 645 /* caution this function must return non 0 to work */ 646 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 647 { 648 void __iomem *ioaddr = hw->pcsr; 649 u32 v; 650 651 v = readl(ioaddr + EMAC_RX_CTL0); 652 v |= EMAC_RX_DO_CRC; 653 writel(v, ioaddr + EMAC_RX_CTL0); 654 655 return 1; 656 } 657 658 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 659 struct net_device *dev) 660 { 661 void __iomem *ioaddr = hw->pcsr; 662 u32 v; 663 int i = 1; 664 struct netdev_hw_addr *ha; 665 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 666 667 v = EMAC_FRM_FLT_CTL; 668 669 if (dev->flags & IFF_PROMISC) { 670 v = EMAC_FRM_FLT_RXALL; 671 } else if (dev->flags & IFF_ALLMULTI) { 672 v |= EMAC_FRM_FLT_MULTICAST; 673 } else if (macaddrs <= hw->unicast_filter_entries) { 674 if (!netdev_mc_empty(dev)) { 675 netdev_for_each_mc_addr(ha, dev) { 676 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 677 i++; 678 } 679 } 680 if (!netdev_uc_empty(dev)) { 681 netdev_for_each_uc_addr(ha, dev) { 682 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 683 i++; 684 } 685 } 686 } else { 687 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 688 netdev_info(dev, "Too many address, switching to promiscuous\n"); 689 v = EMAC_FRM_FLT_RXALL; 690 } 691 692 /* Disable unused address filter slots */ 693 while (i < hw->unicast_filter_entries) 694 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 695 696 writel(v, ioaddr + EMAC_RX_FRM_FLT); 697 } 698 699 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 700 unsigned int duplex, unsigned int fc, 701 unsigned int pause_time, u32 tx_cnt) 702 { 703 void __iomem *ioaddr = hw->pcsr; 704 u32 v; 705 706 v = readl(ioaddr + EMAC_RX_CTL0); 707 if (fc == FLOW_AUTO) 708 v |= EMAC_RX_FLOW_CTL_EN; 709 else 710 v &= ~EMAC_RX_FLOW_CTL_EN; 711 writel(v, ioaddr + EMAC_RX_CTL0); 712 713 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 714 if (fc == FLOW_AUTO) 715 v |= EMAC_TX_FLOW_CTL_EN; 716 else 717 v &= ~EMAC_TX_FLOW_CTL_EN; 718 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 719 } 720 721 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 722 { 723 u32 v; 724 int err; 725 726 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 727 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 728 729 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 730 * need more if no cable plugged. 100ms seems OK 731 */ 732 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 733 !(v & 0x01), 100, 100000); 734 735 if (err) { 736 dev_err(priv->device, "EMAC reset timeout\n"); 737 return -EFAULT; 738 } 739 return 0; 740 } 741 742 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 743 static int get_ephy_nodes(struct stmmac_priv *priv) 744 { 745 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 746 struct device_node *mdio_mux, *iphynode; 747 struct device_node *mdio_internal; 748 int ret; 749 750 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 751 if (!mdio_mux) { 752 dev_err(priv->device, "Cannot get mdio-mux node\n"); 753 return -ENODEV; 754 } 755 756 mdio_internal = of_get_compatible_child(mdio_mux, 757 "allwinner,sun8i-h3-mdio-internal"); 758 of_node_put(mdio_mux); 759 if (!mdio_internal) { 760 dev_err(priv->device, "Cannot get internal_mdio node\n"); 761 return -ENODEV; 762 } 763 764 /* Seek for internal PHY */ 765 for_each_child_of_node(mdio_internal, iphynode) { 766 gmac->ephy_clk = of_clk_get(iphynode, 0); 767 if (IS_ERR(gmac->ephy_clk)) 768 continue; 769 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 770 if (IS_ERR(gmac->rst_ephy)) { 771 ret = PTR_ERR(gmac->rst_ephy); 772 if (ret == -EPROBE_DEFER) { 773 of_node_put(iphynode); 774 of_node_put(mdio_internal); 775 return ret; 776 } 777 continue; 778 } 779 dev_info(priv->device, "Found internal PHY node\n"); 780 of_node_put(iphynode); 781 of_node_put(mdio_internal); 782 return 0; 783 } 784 785 of_node_put(mdio_internal); 786 return -ENODEV; 787 } 788 789 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 790 { 791 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 792 int ret; 793 794 if (gmac->internal_phy_powered) { 795 dev_warn(priv->device, "Internal PHY already powered\n"); 796 return 0; 797 } 798 799 dev_info(priv->device, "Powering internal PHY\n"); 800 ret = clk_prepare_enable(gmac->ephy_clk); 801 if (ret) { 802 dev_err(priv->device, "Cannot enable internal PHY\n"); 803 return ret; 804 } 805 806 /* Make sure the EPHY is properly reseted, as U-Boot may leave 807 * it at deasserted state, and thus it may fail to reset EMAC. 808 * 809 * This assumes the driver has exclusive access to the EPHY reset. 810 */ 811 ret = reset_control_reset(gmac->rst_ephy); 812 if (ret) { 813 dev_err(priv->device, "Cannot reset internal PHY\n"); 814 clk_disable_unprepare(gmac->ephy_clk); 815 return ret; 816 } 817 818 gmac->internal_phy_powered = true; 819 820 return 0; 821 } 822 823 static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 824 { 825 if (!gmac->internal_phy_powered) 826 return; 827 828 clk_disable_unprepare(gmac->ephy_clk); 829 reset_control_assert(gmac->rst_ephy); 830 gmac->internal_phy_powered = false; 831 } 832 833 /* MDIO multiplexing switch function 834 * This function is called by the mdio-mux layer when it thinks the mdio bus 835 * multiplexer needs to switch. 836 * 'current_child' is the current value of the mux register 837 * 'desired_child' is the value of the 'reg' property of the target child MDIO 838 * node. 839 * The first time this function is called, current_child == -1. 840 * If current_child == desired_child, then the mux is already set to the 841 * correct bus. 842 */ 843 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 844 void *data) 845 { 846 struct stmmac_priv *priv = data; 847 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 848 u32 reg, val; 849 int ret = 0; 850 851 if (current_child ^ desired_child) { 852 regmap_field_read(gmac->regmap_field, ®); 853 switch (desired_child) { 854 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 855 dev_info(priv->device, "Switch mux to internal PHY"); 856 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 857 gmac->use_internal_phy = true; 858 break; 859 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 860 dev_info(priv->device, "Switch mux to external PHY"); 861 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 862 gmac->use_internal_phy = false; 863 break; 864 default: 865 dev_err(priv->device, "Invalid child ID %x\n", 866 desired_child); 867 return -EINVAL; 868 } 869 regmap_field_write(gmac->regmap_field, val); 870 if (gmac->use_internal_phy) { 871 ret = sun8i_dwmac_power_internal_phy(priv); 872 if (ret) 873 return ret; 874 } else { 875 sun8i_dwmac_unpower_internal_phy(gmac); 876 } 877 /* After changing syscon value, the MAC need reset or it will 878 * use the last value (and so the last PHY set). 879 */ 880 ret = sun8i_dwmac_reset(priv); 881 } 882 return ret; 883 } 884 885 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 886 { 887 int ret; 888 struct device_node *mdio_mux; 889 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 890 891 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 892 if (!mdio_mux) 893 return -ENODEV; 894 895 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 896 &gmac->mux_handle, priv, priv->mii); 897 return ret; 898 } 899 900 static int sun8i_dwmac_set_syscon(struct device *dev, 901 struct plat_stmmacenet_data *plat) 902 { 903 struct sunxi_priv_data *gmac = plat->bsp_priv; 904 struct device_node *node = dev->of_node; 905 int ret; 906 u32 reg, val; 907 908 ret = regmap_field_read(gmac->regmap_field, &val); 909 if (ret) { 910 dev_err(dev, "Fail to read from regmap field.\n"); 911 return ret; 912 } 913 914 reg = gmac->variant->default_syscon_value; 915 if (reg != val) 916 dev_warn(dev, 917 "Current syscon value is not the default %x (expect %x)\n", 918 val, reg); 919 920 if (gmac->variant->soc_has_internal_phy) { 921 if (of_property_read_bool(node, "allwinner,leds-active-low")) 922 reg |= H3_EPHY_LED_POL; 923 else 924 reg &= ~H3_EPHY_LED_POL; 925 926 /* Force EPHY xtal frequency to 24MHz. */ 927 reg |= H3_EPHY_CLK_SEL; 928 929 ret = of_mdio_parse_addr(dev, plat->phy_node); 930 if (ret < 0) { 931 dev_err(dev, "Could not parse MDIO addr\n"); 932 return ret; 933 } 934 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 935 * address. No need to mask it again. 936 */ 937 reg |= 1 << H3_EPHY_ADDR_SHIFT; 938 } else { 939 /* For SoCs without internal PHY the PHY selection bit should be 940 * set to 0 (external PHY). 941 */ 942 reg &= ~H3_EPHY_SELECT; 943 } 944 945 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 946 if (val % 100) { 947 dev_err(dev, "tx-delay must be a multiple of 100\n"); 948 return -EINVAL; 949 } 950 val /= 100; 951 dev_dbg(dev, "set tx-delay to %x\n", val); 952 if (val <= gmac->variant->tx_delay_max) { 953 reg &= ~(gmac->variant->tx_delay_max << 954 SYSCON_ETXDC_SHIFT); 955 reg |= (val << SYSCON_ETXDC_SHIFT); 956 } else { 957 dev_err(dev, "Invalid TX clock delay: %d\n", 958 val); 959 return -EINVAL; 960 } 961 } 962 963 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 964 if (val % 100) { 965 dev_err(dev, "rx-delay must be a multiple of 100\n"); 966 return -EINVAL; 967 } 968 val /= 100; 969 dev_dbg(dev, "set rx-delay to %x\n", val); 970 if (val <= gmac->variant->rx_delay_max) { 971 reg &= ~(gmac->variant->rx_delay_max << 972 SYSCON_ERXDC_SHIFT); 973 reg |= (val << SYSCON_ERXDC_SHIFT); 974 } else { 975 dev_err(dev, "Invalid RX clock delay: %d\n", 976 val); 977 return -EINVAL; 978 } 979 } 980 981 /* Clear interface mode bits */ 982 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 983 if (gmac->variant->support_rmii) 984 reg &= ~SYSCON_RMII_EN; 985 986 switch (plat->interface) { 987 case PHY_INTERFACE_MODE_MII: 988 /* default */ 989 break; 990 case PHY_INTERFACE_MODE_RGMII: 991 case PHY_INTERFACE_MODE_RGMII_ID: 992 case PHY_INTERFACE_MODE_RGMII_RXID: 993 case PHY_INTERFACE_MODE_RGMII_TXID: 994 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 995 break; 996 case PHY_INTERFACE_MODE_RMII: 997 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 998 break; 999 default: 1000 dev_err(dev, "Unsupported interface mode: %s", 1001 phy_modes(plat->interface)); 1002 return -EINVAL; 1003 } 1004 1005 regmap_field_write(gmac->regmap_field, reg); 1006 1007 return 0; 1008 } 1009 1010 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 1011 { 1012 u32 reg = gmac->variant->default_syscon_value; 1013 1014 regmap_field_write(gmac->regmap_field, reg); 1015 } 1016 1017 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 1018 { 1019 struct sunxi_priv_data *gmac = priv; 1020 1021 if (gmac->variant->soc_has_internal_phy) 1022 sun8i_dwmac_unpower_internal_phy(gmac); 1023 1024 clk_disable_unprepare(gmac->tx_clk); 1025 1026 if (gmac->regulator) 1027 regulator_disable(gmac->regulator); 1028 } 1029 1030 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1031 { 1032 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1033 1034 if (enable) 1035 value |= EMAC_LOOPBACK; 1036 else 1037 value &= ~EMAC_LOOPBACK; 1038 1039 writel(value, ioaddr + EMAC_BASIC_CTL0); 1040 } 1041 1042 static const struct stmmac_ops sun8i_dwmac_ops = { 1043 .core_init = sun8i_dwmac_core_init, 1044 .set_mac = sun8i_dwmac_set_mac, 1045 .dump_regs = sun8i_dwmac_dump_mac_regs, 1046 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1047 .set_filter = sun8i_dwmac_set_filter, 1048 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1049 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1050 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1051 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1052 }; 1053 1054 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1055 { 1056 struct mac_device_info *mac; 1057 struct stmmac_priv *priv = ppriv; 1058 1059 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1060 if (!mac) 1061 return NULL; 1062 1063 mac->pcsr = priv->ioaddr; 1064 mac->mac = &sun8i_dwmac_ops; 1065 mac->dma = &sun8i_dwmac_dma_ops; 1066 1067 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1068 1069 /* The loopback bit seems to be re-set when link change 1070 * Simply mask it each time 1071 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1072 */ 1073 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1074 mac->link.speed10 = EMAC_SPEED_10; 1075 mac->link.speed100 = EMAC_SPEED_100; 1076 mac->link.speed1000 = EMAC_SPEED_1000; 1077 mac->link.duplex = EMAC_DUPLEX_FULL; 1078 mac->mii.addr = EMAC_MDIO_CMD; 1079 mac->mii.data = EMAC_MDIO_DATA; 1080 mac->mii.reg_shift = 4; 1081 mac->mii.reg_mask = GENMASK(8, 4); 1082 mac->mii.addr_shift = 12; 1083 mac->mii.addr_mask = GENMASK(16, 12); 1084 mac->mii.clk_csr_shift = 20; 1085 mac->mii.clk_csr_mask = GENMASK(22, 20); 1086 mac->unicast_filter_entries = 8; 1087 1088 /* Synopsys Id is not available */ 1089 priv->synopsys_id = 0; 1090 1091 return mac; 1092 } 1093 1094 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1095 { 1096 struct device_node *syscon_node; 1097 struct platform_device *syscon_pdev; 1098 struct regmap *regmap = NULL; 1099 1100 syscon_node = of_parse_phandle(node, "syscon", 0); 1101 if (!syscon_node) 1102 return ERR_PTR(-ENODEV); 1103 1104 syscon_pdev = of_find_device_by_node(syscon_node); 1105 if (!syscon_pdev) { 1106 /* platform device might not be probed yet */ 1107 regmap = ERR_PTR(-EPROBE_DEFER); 1108 goto out_put_node; 1109 } 1110 1111 /* If no regmap is found then the other device driver is at fault */ 1112 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1113 if (!regmap) 1114 regmap = ERR_PTR(-EINVAL); 1115 1116 platform_device_put(syscon_pdev); 1117 out_put_node: 1118 of_node_put(syscon_node); 1119 return regmap; 1120 } 1121 1122 static int sun8i_dwmac_probe(struct platform_device *pdev) 1123 { 1124 struct plat_stmmacenet_data *plat_dat; 1125 struct stmmac_resources stmmac_res; 1126 struct sunxi_priv_data *gmac; 1127 struct device *dev = &pdev->dev; 1128 phy_interface_t interface; 1129 int ret; 1130 struct stmmac_priv *priv; 1131 struct net_device *ndev; 1132 struct regmap *regmap; 1133 1134 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1135 if (ret) 1136 return ret; 1137 1138 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1139 if (!gmac) 1140 return -ENOMEM; 1141 1142 gmac->variant = of_device_get_match_data(&pdev->dev); 1143 if (!gmac->variant) { 1144 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1145 return -EINVAL; 1146 } 1147 1148 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1149 if (IS_ERR(gmac->tx_clk)) { 1150 dev_err(dev, "Could not get TX clock\n"); 1151 return PTR_ERR(gmac->tx_clk); 1152 } 1153 1154 /* Optional regulator for PHY */ 1155 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1156 if (IS_ERR(gmac->regulator)) { 1157 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1158 return -EPROBE_DEFER; 1159 dev_info(dev, "No regulator found\n"); 1160 gmac->regulator = NULL; 1161 } 1162 1163 /* The "GMAC clock control" register might be located in the 1164 * CCU address range (on the R40), or the system control address 1165 * range (on most other sun8i and later SoCs). 1166 * 1167 * The former controls most if not all clocks in the SoC. The 1168 * latter has an SoC identification register, and on some SoCs, 1169 * controls to map device specific SRAM to either the intended 1170 * peripheral, or the CPU address space. 1171 * 1172 * In either case, there should be a coordinated and restricted 1173 * method of accessing the register needed here. This is done by 1174 * having the device export a custom regmap, instead of a generic 1175 * syscon, which grants all access to all registers. 1176 * 1177 * To support old device trees, we fall back to using the syscon 1178 * interface if possible. 1179 */ 1180 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1181 if (IS_ERR(regmap)) 1182 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1183 "syscon"); 1184 if (IS_ERR(regmap)) { 1185 ret = PTR_ERR(regmap); 1186 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1187 return ret; 1188 } 1189 1190 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1191 *gmac->variant->syscon_field); 1192 if (IS_ERR(gmac->regmap_field)) { 1193 ret = PTR_ERR(gmac->regmap_field); 1194 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1195 return ret; 1196 } 1197 1198 ret = of_get_phy_mode(dev->of_node, &interface); 1199 if (ret) 1200 return -EINVAL; 1201 1202 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1203 if (IS_ERR(plat_dat)) 1204 return PTR_ERR(plat_dat); 1205 1206 /* platform data specifying hardware features and callbacks. 1207 * hardware features were copied from Allwinner drivers. 1208 */ 1209 plat_dat->interface = interface; 1210 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1211 plat_dat->tx_coe = 1; 1212 plat_dat->has_sun8i = true; 1213 plat_dat->bsp_priv = gmac; 1214 plat_dat->init = sun8i_dwmac_init; 1215 plat_dat->exit = sun8i_dwmac_exit; 1216 plat_dat->setup = sun8i_dwmac_setup; 1217 plat_dat->tx_fifo_size = 4096; 1218 plat_dat->rx_fifo_size = 16384; 1219 1220 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); 1221 if (ret) 1222 goto dwmac_deconfig; 1223 1224 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1225 if (ret) 1226 goto dwmac_syscon; 1227 1228 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1229 if (ret) 1230 goto dwmac_exit; 1231 1232 ndev = dev_get_drvdata(&pdev->dev); 1233 priv = netdev_priv(ndev); 1234 1235 /* The mux must be registered after parent MDIO 1236 * so after stmmac_dvr_probe() 1237 */ 1238 if (gmac->variant->soc_has_internal_phy) { 1239 ret = get_ephy_nodes(priv); 1240 if (ret) 1241 goto dwmac_remove; 1242 ret = sun8i_dwmac_register_mdio_mux(priv); 1243 if (ret) { 1244 dev_err(&pdev->dev, "Failed to register mux\n"); 1245 goto dwmac_mux; 1246 } 1247 } else { 1248 ret = sun8i_dwmac_reset(priv); 1249 if (ret) 1250 goto dwmac_remove; 1251 } 1252 1253 return 0; 1254 1255 dwmac_mux: 1256 reset_control_put(gmac->rst_ephy); 1257 clk_put(gmac->ephy_clk); 1258 dwmac_remove: 1259 stmmac_dvr_remove(&pdev->dev); 1260 dwmac_exit: 1261 sun8i_dwmac_exit(pdev, gmac); 1262 dwmac_syscon: 1263 sun8i_dwmac_unset_syscon(gmac); 1264 dwmac_deconfig: 1265 stmmac_remove_config_dt(pdev, plat_dat); 1266 1267 return ret; 1268 } 1269 1270 static int sun8i_dwmac_remove(struct platform_device *pdev) 1271 { 1272 struct net_device *ndev = platform_get_drvdata(pdev); 1273 struct stmmac_priv *priv = netdev_priv(ndev); 1274 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1275 1276 if (gmac->variant->soc_has_internal_phy) { 1277 mdio_mux_uninit(gmac->mux_handle); 1278 sun8i_dwmac_unpower_internal_phy(gmac); 1279 reset_control_put(gmac->rst_ephy); 1280 clk_put(gmac->ephy_clk); 1281 } 1282 1283 stmmac_pltfr_remove(pdev); 1284 sun8i_dwmac_unset_syscon(gmac); 1285 1286 return 0; 1287 } 1288 1289 static void sun8i_dwmac_shutdown(struct platform_device *pdev) 1290 { 1291 struct net_device *ndev = platform_get_drvdata(pdev); 1292 struct stmmac_priv *priv = netdev_priv(ndev); 1293 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1294 1295 sun8i_dwmac_exit(pdev, gmac); 1296 } 1297 1298 static const struct of_device_id sun8i_dwmac_match[] = { 1299 { .compatible = "allwinner,sun8i-h3-emac", 1300 .data = &emac_variant_h3 }, 1301 { .compatible = "allwinner,sun8i-v3s-emac", 1302 .data = &emac_variant_v3s }, 1303 { .compatible = "allwinner,sun8i-a83t-emac", 1304 .data = &emac_variant_a83t }, 1305 { .compatible = "allwinner,sun8i-r40-gmac", 1306 .data = &emac_variant_r40 }, 1307 { .compatible = "allwinner,sun50i-a64-emac", 1308 .data = &emac_variant_a64 }, 1309 { .compatible = "allwinner,sun50i-h6-emac", 1310 .data = &emac_variant_h6 }, 1311 { } 1312 }; 1313 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1314 1315 static struct platform_driver sun8i_dwmac_driver = { 1316 .probe = sun8i_dwmac_probe, 1317 .remove = sun8i_dwmac_remove, 1318 .shutdown = sun8i_dwmac_shutdown, 1319 .driver = { 1320 .name = "dwmac-sun8i", 1321 .pm = &stmmac_pltfr_pm_ops, 1322 .of_match_table = sun8i_dwmac_match, 1323 }, 1324 }; 1325 module_platform_driver(sun8i_dwmac_driver); 1326 1327 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1328 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1329 MODULE_LICENSE("GPL"); 1330