1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/stmmac.h> 22 23 #include "stmmac.h" 24 #include "stmmac_platform.h" 25 26 /* General notes on dwmac-sun8i: 27 * Locking: no locking is necessary in this file because all necessary locking 28 * is done in the "stmmac files" 29 */ 30 31 /* struct emac_variant - Describe dwmac-sun8i hardware variant 32 * @default_syscon_value: The default value of the EMAC register in syscon 33 * This value is used for disabling properly EMAC 34 * and used as a good starting value in case of the 35 * boot process(uboot) leave some stuff. 36 * @syscon_field reg_field for the syscon's gmac register 37 * @soc_has_internal_phy: Does the MAC embed an internal PHY 38 * @support_mii: Does the MAC handle MII 39 * @support_rmii: Does the MAC handle RMII 40 * @support_rgmii: Does the MAC handle RGMII 41 * 42 * @rx_delay_max: Maximum raw value for RX delay chain 43 * @tx_delay_max: Maximum raw value for TX delay chain 44 * These two also indicate the bitmask for 45 * the RX and TX delay chain registers. A 46 * value of zero indicates this is not supported. 47 */ 48 struct emac_variant { 49 u32 default_syscon_value; 50 const struct reg_field *syscon_field; 51 bool soc_has_internal_phy; 52 bool support_mii; 53 bool support_rmii; 54 bool support_rgmii; 55 u8 rx_delay_max; 56 u8 tx_delay_max; 57 }; 58 59 /* struct sunxi_priv_data - hold all sunxi private data 60 * @tx_clk: reference to MAC TX clock 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @mux_handle: Internal pointer used by mdio-mux lib 68 */ 69 struct sunxi_priv_data { 70 struct clk *tx_clk; 71 struct clk *ephy_clk; 72 struct regulator *regulator; 73 struct reset_control *rst_ephy; 74 const struct emac_variant *variant; 75 struct regmap_field *regmap_field; 76 bool internal_phy_powered; 77 void *mux_handle; 78 }; 79 80 /* EMAC clock register @ 0x30 in the "system control" address range */ 81 static const struct reg_field sun8i_syscon_reg_field = { 82 .reg = 0x30, 83 .lsb = 0, 84 .msb = 31, 85 }; 86 87 /* EMAC clock register @ 0x164 in the CCU address range */ 88 static const struct reg_field sun8i_ccu_reg_field = { 89 .reg = 0x164, 90 .lsb = 0, 91 .msb = 31, 92 }; 93 94 static const struct emac_variant emac_variant_h3 = { 95 .default_syscon_value = 0x58000, 96 .syscon_field = &sun8i_syscon_reg_field, 97 .soc_has_internal_phy = true, 98 .support_mii = true, 99 .support_rmii = true, 100 .support_rgmii = true, 101 .rx_delay_max = 31, 102 .tx_delay_max = 7, 103 }; 104 105 static const struct emac_variant emac_variant_v3s = { 106 .default_syscon_value = 0x38000, 107 .syscon_field = &sun8i_syscon_reg_field, 108 .soc_has_internal_phy = true, 109 .support_mii = true 110 }; 111 112 static const struct emac_variant emac_variant_a83t = { 113 .default_syscon_value = 0, 114 .syscon_field = &sun8i_syscon_reg_field, 115 .soc_has_internal_phy = false, 116 .support_mii = true, 117 .support_rgmii = true, 118 .rx_delay_max = 31, 119 .tx_delay_max = 7, 120 }; 121 122 static const struct emac_variant emac_variant_r40 = { 123 .default_syscon_value = 0, 124 .syscon_field = &sun8i_ccu_reg_field, 125 .support_mii = true, 126 .support_rgmii = true, 127 .rx_delay_max = 7, 128 }; 129 130 static const struct emac_variant emac_variant_a64 = { 131 .default_syscon_value = 0, 132 .syscon_field = &sun8i_syscon_reg_field, 133 .soc_has_internal_phy = false, 134 .support_mii = true, 135 .support_rmii = true, 136 .support_rgmii = true, 137 .rx_delay_max = 31, 138 .tx_delay_max = 7, 139 }; 140 141 #define EMAC_BASIC_CTL0 0x00 142 #define EMAC_BASIC_CTL1 0x04 143 #define EMAC_INT_STA 0x08 144 #define EMAC_INT_EN 0x0C 145 #define EMAC_TX_CTL0 0x10 146 #define EMAC_TX_CTL1 0x14 147 #define EMAC_TX_FLOW_CTL 0x1C 148 #define EMAC_TX_DESC_LIST 0x20 149 #define EMAC_RX_CTL0 0x24 150 #define EMAC_RX_CTL1 0x28 151 #define EMAC_RX_DESC_LIST 0x34 152 #define EMAC_RX_FRM_FLT 0x38 153 #define EMAC_MDIO_CMD 0x48 154 #define EMAC_MDIO_DATA 0x4C 155 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 156 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 157 #define EMAC_TX_DMA_STA 0xB0 158 #define EMAC_TX_CUR_DESC 0xB4 159 #define EMAC_TX_CUR_BUF 0xB8 160 #define EMAC_RX_DMA_STA 0xC0 161 #define EMAC_RX_CUR_DESC 0xC4 162 #define EMAC_RX_CUR_BUF 0xC8 163 164 /* Use in EMAC_BASIC_CTL0 */ 165 #define EMAC_DUPLEX_FULL BIT(0) 166 #define EMAC_LOOPBACK BIT(1) 167 #define EMAC_SPEED_1000 0 168 #define EMAC_SPEED_100 (0x03 << 2) 169 #define EMAC_SPEED_10 (0x02 << 2) 170 171 /* Use in EMAC_BASIC_CTL1 */ 172 #define EMAC_BURSTLEN_SHIFT 24 173 174 /* Used in EMAC_RX_FRM_FLT */ 175 #define EMAC_FRM_FLT_RXALL BIT(0) 176 #define EMAC_FRM_FLT_CTL BIT(13) 177 #define EMAC_FRM_FLT_MULTICAST BIT(16) 178 179 /* Used in RX_CTL1*/ 180 #define EMAC_RX_MD BIT(1) 181 #define EMAC_RX_TH_MASK GENMASK(4, 5) 182 #define EMAC_RX_TH_32 0 183 #define EMAC_RX_TH_64 (0x1 << 4) 184 #define EMAC_RX_TH_96 (0x2 << 4) 185 #define EMAC_RX_TH_128 (0x3 << 4) 186 #define EMAC_RX_DMA_EN BIT(30) 187 #define EMAC_RX_DMA_START BIT(31) 188 189 /* Used in TX_CTL1*/ 190 #define EMAC_TX_MD BIT(1) 191 #define EMAC_TX_NEXT_FRM BIT(2) 192 #define EMAC_TX_TH_MASK GENMASK(8, 10) 193 #define EMAC_TX_TH_64 0 194 #define EMAC_TX_TH_128 (0x1 << 8) 195 #define EMAC_TX_TH_192 (0x2 << 8) 196 #define EMAC_TX_TH_256 (0x3 << 8) 197 #define EMAC_TX_DMA_EN BIT(30) 198 #define EMAC_TX_DMA_START BIT(31) 199 200 /* Used in RX_CTL0 */ 201 #define EMAC_RX_RECEIVER_EN BIT(31) 202 #define EMAC_RX_DO_CRC BIT(27) 203 #define EMAC_RX_FLOW_CTL_EN BIT(16) 204 205 /* Used in TX_CTL0 */ 206 #define EMAC_TX_TRANSMITTER_EN BIT(31) 207 208 /* Used in EMAC_TX_FLOW_CTL */ 209 #define EMAC_TX_FLOW_CTL_EN BIT(0) 210 211 /* Used in EMAC_INT_STA */ 212 #define EMAC_TX_INT BIT(0) 213 #define EMAC_TX_DMA_STOP_INT BIT(1) 214 #define EMAC_TX_BUF_UA_INT BIT(2) 215 #define EMAC_TX_TIMEOUT_INT BIT(3) 216 #define EMAC_TX_UNDERFLOW_INT BIT(4) 217 #define EMAC_TX_EARLY_INT BIT(5) 218 #define EMAC_RX_INT BIT(8) 219 #define EMAC_RX_BUF_UA_INT BIT(9) 220 #define EMAC_RX_DMA_STOP_INT BIT(10) 221 #define EMAC_RX_TIMEOUT_INT BIT(11) 222 #define EMAC_RX_OVERFLOW_INT BIT(12) 223 #define EMAC_RX_EARLY_INT BIT(13) 224 #define EMAC_RGMII_STA_INT BIT(16) 225 226 #define MAC_ADDR_TYPE_DST BIT(31) 227 228 /* H3 specific bits for EPHY */ 229 #define H3_EPHY_ADDR_SHIFT 20 230 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 231 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 232 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 233 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 234 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 235 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 236 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 237 238 /* H3/A64 specific bits */ 239 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 240 241 /* Generic system control EMAC_CLK bits */ 242 #define SYSCON_ETXDC_SHIFT 10 243 #define SYSCON_ERXDC_SHIFT 5 244 /* EMAC PHY Interface Type */ 245 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 246 #define SYSCON_ETCS_MASK GENMASK(1, 0) 247 #define SYSCON_ETCS_MII 0x0 248 #define SYSCON_ETCS_EXT_GMII 0x1 249 #define SYSCON_ETCS_INT_GMII 0x2 250 251 /* sun8i_dwmac_dma_reset() - reset the EMAC 252 * Called from stmmac via stmmac_dma_ops->reset 253 */ 254 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 255 { 256 writel(0, ioaddr + EMAC_RX_CTL1); 257 writel(0, ioaddr + EMAC_TX_CTL1); 258 writel(0, ioaddr + EMAC_RX_FRM_FLT); 259 writel(0, ioaddr + EMAC_RX_DESC_LIST); 260 writel(0, ioaddr + EMAC_TX_DESC_LIST); 261 writel(0, ioaddr + EMAC_INT_EN); 262 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 263 return 0; 264 } 265 266 /* sun8i_dwmac_dma_init() - initialize the EMAC 267 * Called from stmmac via stmmac_dma_ops->init 268 */ 269 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 270 struct stmmac_dma_cfg *dma_cfg, int atds) 271 { 272 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 273 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 274 } 275 276 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 277 struct stmmac_dma_cfg *dma_cfg, 278 u32 dma_rx_phy, u32 chan) 279 { 280 /* Write RX descriptors address */ 281 writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST); 282 } 283 284 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 285 struct stmmac_dma_cfg *dma_cfg, 286 u32 dma_tx_phy, u32 chan) 287 { 288 /* Write TX descriptors address */ 289 writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST); 290 } 291 292 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 293 * Called from stmmac_dma_ops->dump_regs 294 * Used for ethtool 295 */ 296 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 297 { 298 int i; 299 300 for (i = 0; i < 0xC8; i += 4) { 301 if (i == 0x32 || i == 0x3C) 302 continue; 303 reg_space[i / 4] = readl(ioaddr + i); 304 } 305 } 306 307 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 308 * Called from stmmac_ops->dump_regs 309 * Used for ethtool 310 */ 311 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 312 u32 *reg_space) 313 { 314 int i; 315 void __iomem *ioaddr = hw->pcsr; 316 317 for (i = 0; i < 0xC8; i += 4) { 318 if (i == 0x32 || i == 0x3C) 319 continue; 320 reg_space[i / 4] = readl(ioaddr + i); 321 } 322 } 323 324 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) 325 { 326 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 327 } 328 329 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 330 { 331 writel(0, ioaddr + EMAC_INT_EN); 332 } 333 334 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 335 { 336 u32 v; 337 338 v = readl(ioaddr + EMAC_TX_CTL1); 339 v |= EMAC_TX_DMA_START; 340 v |= EMAC_TX_DMA_EN; 341 writel(v, ioaddr + EMAC_TX_CTL1); 342 } 343 344 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 345 { 346 u32 v; 347 348 v = readl(ioaddr + EMAC_TX_CTL1); 349 v |= EMAC_TX_DMA_START; 350 v |= EMAC_TX_DMA_EN; 351 writel(v, ioaddr + EMAC_TX_CTL1); 352 } 353 354 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 355 { 356 u32 v; 357 358 v = readl(ioaddr + EMAC_TX_CTL1); 359 v &= ~EMAC_TX_DMA_EN; 360 writel(v, ioaddr + EMAC_TX_CTL1); 361 } 362 363 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 364 { 365 u32 v; 366 367 v = readl(ioaddr + EMAC_RX_CTL1); 368 v |= EMAC_RX_DMA_START; 369 v |= EMAC_RX_DMA_EN; 370 writel(v, ioaddr + EMAC_RX_CTL1); 371 } 372 373 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 374 { 375 u32 v; 376 377 v = readl(ioaddr + EMAC_RX_CTL1); 378 v &= ~EMAC_RX_DMA_EN; 379 writel(v, ioaddr + EMAC_RX_CTL1); 380 } 381 382 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 383 struct stmmac_extra_stats *x, u32 chan) 384 { 385 u32 v; 386 int ret = 0; 387 388 v = readl(ioaddr + EMAC_INT_STA); 389 390 if (v & EMAC_TX_INT) { 391 ret |= handle_tx; 392 x->tx_normal_irq_n++; 393 } 394 395 if (v & EMAC_TX_DMA_STOP_INT) 396 x->tx_process_stopped_irq++; 397 398 if (v & EMAC_TX_BUF_UA_INT) 399 x->tx_process_stopped_irq++; 400 401 if (v & EMAC_TX_TIMEOUT_INT) 402 ret |= tx_hard_error; 403 404 if (v & EMAC_TX_UNDERFLOW_INT) { 405 ret |= tx_hard_error; 406 x->tx_undeflow_irq++; 407 } 408 409 if (v & EMAC_TX_EARLY_INT) 410 x->tx_early_irq++; 411 412 if (v & EMAC_RX_INT) { 413 ret |= handle_rx; 414 x->rx_normal_irq_n++; 415 } 416 417 if (v & EMAC_RX_BUF_UA_INT) 418 x->rx_buf_unav_irq++; 419 420 if (v & EMAC_RX_DMA_STOP_INT) 421 x->rx_process_stopped_irq++; 422 423 if (v & EMAC_RX_TIMEOUT_INT) 424 ret |= tx_hard_error; 425 426 if (v & EMAC_RX_OVERFLOW_INT) { 427 ret |= tx_hard_error; 428 x->rx_overflow_irq++; 429 } 430 431 if (v & EMAC_RX_EARLY_INT) 432 x->rx_early_irq++; 433 434 if (v & EMAC_RGMII_STA_INT) 435 x->irq_rgmii_n++; 436 437 writel(v, ioaddr + EMAC_INT_STA); 438 439 return ret; 440 } 441 442 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 443 u32 channel, int fifosz, u8 qmode) 444 { 445 u32 v; 446 447 v = readl(ioaddr + EMAC_RX_CTL1); 448 if (mode == SF_DMA_MODE) { 449 v |= EMAC_RX_MD; 450 } else { 451 v &= ~EMAC_RX_MD; 452 v &= ~EMAC_RX_TH_MASK; 453 if (mode < 32) 454 v |= EMAC_RX_TH_32; 455 else if (mode < 64) 456 v |= EMAC_RX_TH_64; 457 else if (mode < 96) 458 v |= EMAC_RX_TH_96; 459 else if (mode < 128) 460 v |= EMAC_RX_TH_128; 461 } 462 writel(v, ioaddr + EMAC_RX_CTL1); 463 } 464 465 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 466 u32 channel, int fifosz, u8 qmode) 467 { 468 u32 v; 469 470 v = readl(ioaddr + EMAC_TX_CTL1); 471 if (mode == SF_DMA_MODE) { 472 v |= EMAC_TX_MD; 473 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 474 * comment is 475 * "Operating on second frame increase the performance 476 * especially when transmit store-and-forward is used." 477 */ 478 v |= EMAC_TX_NEXT_FRM; 479 } else { 480 v &= ~EMAC_TX_MD; 481 v &= ~EMAC_TX_TH_MASK; 482 if (mode < 64) 483 v |= EMAC_TX_TH_64; 484 else if (mode < 128) 485 v |= EMAC_TX_TH_128; 486 else if (mode < 192) 487 v |= EMAC_TX_TH_192; 488 else if (mode < 256) 489 v |= EMAC_TX_TH_256; 490 } 491 writel(v, ioaddr + EMAC_TX_CTL1); 492 } 493 494 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 495 .reset = sun8i_dwmac_dma_reset, 496 .init = sun8i_dwmac_dma_init, 497 .init_rx_chan = sun8i_dwmac_dma_init_rx, 498 .init_tx_chan = sun8i_dwmac_dma_init_tx, 499 .dump_regs = sun8i_dwmac_dump_regs, 500 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 501 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 502 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 503 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 504 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 505 .start_tx = sun8i_dwmac_dma_start_tx, 506 .stop_tx = sun8i_dwmac_dma_stop_tx, 507 .start_rx = sun8i_dwmac_dma_start_rx, 508 .stop_rx = sun8i_dwmac_dma_stop_rx, 509 .dma_interrupt = sun8i_dwmac_dma_interrupt, 510 }; 511 512 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 513 { 514 struct sunxi_priv_data *gmac = priv; 515 int ret; 516 517 if (gmac->regulator) { 518 ret = regulator_enable(gmac->regulator); 519 if (ret) { 520 dev_err(&pdev->dev, "Fail to enable regulator\n"); 521 return ret; 522 } 523 } 524 525 ret = clk_prepare_enable(gmac->tx_clk); 526 if (ret) { 527 if (gmac->regulator) 528 regulator_disable(gmac->regulator); 529 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 530 return ret; 531 } 532 533 return 0; 534 } 535 536 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 537 struct net_device *dev) 538 { 539 void __iomem *ioaddr = hw->pcsr; 540 u32 v; 541 542 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 543 writel(v, ioaddr + EMAC_BASIC_CTL1); 544 } 545 546 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 547 { 548 u32 t, r; 549 550 t = readl(ioaddr + EMAC_TX_CTL0); 551 r = readl(ioaddr + EMAC_RX_CTL0); 552 if (enable) { 553 t |= EMAC_TX_TRANSMITTER_EN; 554 r |= EMAC_RX_RECEIVER_EN; 555 } else { 556 t &= ~EMAC_TX_TRANSMITTER_EN; 557 r &= ~EMAC_RX_RECEIVER_EN; 558 } 559 writel(t, ioaddr + EMAC_TX_CTL0); 560 writel(r, ioaddr + EMAC_RX_CTL0); 561 } 562 563 /* Set MAC address at slot reg_n 564 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 565 * If addr is NULL, clear the slot 566 */ 567 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 568 unsigned char *addr, 569 unsigned int reg_n) 570 { 571 void __iomem *ioaddr = hw->pcsr; 572 u32 v; 573 574 if (!addr) { 575 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 576 return; 577 } 578 579 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 580 EMAC_MACADDR_LO(reg_n)); 581 if (reg_n > 0) { 582 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 583 v |= MAC_ADDR_TYPE_DST; 584 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 585 } 586 } 587 588 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 589 unsigned char *addr, 590 unsigned int reg_n) 591 { 592 void __iomem *ioaddr = hw->pcsr; 593 594 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 595 EMAC_MACADDR_LO(reg_n)); 596 } 597 598 /* caution this function must return non 0 to work */ 599 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 600 { 601 void __iomem *ioaddr = hw->pcsr; 602 u32 v; 603 604 v = readl(ioaddr + EMAC_RX_CTL0); 605 v |= EMAC_RX_DO_CRC; 606 writel(v, ioaddr + EMAC_RX_CTL0); 607 608 return 1; 609 } 610 611 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 612 struct net_device *dev) 613 { 614 void __iomem *ioaddr = hw->pcsr; 615 u32 v; 616 int i = 1; 617 struct netdev_hw_addr *ha; 618 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 619 620 v = EMAC_FRM_FLT_CTL; 621 622 if (dev->flags & IFF_PROMISC) { 623 v = EMAC_FRM_FLT_RXALL; 624 } else if (dev->flags & IFF_ALLMULTI) { 625 v |= EMAC_FRM_FLT_MULTICAST; 626 } else if (macaddrs <= hw->unicast_filter_entries) { 627 if (!netdev_mc_empty(dev)) { 628 netdev_for_each_mc_addr(ha, dev) { 629 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 630 i++; 631 } 632 } 633 if (!netdev_uc_empty(dev)) { 634 netdev_for_each_uc_addr(ha, dev) { 635 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 636 i++; 637 } 638 } 639 } else { 640 netdev_info(dev, "Too many address, switching to promiscuous\n"); 641 v = EMAC_FRM_FLT_RXALL; 642 } 643 644 /* Disable unused address filter slots */ 645 while (i < hw->unicast_filter_entries) 646 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 647 648 writel(v, ioaddr + EMAC_RX_FRM_FLT); 649 } 650 651 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 652 unsigned int duplex, unsigned int fc, 653 unsigned int pause_time, u32 tx_cnt) 654 { 655 void __iomem *ioaddr = hw->pcsr; 656 u32 v; 657 658 v = readl(ioaddr + EMAC_RX_CTL0); 659 if (fc == FLOW_AUTO) 660 v |= EMAC_RX_FLOW_CTL_EN; 661 else 662 v &= ~EMAC_RX_FLOW_CTL_EN; 663 writel(v, ioaddr + EMAC_RX_CTL0); 664 665 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 666 if (fc == FLOW_AUTO) 667 v |= EMAC_TX_FLOW_CTL_EN; 668 else 669 v &= ~EMAC_TX_FLOW_CTL_EN; 670 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 671 } 672 673 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 674 { 675 u32 v; 676 int err; 677 678 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 679 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 680 681 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 682 * need more if no cable plugged. 100ms seems OK 683 */ 684 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 685 !(v & 0x01), 100, 100000); 686 687 if (err) { 688 dev_err(priv->device, "EMAC reset timeout\n"); 689 return -EFAULT; 690 } 691 return 0; 692 } 693 694 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 695 static int get_ephy_nodes(struct stmmac_priv *priv) 696 { 697 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 698 struct device_node *mdio_mux, *iphynode; 699 struct device_node *mdio_internal; 700 int ret; 701 702 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 703 if (!mdio_mux) { 704 dev_err(priv->device, "Cannot get mdio-mux node\n"); 705 return -ENODEV; 706 } 707 708 mdio_internal = of_get_compatible_child(mdio_mux, 709 "allwinner,sun8i-h3-mdio-internal"); 710 of_node_put(mdio_mux); 711 if (!mdio_internal) { 712 dev_err(priv->device, "Cannot get internal_mdio node\n"); 713 return -ENODEV; 714 } 715 716 /* Seek for internal PHY */ 717 for_each_child_of_node(mdio_internal, iphynode) { 718 gmac->ephy_clk = of_clk_get(iphynode, 0); 719 if (IS_ERR(gmac->ephy_clk)) 720 continue; 721 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 722 if (IS_ERR(gmac->rst_ephy)) { 723 ret = PTR_ERR(gmac->rst_ephy); 724 if (ret == -EPROBE_DEFER) { 725 of_node_put(iphynode); 726 of_node_put(mdio_internal); 727 return ret; 728 } 729 continue; 730 } 731 dev_info(priv->device, "Found internal PHY node\n"); 732 of_node_put(iphynode); 733 of_node_put(mdio_internal); 734 return 0; 735 } 736 737 of_node_put(mdio_internal); 738 return -ENODEV; 739 } 740 741 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 742 { 743 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 744 int ret; 745 746 if (gmac->internal_phy_powered) { 747 dev_warn(priv->device, "Internal PHY already powered\n"); 748 return 0; 749 } 750 751 dev_info(priv->device, "Powering internal PHY\n"); 752 ret = clk_prepare_enable(gmac->ephy_clk); 753 if (ret) { 754 dev_err(priv->device, "Cannot enable internal PHY\n"); 755 return ret; 756 } 757 758 /* Make sure the EPHY is properly reseted, as U-Boot may leave 759 * it at deasserted state, and thus it may fail to reset EMAC. 760 */ 761 reset_control_assert(gmac->rst_ephy); 762 763 ret = reset_control_deassert(gmac->rst_ephy); 764 if (ret) { 765 dev_err(priv->device, "Cannot deassert internal phy\n"); 766 clk_disable_unprepare(gmac->ephy_clk); 767 return ret; 768 } 769 770 gmac->internal_phy_powered = true; 771 772 return 0; 773 } 774 775 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 776 { 777 if (!gmac->internal_phy_powered) 778 return 0; 779 780 clk_disable_unprepare(gmac->ephy_clk); 781 reset_control_assert(gmac->rst_ephy); 782 gmac->internal_phy_powered = false; 783 return 0; 784 } 785 786 /* MDIO multiplexing switch function 787 * This function is called by the mdio-mux layer when it thinks the mdio bus 788 * multiplexer needs to switch. 789 * 'current_child' is the current value of the mux register 790 * 'desired_child' is the value of the 'reg' property of the target child MDIO 791 * node. 792 * The first time this function is called, current_child == -1. 793 * If current_child == desired_child, then the mux is already set to the 794 * correct bus. 795 */ 796 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 797 void *data) 798 { 799 struct stmmac_priv *priv = data; 800 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 801 u32 reg, val; 802 int ret = 0; 803 bool need_power_ephy = false; 804 805 if (current_child ^ desired_child) { 806 regmap_field_read(gmac->regmap_field, ®); 807 switch (desired_child) { 808 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 809 dev_info(priv->device, "Switch mux to internal PHY"); 810 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 811 812 need_power_ephy = true; 813 break; 814 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 815 dev_info(priv->device, "Switch mux to external PHY"); 816 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 817 need_power_ephy = false; 818 break; 819 default: 820 dev_err(priv->device, "Invalid child ID %x\n", 821 desired_child); 822 return -EINVAL; 823 } 824 regmap_field_write(gmac->regmap_field, val); 825 if (need_power_ephy) { 826 ret = sun8i_dwmac_power_internal_phy(priv); 827 if (ret) 828 return ret; 829 } else { 830 sun8i_dwmac_unpower_internal_phy(gmac); 831 } 832 /* After changing syscon value, the MAC need reset or it will 833 * use the last value (and so the last PHY set). 834 */ 835 ret = sun8i_dwmac_reset(priv); 836 } 837 return ret; 838 } 839 840 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 841 { 842 int ret; 843 struct device_node *mdio_mux; 844 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 845 846 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 847 if (!mdio_mux) 848 return -ENODEV; 849 850 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 851 &gmac->mux_handle, priv, priv->mii); 852 return ret; 853 } 854 855 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 856 { 857 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 858 struct device_node *node = priv->device->of_node; 859 int ret; 860 u32 reg, val; 861 862 regmap_field_read(gmac->regmap_field, &val); 863 reg = gmac->variant->default_syscon_value; 864 if (reg != val) 865 dev_warn(priv->device, 866 "Current syscon value is not the default %x (expect %x)\n", 867 val, reg); 868 869 if (gmac->variant->soc_has_internal_phy) { 870 if (of_property_read_bool(node, "allwinner,leds-active-low")) 871 reg |= H3_EPHY_LED_POL; 872 else 873 reg &= ~H3_EPHY_LED_POL; 874 875 /* Force EPHY xtal frequency to 24MHz. */ 876 reg |= H3_EPHY_CLK_SEL; 877 878 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 879 if (ret < 0) { 880 dev_err(priv->device, "Could not parse MDIO addr\n"); 881 return ret; 882 } 883 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 884 * address. No need to mask it again. 885 */ 886 reg |= 1 << H3_EPHY_ADDR_SHIFT; 887 } 888 889 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 890 if (val % 100) { 891 dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 892 return -EINVAL; 893 } 894 val /= 100; 895 dev_dbg(priv->device, "set tx-delay to %x\n", val); 896 if (val <= gmac->variant->tx_delay_max) { 897 reg &= ~(gmac->variant->tx_delay_max << 898 SYSCON_ETXDC_SHIFT); 899 reg |= (val << SYSCON_ETXDC_SHIFT); 900 } else { 901 dev_err(priv->device, "Invalid TX clock delay: %d\n", 902 val); 903 return -EINVAL; 904 } 905 } 906 907 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 908 if (val % 100) { 909 dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 910 return -EINVAL; 911 } 912 val /= 100; 913 dev_dbg(priv->device, "set rx-delay to %x\n", val); 914 if (val <= gmac->variant->rx_delay_max) { 915 reg &= ~(gmac->variant->rx_delay_max << 916 SYSCON_ERXDC_SHIFT); 917 reg |= (val << SYSCON_ERXDC_SHIFT); 918 } else { 919 dev_err(priv->device, "Invalid RX clock delay: %d\n", 920 val); 921 return -EINVAL; 922 } 923 } 924 925 /* Clear interface mode bits */ 926 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 927 if (gmac->variant->support_rmii) 928 reg &= ~SYSCON_RMII_EN; 929 930 switch (priv->plat->interface) { 931 case PHY_INTERFACE_MODE_MII: 932 /* default */ 933 break; 934 case PHY_INTERFACE_MODE_RGMII: 935 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 936 break; 937 case PHY_INTERFACE_MODE_RMII: 938 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 939 break; 940 default: 941 dev_err(priv->device, "Unsupported interface mode: %s", 942 phy_modes(priv->plat->interface)); 943 return -EINVAL; 944 } 945 946 regmap_field_write(gmac->regmap_field, reg); 947 948 return 0; 949 } 950 951 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 952 { 953 u32 reg = gmac->variant->default_syscon_value; 954 955 regmap_field_write(gmac->regmap_field, reg); 956 } 957 958 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 959 { 960 struct sunxi_priv_data *gmac = priv; 961 962 if (gmac->variant->soc_has_internal_phy) { 963 /* sun8i_dwmac_exit could be called with mdiomux uninit */ 964 if (gmac->mux_handle) 965 mdio_mux_uninit(gmac->mux_handle); 966 if (gmac->internal_phy_powered) 967 sun8i_dwmac_unpower_internal_phy(gmac); 968 } 969 970 sun8i_dwmac_unset_syscon(gmac); 971 972 reset_control_put(gmac->rst_ephy); 973 974 clk_disable_unprepare(gmac->tx_clk); 975 976 if (gmac->regulator) 977 regulator_disable(gmac->regulator); 978 } 979 980 static const struct stmmac_ops sun8i_dwmac_ops = { 981 .core_init = sun8i_dwmac_core_init, 982 .set_mac = sun8i_dwmac_set_mac, 983 .dump_regs = sun8i_dwmac_dump_mac_regs, 984 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 985 .set_filter = sun8i_dwmac_set_filter, 986 .flow_ctrl = sun8i_dwmac_flow_ctrl, 987 .set_umac_addr = sun8i_dwmac_set_umac_addr, 988 .get_umac_addr = sun8i_dwmac_get_umac_addr, 989 }; 990 991 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 992 { 993 struct mac_device_info *mac; 994 struct stmmac_priv *priv = ppriv; 995 int ret; 996 997 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 998 if (!mac) 999 return NULL; 1000 1001 ret = sun8i_dwmac_set_syscon(priv); 1002 if (ret) 1003 return NULL; 1004 1005 mac->pcsr = priv->ioaddr; 1006 mac->mac = &sun8i_dwmac_ops; 1007 mac->dma = &sun8i_dwmac_dma_ops; 1008 1009 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1010 1011 /* The loopback bit seems to be re-set when link change 1012 * Simply mask it each time 1013 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1014 */ 1015 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1016 mac->link.speed10 = EMAC_SPEED_10; 1017 mac->link.speed100 = EMAC_SPEED_100; 1018 mac->link.speed1000 = EMAC_SPEED_1000; 1019 mac->link.duplex = EMAC_DUPLEX_FULL; 1020 mac->mii.addr = EMAC_MDIO_CMD; 1021 mac->mii.data = EMAC_MDIO_DATA; 1022 mac->mii.reg_shift = 4; 1023 mac->mii.reg_mask = GENMASK(8, 4); 1024 mac->mii.addr_shift = 12; 1025 mac->mii.addr_mask = GENMASK(16, 12); 1026 mac->mii.clk_csr_shift = 20; 1027 mac->mii.clk_csr_mask = GENMASK(22, 20); 1028 mac->unicast_filter_entries = 8; 1029 1030 /* Synopsys Id is not available */ 1031 priv->synopsys_id = 0; 1032 1033 return mac; 1034 } 1035 1036 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1037 { 1038 struct device_node *syscon_node; 1039 struct platform_device *syscon_pdev; 1040 struct regmap *regmap = NULL; 1041 1042 syscon_node = of_parse_phandle(node, "syscon", 0); 1043 if (!syscon_node) 1044 return ERR_PTR(-ENODEV); 1045 1046 syscon_pdev = of_find_device_by_node(syscon_node); 1047 if (!syscon_pdev) { 1048 /* platform device might not be probed yet */ 1049 regmap = ERR_PTR(-EPROBE_DEFER); 1050 goto out_put_node; 1051 } 1052 1053 /* If no regmap is found then the other device driver is at fault */ 1054 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1055 if (!regmap) 1056 regmap = ERR_PTR(-EINVAL); 1057 1058 platform_device_put(syscon_pdev); 1059 out_put_node: 1060 of_node_put(syscon_node); 1061 return regmap; 1062 } 1063 1064 static int sun8i_dwmac_probe(struct platform_device *pdev) 1065 { 1066 struct plat_stmmacenet_data *plat_dat; 1067 struct stmmac_resources stmmac_res; 1068 struct sunxi_priv_data *gmac; 1069 struct device *dev = &pdev->dev; 1070 int ret; 1071 struct stmmac_priv *priv; 1072 struct net_device *ndev; 1073 struct regmap *regmap; 1074 1075 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1076 if (ret) 1077 return ret; 1078 1079 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1080 if (IS_ERR(plat_dat)) 1081 return PTR_ERR(plat_dat); 1082 1083 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1084 if (!gmac) 1085 return -ENOMEM; 1086 1087 gmac->variant = of_device_get_match_data(&pdev->dev); 1088 if (!gmac->variant) { 1089 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1090 return -EINVAL; 1091 } 1092 1093 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1094 if (IS_ERR(gmac->tx_clk)) { 1095 dev_err(dev, "Could not get TX clock\n"); 1096 return PTR_ERR(gmac->tx_clk); 1097 } 1098 1099 /* Optional regulator for PHY */ 1100 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1101 if (IS_ERR(gmac->regulator)) { 1102 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1103 return -EPROBE_DEFER; 1104 dev_info(dev, "No regulator found\n"); 1105 gmac->regulator = NULL; 1106 } 1107 1108 /* The "GMAC clock control" register might be located in the 1109 * CCU address range (on the R40), or the system control address 1110 * range (on most other sun8i and later SoCs). 1111 * 1112 * The former controls most if not all clocks in the SoC. The 1113 * latter has an SoC identification register, and on some SoCs, 1114 * controls to map device specific SRAM to either the intended 1115 * peripheral, or the CPU address space. 1116 * 1117 * In either case, there should be a coordinated and restricted 1118 * method of accessing the register needed here. This is done by 1119 * having the device export a custom regmap, instead of a generic 1120 * syscon, which grants all access to all registers. 1121 * 1122 * To support old device trees, we fall back to using the syscon 1123 * interface if possible. 1124 */ 1125 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1126 if (IS_ERR(regmap)) 1127 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1128 "syscon"); 1129 if (IS_ERR(regmap)) { 1130 ret = PTR_ERR(regmap); 1131 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1132 return ret; 1133 } 1134 1135 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1136 *gmac->variant->syscon_field); 1137 if (IS_ERR(gmac->regmap_field)) { 1138 ret = PTR_ERR(gmac->regmap_field); 1139 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1140 return ret; 1141 } 1142 1143 ret = of_get_phy_mode(dev->of_node); 1144 if (ret < 0) 1145 return -EINVAL; 1146 plat_dat->interface = ret; 1147 1148 /* platform data specifying hardware features and callbacks. 1149 * hardware features were copied from Allwinner drivers. 1150 */ 1151 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1152 plat_dat->tx_coe = 1; 1153 plat_dat->has_sun8i = true; 1154 plat_dat->bsp_priv = gmac; 1155 plat_dat->init = sun8i_dwmac_init; 1156 plat_dat->exit = sun8i_dwmac_exit; 1157 plat_dat->setup = sun8i_dwmac_setup; 1158 1159 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1160 if (ret) 1161 return ret; 1162 1163 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1164 if (ret) 1165 goto dwmac_exit; 1166 1167 ndev = dev_get_drvdata(&pdev->dev); 1168 priv = netdev_priv(ndev); 1169 /* The mux must be registered after parent MDIO 1170 * so after stmmac_dvr_probe() 1171 */ 1172 if (gmac->variant->soc_has_internal_phy) { 1173 ret = get_ephy_nodes(priv); 1174 if (ret) 1175 goto dwmac_exit; 1176 ret = sun8i_dwmac_register_mdio_mux(priv); 1177 if (ret) { 1178 dev_err(&pdev->dev, "Failed to register mux\n"); 1179 goto dwmac_mux; 1180 } 1181 } else { 1182 ret = sun8i_dwmac_reset(priv); 1183 if (ret) 1184 goto dwmac_exit; 1185 } 1186 1187 return ret; 1188 dwmac_mux: 1189 sun8i_dwmac_unset_syscon(gmac); 1190 dwmac_exit: 1191 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); 1192 return ret; 1193 } 1194 1195 static const struct of_device_id sun8i_dwmac_match[] = { 1196 { .compatible = "allwinner,sun8i-h3-emac", 1197 .data = &emac_variant_h3 }, 1198 { .compatible = "allwinner,sun8i-v3s-emac", 1199 .data = &emac_variant_v3s }, 1200 { .compatible = "allwinner,sun8i-a83t-emac", 1201 .data = &emac_variant_a83t }, 1202 { .compatible = "allwinner,sun8i-r40-gmac", 1203 .data = &emac_variant_r40 }, 1204 { .compatible = "allwinner,sun50i-a64-emac", 1205 .data = &emac_variant_a64 }, 1206 { } 1207 }; 1208 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1209 1210 static struct platform_driver sun8i_dwmac_driver = { 1211 .probe = sun8i_dwmac_probe, 1212 .remove = stmmac_pltfr_remove, 1213 .driver = { 1214 .name = "dwmac-sun8i", 1215 .pm = &stmmac_pltfr_pm_ops, 1216 .of_match_table = sun8i_dwmac_match, 1217 }, 1218 }; 1219 module_platform_driver(sun8i_dwmac_driver); 1220 1221 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1222 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1223 MODULE_LICENSE("GPL"); 1224