1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/stmmac.h> 22 23 #include "stmmac.h" 24 #include "stmmac_platform.h" 25 26 /* General notes on dwmac-sun8i: 27 * Locking: no locking is necessary in this file because all necessary locking 28 * is done in the "stmmac files" 29 */ 30 31 /* struct emac_variant - Describe dwmac-sun8i hardware variant 32 * @default_syscon_value: The default value of the EMAC register in syscon 33 * This value is used for disabling properly EMAC 34 * and used as a good starting value in case of the 35 * boot process(uboot) leave some stuff. 36 * @syscon_field reg_field for the syscon's gmac register 37 * @soc_has_internal_phy: Does the MAC embed an internal PHY 38 * @support_mii: Does the MAC handle MII 39 * @support_rmii: Does the MAC handle RMII 40 * @support_rgmii: Does the MAC handle RGMII 41 * 42 * @rx_delay_max: Maximum raw value for RX delay chain 43 * @tx_delay_max: Maximum raw value for TX delay chain 44 * These two also indicate the bitmask for 45 * the RX and TX delay chain registers. A 46 * value of zero indicates this is not supported. 47 */ 48 struct emac_variant { 49 u32 default_syscon_value; 50 const struct reg_field *syscon_field; 51 bool soc_has_internal_phy; 52 bool support_mii; 53 bool support_rmii; 54 bool support_rgmii; 55 u8 rx_delay_max; 56 u8 tx_delay_max; 57 }; 58 59 /* struct sunxi_priv_data - hold all sunxi private data 60 * @tx_clk: reference to MAC TX clock 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @mux_handle: Internal pointer used by mdio-mux lib 68 */ 69 struct sunxi_priv_data { 70 struct clk *tx_clk; 71 struct clk *ephy_clk; 72 struct regulator *regulator; 73 struct reset_control *rst_ephy; 74 const struct emac_variant *variant; 75 struct regmap_field *regmap_field; 76 bool internal_phy_powered; 77 void *mux_handle; 78 }; 79 80 /* EMAC clock register @ 0x30 in the "system control" address range */ 81 static const struct reg_field sun8i_syscon_reg_field = { 82 .reg = 0x30, 83 .lsb = 0, 84 .msb = 31, 85 }; 86 87 /* EMAC clock register @ 0x164 in the CCU address range */ 88 static const struct reg_field sun8i_ccu_reg_field = { 89 .reg = 0x164, 90 .lsb = 0, 91 .msb = 31, 92 }; 93 94 static const struct emac_variant emac_variant_h3 = { 95 .default_syscon_value = 0x58000, 96 .syscon_field = &sun8i_syscon_reg_field, 97 .soc_has_internal_phy = true, 98 .support_mii = true, 99 .support_rmii = true, 100 .support_rgmii = true, 101 .rx_delay_max = 31, 102 .tx_delay_max = 7, 103 }; 104 105 static const struct emac_variant emac_variant_v3s = { 106 .default_syscon_value = 0x38000, 107 .syscon_field = &sun8i_syscon_reg_field, 108 .soc_has_internal_phy = true, 109 .support_mii = true 110 }; 111 112 static const struct emac_variant emac_variant_a83t = { 113 .default_syscon_value = 0, 114 .syscon_field = &sun8i_syscon_reg_field, 115 .soc_has_internal_phy = false, 116 .support_mii = true, 117 .support_rgmii = true, 118 .rx_delay_max = 31, 119 .tx_delay_max = 7, 120 }; 121 122 static const struct emac_variant emac_variant_r40 = { 123 .default_syscon_value = 0, 124 .syscon_field = &sun8i_ccu_reg_field, 125 .support_mii = true, 126 .support_rgmii = true, 127 .rx_delay_max = 7, 128 }; 129 130 static const struct emac_variant emac_variant_a64 = { 131 .default_syscon_value = 0, 132 .syscon_field = &sun8i_syscon_reg_field, 133 .soc_has_internal_phy = false, 134 .support_mii = true, 135 .support_rmii = true, 136 .support_rgmii = true, 137 .rx_delay_max = 31, 138 .tx_delay_max = 7, 139 }; 140 141 static const struct emac_variant emac_variant_h6 = { 142 .default_syscon_value = 0x50000, 143 .syscon_field = &sun8i_syscon_reg_field, 144 /* The "Internal PHY" of H6 is not on the die. It's on the 145 * co-packaged AC200 chip instead. 146 */ 147 .soc_has_internal_phy = false, 148 .support_mii = true, 149 .support_rmii = true, 150 .support_rgmii = true, 151 .rx_delay_max = 31, 152 .tx_delay_max = 7, 153 }; 154 155 #define EMAC_BASIC_CTL0 0x00 156 #define EMAC_BASIC_CTL1 0x04 157 #define EMAC_INT_STA 0x08 158 #define EMAC_INT_EN 0x0C 159 #define EMAC_TX_CTL0 0x10 160 #define EMAC_TX_CTL1 0x14 161 #define EMAC_TX_FLOW_CTL 0x1C 162 #define EMAC_TX_DESC_LIST 0x20 163 #define EMAC_RX_CTL0 0x24 164 #define EMAC_RX_CTL1 0x28 165 #define EMAC_RX_DESC_LIST 0x34 166 #define EMAC_RX_FRM_FLT 0x38 167 #define EMAC_MDIO_CMD 0x48 168 #define EMAC_MDIO_DATA 0x4C 169 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 170 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 171 #define EMAC_TX_DMA_STA 0xB0 172 #define EMAC_TX_CUR_DESC 0xB4 173 #define EMAC_TX_CUR_BUF 0xB8 174 #define EMAC_RX_DMA_STA 0xC0 175 #define EMAC_RX_CUR_DESC 0xC4 176 #define EMAC_RX_CUR_BUF 0xC8 177 178 /* Use in EMAC_BASIC_CTL0 */ 179 #define EMAC_DUPLEX_FULL BIT(0) 180 #define EMAC_LOOPBACK BIT(1) 181 #define EMAC_SPEED_1000 0 182 #define EMAC_SPEED_100 (0x03 << 2) 183 #define EMAC_SPEED_10 (0x02 << 2) 184 185 /* Use in EMAC_BASIC_CTL1 */ 186 #define EMAC_BURSTLEN_SHIFT 24 187 188 /* Used in EMAC_RX_FRM_FLT */ 189 #define EMAC_FRM_FLT_RXALL BIT(0) 190 #define EMAC_FRM_FLT_CTL BIT(13) 191 #define EMAC_FRM_FLT_MULTICAST BIT(16) 192 193 /* Used in RX_CTL1*/ 194 #define EMAC_RX_MD BIT(1) 195 #define EMAC_RX_TH_MASK GENMASK(5, 4) 196 #define EMAC_RX_TH_32 0 197 #define EMAC_RX_TH_64 (0x1 << 4) 198 #define EMAC_RX_TH_96 (0x2 << 4) 199 #define EMAC_RX_TH_128 (0x3 << 4) 200 #define EMAC_RX_DMA_EN BIT(30) 201 #define EMAC_RX_DMA_START BIT(31) 202 203 /* Used in TX_CTL1*/ 204 #define EMAC_TX_MD BIT(1) 205 #define EMAC_TX_NEXT_FRM BIT(2) 206 #define EMAC_TX_TH_MASK GENMASK(10, 8) 207 #define EMAC_TX_TH_64 0 208 #define EMAC_TX_TH_128 (0x1 << 8) 209 #define EMAC_TX_TH_192 (0x2 << 8) 210 #define EMAC_TX_TH_256 (0x3 << 8) 211 #define EMAC_TX_DMA_EN BIT(30) 212 #define EMAC_TX_DMA_START BIT(31) 213 214 /* Used in RX_CTL0 */ 215 #define EMAC_RX_RECEIVER_EN BIT(31) 216 #define EMAC_RX_DO_CRC BIT(27) 217 #define EMAC_RX_FLOW_CTL_EN BIT(16) 218 219 /* Used in TX_CTL0 */ 220 #define EMAC_TX_TRANSMITTER_EN BIT(31) 221 222 /* Used in EMAC_TX_FLOW_CTL */ 223 #define EMAC_TX_FLOW_CTL_EN BIT(0) 224 225 /* Used in EMAC_INT_STA */ 226 #define EMAC_TX_INT BIT(0) 227 #define EMAC_TX_DMA_STOP_INT BIT(1) 228 #define EMAC_TX_BUF_UA_INT BIT(2) 229 #define EMAC_TX_TIMEOUT_INT BIT(3) 230 #define EMAC_TX_UNDERFLOW_INT BIT(4) 231 #define EMAC_TX_EARLY_INT BIT(5) 232 #define EMAC_RX_INT BIT(8) 233 #define EMAC_RX_BUF_UA_INT BIT(9) 234 #define EMAC_RX_DMA_STOP_INT BIT(10) 235 #define EMAC_RX_TIMEOUT_INT BIT(11) 236 #define EMAC_RX_OVERFLOW_INT BIT(12) 237 #define EMAC_RX_EARLY_INT BIT(13) 238 #define EMAC_RGMII_STA_INT BIT(16) 239 240 #define MAC_ADDR_TYPE_DST BIT(31) 241 242 /* H3 specific bits for EPHY */ 243 #define H3_EPHY_ADDR_SHIFT 20 244 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 245 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 246 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 247 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 248 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 249 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 250 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 251 252 /* H3/A64 specific bits */ 253 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 254 255 /* Generic system control EMAC_CLK bits */ 256 #define SYSCON_ETXDC_SHIFT 10 257 #define SYSCON_ERXDC_SHIFT 5 258 /* EMAC PHY Interface Type */ 259 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 260 #define SYSCON_ETCS_MASK GENMASK(1, 0) 261 #define SYSCON_ETCS_MII 0x0 262 #define SYSCON_ETCS_EXT_GMII 0x1 263 #define SYSCON_ETCS_INT_GMII 0x2 264 265 /* sun8i_dwmac_dma_reset() - reset the EMAC 266 * Called from stmmac via stmmac_dma_ops->reset 267 */ 268 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 269 { 270 writel(0, ioaddr + EMAC_RX_CTL1); 271 writel(0, ioaddr + EMAC_TX_CTL1); 272 writel(0, ioaddr + EMAC_RX_FRM_FLT); 273 writel(0, ioaddr + EMAC_RX_DESC_LIST); 274 writel(0, ioaddr + EMAC_TX_DESC_LIST); 275 writel(0, ioaddr + EMAC_INT_EN); 276 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 277 return 0; 278 } 279 280 /* sun8i_dwmac_dma_init() - initialize the EMAC 281 * Called from stmmac via stmmac_dma_ops->init 282 */ 283 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 284 struct stmmac_dma_cfg *dma_cfg, int atds) 285 { 286 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 287 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 288 } 289 290 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 291 struct stmmac_dma_cfg *dma_cfg, 292 dma_addr_t dma_rx_phy, u32 chan) 293 { 294 /* Write RX descriptors address */ 295 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 296 } 297 298 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 299 struct stmmac_dma_cfg *dma_cfg, 300 dma_addr_t dma_tx_phy, u32 chan) 301 { 302 /* Write TX descriptors address */ 303 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 304 } 305 306 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 307 * Called from stmmac_dma_ops->dump_regs 308 * Used for ethtool 309 */ 310 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 311 { 312 int i; 313 314 for (i = 0; i < 0xC8; i += 4) { 315 if (i == 0x32 || i == 0x3C) 316 continue; 317 reg_space[i / 4] = readl(ioaddr + i); 318 } 319 } 320 321 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 322 * Called from stmmac_ops->dump_regs 323 * Used for ethtool 324 */ 325 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 326 u32 *reg_space) 327 { 328 int i; 329 void __iomem *ioaddr = hw->pcsr; 330 331 for (i = 0; i < 0xC8; i += 4) { 332 if (i == 0x32 || i == 0x3C) 333 continue; 334 reg_space[i / 4] = readl(ioaddr + i); 335 } 336 } 337 338 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, 339 bool rx, bool tx) 340 { 341 u32 value = readl(ioaddr + EMAC_INT_EN); 342 343 if (rx) 344 value |= EMAC_RX_INT; 345 if (tx) 346 value |= EMAC_TX_INT; 347 348 writel(value, ioaddr + EMAC_INT_EN); 349 } 350 351 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, 352 bool rx, bool tx) 353 { 354 u32 value = readl(ioaddr + EMAC_INT_EN); 355 356 if (rx) 357 value &= ~EMAC_RX_INT; 358 if (tx) 359 value &= ~EMAC_TX_INT; 360 361 writel(value, ioaddr + EMAC_INT_EN); 362 } 363 364 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 365 { 366 u32 v; 367 368 v = readl(ioaddr + EMAC_TX_CTL1); 369 v |= EMAC_TX_DMA_START; 370 v |= EMAC_TX_DMA_EN; 371 writel(v, ioaddr + EMAC_TX_CTL1); 372 } 373 374 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 375 { 376 u32 v; 377 378 v = readl(ioaddr + EMAC_TX_CTL1); 379 v |= EMAC_TX_DMA_START; 380 v |= EMAC_TX_DMA_EN; 381 writel(v, ioaddr + EMAC_TX_CTL1); 382 } 383 384 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 385 { 386 u32 v; 387 388 v = readl(ioaddr + EMAC_TX_CTL1); 389 v &= ~EMAC_TX_DMA_EN; 390 writel(v, ioaddr + EMAC_TX_CTL1); 391 } 392 393 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 394 { 395 u32 v; 396 397 v = readl(ioaddr + EMAC_RX_CTL1); 398 v |= EMAC_RX_DMA_START; 399 v |= EMAC_RX_DMA_EN; 400 writel(v, ioaddr + EMAC_RX_CTL1); 401 } 402 403 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 404 { 405 u32 v; 406 407 v = readl(ioaddr + EMAC_RX_CTL1); 408 v &= ~EMAC_RX_DMA_EN; 409 writel(v, ioaddr + EMAC_RX_CTL1); 410 } 411 412 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 413 struct stmmac_extra_stats *x, u32 chan) 414 { 415 u32 v; 416 int ret = 0; 417 418 v = readl(ioaddr + EMAC_INT_STA); 419 420 if (v & EMAC_TX_INT) { 421 ret |= handle_tx; 422 x->tx_normal_irq_n++; 423 } 424 425 if (v & EMAC_TX_DMA_STOP_INT) 426 x->tx_process_stopped_irq++; 427 428 if (v & EMAC_TX_BUF_UA_INT) 429 x->tx_process_stopped_irq++; 430 431 if (v & EMAC_TX_TIMEOUT_INT) 432 ret |= tx_hard_error; 433 434 if (v & EMAC_TX_UNDERFLOW_INT) { 435 ret |= tx_hard_error; 436 x->tx_undeflow_irq++; 437 } 438 439 if (v & EMAC_TX_EARLY_INT) 440 x->tx_early_irq++; 441 442 if (v & EMAC_RX_INT) { 443 ret |= handle_rx; 444 x->rx_normal_irq_n++; 445 } 446 447 if (v & EMAC_RX_BUF_UA_INT) 448 x->rx_buf_unav_irq++; 449 450 if (v & EMAC_RX_DMA_STOP_INT) 451 x->rx_process_stopped_irq++; 452 453 if (v & EMAC_RX_TIMEOUT_INT) 454 ret |= tx_hard_error; 455 456 if (v & EMAC_RX_OVERFLOW_INT) { 457 ret |= tx_hard_error; 458 x->rx_overflow_irq++; 459 } 460 461 if (v & EMAC_RX_EARLY_INT) 462 x->rx_early_irq++; 463 464 if (v & EMAC_RGMII_STA_INT) 465 x->irq_rgmii_n++; 466 467 writel(v, ioaddr + EMAC_INT_STA); 468 469 return ret; 470 } 471 472 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 473 u32 channel, int fifosz, u8 qmode) 474 { 475 u32 v; 476 477 v = readl(ioaddr + EMAC_RX_CTL1); 478 if (mode == SF_DMA_MODE) { 479 v |= EMAC_RX_MD; 480 } else { 481 v &= ~EMAC_RX_MD; 482 v &= ~EMAC_RX_TH_MASK; 483 if (mode < 32) 484 v |= EMAC_RX_TH_32; 485 else if (mode < 64) 486 v |= EMAC_RX_TH_64; 487 else if (mode < 96) 488 v |= EMAC_RX_TH_96; 489 else if (mode < 128) 490 v |= EMAC_RX_TH_128; 491 } 492 writel(v, ioaddr + EMAC_RX_CTL1); 493 } 494 495 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 496 u32 channel, int fifosz, u8 qmode) 497 { 498 u32 v; 499 500 v = readl(ioaddr + EMAC_TX_CTL1); 501 if (mode == SF_DMA_MODE) { 502 v |= EMAC_TX_MD; 503 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 504 * comment is 505 * "Operating on second frame increase the performance 506 * especially when transmit store-and-forward is used." 507 */ 508 v |= EMAC_TX_NEXT_FRM; 509 } else { 510 v &= ~EMAC_TX_MD; 511 v &= ~EMAC_TX_TH_MASK; 512 if (mode < 64) 513 v |= EMAC_TX_TH_64; 514 else if (mode < 128) 515 v |= EMAC_TX_TH_128; 516 else if (mode < 192) 517 v |= EMAC_TX_TH_192; 518 else if (mode < 256) 519 v |= EMAC_TX_TH_256; 520 } 521 writel(v, ioaddr + EMAC_TX_CTL1); 522 } 523 524 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 525 .reset = sun8i_dwmac_dma_reset, 526 .init = sun8i_dwmac_dma_init, 527 .init_rx_chan = sun8i_dwmac_dma_init_rx, 528 .init_tx_chan = sun8i_dwmac_dma_init_tx, 529 .dump_regs = sun8i_dwmac_dump_regs, 530 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 531 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 532 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 533 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 534 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 535 .start_tx = sun8i_dwmac_dma_start_tx, 536 .stop_tx = sun8i_dwmac_dma_stop_tx, 537 .start_rx = sun8i_dwmac_dma_start_rx, 538 .stop_rx = sun8i_dwmac_dma_stop_rx, 539 .dma_interrupt = sun8i_dwmac_dma_interrupt, 540 }; 541 542 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 543 { 544 struct sunxi_priv_data *gmac = priv; 545 int ret; 546 547 if (gmac->regulator) { 548 ret = regulator_enable(gmac->regulator); 549 if (ret) { 550 dev_err(&pdev->dev, "Fail to enable regulator\n"); 551 return ret; 552 } 553 } 554 555 ret = clk_prepare_enable(gmac->tx_clk); 556 if (ret) { 557 if (gmac->regulator) 558 regulator_disable(gmac->regulator); 559 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 560 return ret; 561 } 562 563 return 0; 564 } 565 566 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 567 struct net_device *dev) 568 { 569 void __iomem *ioaddr = hw->pcsr; 570 u32 v; 571 572 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 573 writel(v, ioaddr + EMAC_BASIC_CTL1); 574 } 575 576 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 577 { 578 u32 t, r; 579 580 t = readl(ioaddr + EMAC_TX_CTL0); 581 r = readl(ioaddr + EMAC_RX_CTL0); 582 if (enable) { 583 t |= EMAC_TX_TRANSMITTER_EN; 584 r |= EMAC_RX_RECEIVER_EN; 585 } else { 586 t &= ~EMAC_TX_TRANSMITTER_EN; 587 r &= ~EMAC_RX_RECEIVER_EN; 588 } 589 writel(t, ioaddr + EMAC_TX_CTL0); 590 writel(r, ioaddr + EMAC_RX_CTL0); 591 } 592 593 /* Set MAC address at slot reg_n 594 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 595 * If addr is NULL, clear the slot 596 */ 597 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 598 unsigned char *addr, 599 unsigned int reg_n) 600 { 601 void __iomem *ioaddr = hw->pcsr; 602 u32 v; 603 604 if (!addr) { 605 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 606 return; 607 } 608 609 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 610 EMAC_MACADDR_LO(reg_n)); 611 if (reg_n > 0) { 612 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 613 v |= MAC_ADDR_TYPE_DST; 614 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 615 } 616 } 617 618 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 619 unsigned char *addr, 620 unsigned int reg_n) 621 { 622 void __iomem *ioaddr = hw->pcsr; 623 624 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 625 EMAC_MACADDR_LO(reg_n)); 626 } 627 628 /* caution this function must return non 0 to work */ 629 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 630 { 631 void __iomem *ioaddr = hw->pcsr; 632 u32 v; 633 634 v = readl(ioaddr + EMAC_RX_CTL0); 635 v |= EMAC_RX_DO_CRC; 636 writel(v, ioaddr + EMAC_RX_CTL0); 637 638 return 1; 639 } 640 641 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 642 struct net_device *dev) 643 { 644 void __iomem *ioaddr = hw->pcsr; 645 u32 v; 646 int i = 1; 647 struct netdev_hw_addr *ha; 648 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 649 650 v = EMAC_FRM_FLT_CTL; 651 652 if (dev->flags & IFF_PROMISC) { 653 v = EMAC_FRM_FLT_RXALL; 654 } else if (dev->flags & IFF_ALLMULTI) { 655 v |= EMAC_FRM_FLT_MULTICAST; 656 } else if (macaddrs <= hw->unicast_filter_entries) { 657 if (!netdev_mc_empty(dev)) { 658 netdev_for_each_mc_addr(ha, dev) { 659 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 660 i++; 661 } 662 } 663 if (!netdev_uc_empty(dev)) { 664 netdev_for_each_uc_addr(ha, dev) { 665 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 666 i++; 667 } 668 } 669 } else { 670 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 671 netdev_info(dev, "Too many address, switching to promiscuous\n"); 672 v = EMAC_FRM_FLT_RXALL; 673 } 674 675 /* Disable unused address filter slots */ 676 while (i < hw->unicast_filter_entries) 677 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 678 679 writel(v, ioaddr + EMAC_RX_FRM_FLT); 680 } 681 682 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 683 unsigned int duplex, unsigned int fc, 684 unsigned int pause_time, u32 tx_cnt) 685 { 686 void __iomem *ioaddr = hw->pcsr; 687 u32 v; 688 689 v = readl(ioaddr + EMAC_RX_CTL0); 690 if (fc == FLOW_AUTO) 691 v |= EMAC_RX_FLOW_CTL_EN; 692 else 693 v &= ~EMAC_RX_FLOW_CTL_EN; 694 writel(v, ioaddr + EMAC_RX_CTL0); 695 696 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 697 if (fc == FLOW_AUTO) 698 v |= EMAC_TX_FLOW_CTL_EN; 699 else 700 v &= ~EMAC_TX_FLOW_CTL_EN; 701 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 702 } 703 704 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 705 { 706 u32 v; 707 int err; 708 709 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 710 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 711 712 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 713 * need more if no cable plugged. 100ms seems OK 714 */ 715 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 716 !(v & 0x01), 100, 100000); 717 718 if (err) { 719 dev_err(priv->device, "EMAC reset timeout\n"); 720 return -EFAULT; 721 } 722 return 0; 723 } 724 725 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 726 static int get_ephy_nodes(struct stmmac_priv *priv) 727 { 728 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 729 struct device_node *mdio_mux, *iphynode; 730 struct device_node *mdio_internal; 731 int ret; 732 733 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 734 if (!mdio_mux) { 735 dev_err(priv->device, "Cannot get mdio-mux node\n"); 736 return -ENODEV; 737 } 738 739 mdio_internal = of_get_compatible_child(mdio_mux, 740 "allwinner,sun8i-h3-mdio-internal"); 741 of_node_put(mdio_mux); 742 if (!mdio_internal) { 743 dev_err(priv->device, "Cannot get internal_mdio node\n"); 744 return -ENODEV; 745 } 746 747 /* Seek for internal PHY */ 748 for_each_child_of_node(mdio_internal, iphynode) { 749 gmac->ephy_clk = of_clk_get(iphynode, 0); 750 if (IS_ERR(gmac->ephy_clk)) 751 continue; 752 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 753 if (IS_ERR(gmac->rst_ephy)) { 754 ret = PTR_ERR(gmac->rst_ephy); 755 if (ret == -EPROBE_DEFER) { 756 of_node_put(iphynode); 757 of_node_put(mdio_internal); 758 return ret; 759 } 760 continue; 761 } 762 dev_info(priv->device, "Found internal PHY node\n"); 763 of_node_put(iphynode); 764 of_node_put(mdio_internal); 765 return 0; 766 } 767 768 of_node_put(mdio_internal); 769 return -ENODEV; 770 } 771 772 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 773 { 774 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 775 int ret; 776 777 if (gmac->internal_phy_powered) { 778 dev_warn(priv->device, "Internal PHY already powered\n"); 779 return 0; 780 } 781 782 dev_info(priv->device, "Powering internal PHY\n"); 783 ret = clk_prepare_enable(gmac->ephy_clk); 784 if (ret) { 785 dev_err(priv->device, "Cannot enable internal PHY\n"); 786 return ret; 787 } 788 789 /* Make sure the EPHY is properly reseted, as U-Boot may leave 790 * it at deasserted state, and thus it may fail to reset EMAC. 791 */ 792 reset_control_assert(gmac->rst_ephy); 793 794 ret = reset_control_deassert(gmac->rst_ephy); 795 if (ret) { 796 dev_err(priv->device, "Cannot deassert internal phy\n"); 797 clk_disable_unprepare(gmac->ephy_clk); 798 return ret; 799 } 800 801 gmac->internal_phy_powered = true; 802 803 return 0; 804 } 805 806 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 807 { 808 if (!gmac->internal_phy_powered) 809 return 0; 810 811 clk_disable_unprepare(gmac->ephy_clk); 812 reset_control_assert(gmac->rst_ephy); 813 gmac->internal_phy_powered = false; 814 return 0; 815 } 816 817 /* MDIO multiplexing switch function 818 * This function is called by the mdio-mux layer when it thinks the mdio bus 819 * multiplexer needs to switch. 820 * 'current_child' is the current value of the mux register 821 * 'desired_child' is the value of the 'reg' property of the target child MDIO 822 * node. 823 * The first time this function is called, current_child == -1. 824 * If current_child == desired_child, then the mux is already set to the 825 * correct bus. 826 */ 827 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 828 void *data) 829 { 830 struct stmmac_priv *priv = data; 831 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 832 u32 reg, val; 833 int ret = 0; 834 bool need_power_ephy = false; 835 836 if (current_child ^ desired_child) { 837 regmap_field_read(gmac->regmap_field, ®); 838 switch (desired_child) { 839 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 840 dev_info(priv->device, "Switch mux to internal PHY"); 841 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 842 843 need_power_ephy = true; 844 break; 845 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 846 dev_info(priv->device, "Switch mux to external PHY"); 847 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 848 need_power_ephy = false; 849 break; 850 default: 851 dev_err(priv->device, "Invalid child ID %x\n", 852 desired_child); 853 return -EINVAL; 854 } 855 regmap_field_write(gmac->regmap_field, val); 856 if (need_power_ephy) { 857 ret = sun8i_dwmac_power_internal_phy(priv); 858 if (ret) 859 return ret; 860 } else { 861 sun8i_dwmac_unpower_internal_phy(gmac); 862 } 863 /* After changing syscon value, the MAC need reset or it will 864 * use the last value (and so the last PHY set). 865 */ 866 ret = sun8i_dwmac_reset(priv); 867 } 868 return ret; 869 } 870 871 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 872 { 873 int ret; 874 struct device_node *mdio_mux; 875 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 876 877 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 878 if (!mdio_mux) 879 return -ENODEV; 880 881 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 882 &gmac->mux_handle, priv, priv->mii); 883 return ret; 884 } 885 886 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 887 { 888 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 889 struct device_node *node = priv->device->of_node; 890 int ret; 891 u32 reg, val; 892 893 ret = regmap_field_read(gmac->regmap_field, &val); 894 if (ret) { 895 dev_err(priv->device, "Fail to read from regmap field.\n"); 896 return ret; 897 } 898 899 reg = gmac->variant->default_syscon_value; 900 if (reg != val) 901 dev_warn(priv->device, 902 "Current syscon value is not the default %x (expect %x)\n", 903 val, reg); 904 905 if (gmac->variant->soc_has_internal_phy) { 906 if (of_property_read_bool(node, "allwinner,leds-active-low")) 907 reg |= H3_EPHY_LED_POL; 908 else 909 reg &= ~H3_EPHY_LED_POL; 910 911 /* Force EPHY xtal frequency to 24MHz. */ 912 reg |= H3_EPHY_CLK_SEL; 913 914 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 915 if (ret < 0) { 916 dev_err(priv->device, "Could not parse MDIO addr\n"); 917 return ret; 918 } 919 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 920 * address. No need to mask it again. 921 */ 922 reg |= 1 << H3_EPHY_ADDR_SHIFT; 923 } else { 924 /* For SoCs without internal PHY the PHY selection bit should be 925 * set to 0 (external PHY). 926 */ 927 reg &= ~H3_EPHY_SELECT; 928 } 929 930 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 931 if (val % 100) { 932 dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 933 return -EINVAL; 934 } 935 val /= 100; 936 dev_dbg(priv->device, "set tx-delay to %x\n", val); 937 if (val <= gmac->variant->tx_delay_max) { 938 reg &= ~(gmac->variant->tx_delay_max << 939 SYSCON_ETXDC_SHIFT); 940 reg |= (val << SYSCON_ETXDC_SHIFT); 941 } else { 942 dev_err(priv->device, "Invalid TX clock delay: %d\n", 943 val); 944 return -EINVAL; 945 } 946 } 947 948 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 949 if (val % 100) { 950 dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 951 return -EINVAL; 952 } 953 val /= 100; 954 dev_dbg(priv->device, "set rx-delay to %x\n", val); 955 if (val <= gmac->variant->rx_delay_max) { 956 reg &= ~(gmac->variant->rx_delay_max << 957 SYSCON_ERXDC_SHIFT); 958 reg |= (val << SYSCON_ERXDC_SHIFT); 959 } else { 960 dev_err(priv->device, "Invalid RX clock delay: %d\n", 961 val); 962 return -EINVAL; 963 } 964 } 965 966 /* Clear interface mode bits */ 967 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 968 if (gmac->variant->support_rmii) 969 reg &= ~SYSCON_RMII_EN; 970 971 switch (priv->plat->interface) { 972 case PHY_INTERFACE_MODE_MII: 973 /* default */ 974 break; 975 case PHY_INTERFACE_MODE_RGMII: 976 case PHY_INTERFACE_MODE_RGMII_ID: 977 case PHY_INTERFACE_MODE_RGMII_RXID: 978 case PHY_INTERFACE_MODE_RGMII_TXID: 979 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 980 break; 981 case PHY_INTERFACE_MODE_RMII: 982 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 983 break; 984 default: 985 dev_err(priv->device, "Unsupported interface mode: %s", 986 phy_modes(priv->plat->interface)); 987 return -EINVAL; 988 } 989 990 regmap_field_write(gmac->regmap_field, reg); 991 992 return 0; 993 } 994 995 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 996 { 997 u32 reg = gmac->variant->default_syscon_value; 998 999 regmap_field_write(gmac->regmap_field, reg); 1000 } 1001 1002 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 1003 { 1004 struct sunxi_priv_data *gmac = priv; 1005 1006 if (gmac->variant->soc_has_internal_phy) { 1007 /* sun8i_dwmac_exit could be called with mdiomux uninit */ 1008 if (gmac->mux_handle) 1009 mdio_mux_uninit(gmac->mux_handle); 1010 if (gmac->internal_phy_powered) 1011 sun8i_dwmac_unpower_internal_phy(gmac); 1012 } 1013 1014 sun8i_dwmac_unset_syscon(gmac); 1015 1016 reset_control_put(gmac->rst_ephy); 1017 1018 clk_disable_unprepare(gmac->tx_clk); 1019 1020 if (gmac->regulator) 1021 regulator_disable(gmac->regulator); 1022 } 1023 1024 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1025 { 1026 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1027 1028 if (enable) 1029 value |= EMAC_LOOPBACK; 1030 else 1031 value &= ~EMAC_LOOPBACK; 1032 1033 writel(value, ioaddr + EMAC_BASIC_CTL0); 1034 } 1035 1036 static const struct stmmac_ops sun8i_dwmac_ops = { 1037 .core_init = sun8i_dwmac_core_init, 1038 .set_mac = sun8i_dwmac_set_mac, 1039 .dump_regs = sun8i_dwmac_dump_mac_regs, 1040 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1041 .set_filter = sun8i_dwmac_set_filter, 1042 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1043 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1044 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1045 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1046 }; 1047 1048 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1049 { 1050 struct mac_device_info *mac; 1051 struct stmmac_priv *priv = ppriv; 1052 int ret; 1053 1054 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1055 if (!mac) 1056 return NULL; 1057 1058 ret = sun8i_dwmac_set_syscon(priv); 1059 if (ret) 1060 return NULL; 1061 1062 mac->pcsr = priv->ioaddr; 1063 mac->mac = &sun8i_dwmac_ops; 1064 mac->dma = &sun8i_dwmac_dma_ops; 1065 1066 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1067 1068 /* The loopback bit seems to be re-set when link change 1069 * Simply mask it each time 1070 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1071 */ 1072 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1073 mac->link.speed10 = EMAC_SPEED_10; 1074 mac->link.speed100 = EMAC_SPEED_100; 1075 mac->link.speed1000 = EMAC_SPEED_1000; 1076 mac->link.duplex = EMAC_DUPLEX_FULL; 1077 mac->mii.addr = EMAC_MDIO_CMD; 1078 mac->mii.data = EMAC_MDIO_DATA; 1079 mac->mii.reg_shift = 4; 1080 mac->mii.reg_mask = GENMASK(8, 4); 1081 mac->mii.addr_shift = 12; 1082 mac->mii.addr_mask = GENMASK(16, 12); 1083 mac->mii.clk_csr_shift = 20; 1084 mac->mii.clk_csr_mask = GENMASK(22, 20); 1085 mac->unicast_filter_entries = 8; 1086 1087 /* Synopsys Id is not available */ 1088 priv->synopsys_id = 0; 1089 1090 return mac; 1091 } 1092 1093 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1094 { 1095 struct device_node *syscon_node; 1096 struct platform_device *syscon_pdev; 1097 struct regmap *regmap = NULL; 1098 1099 syscon_node = of_parse_phandle(node, "syscon", 0); 1100 if (!syscon_node) 1101 return ERR_PTR(-ENODEV); 1102 1103 syscon_pdev = of_find_device_by_node(syscon_node); 1104 if (!syscon_pdev) { 1105 /* platform device might not be probed yet */ 1106 regmap = ERR_PTR(-EPROBE_DEFER); 1107 goto out_put_node; 1108 } 1109 1110 /* If no regmap is found then the other device driver is at fault */ 1111 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1112 if (!regmap) 1113 regmap = ERR_PTR(-EINVAL); 1114 1115 platform_device_put(syscon_pdev); 1116 out_put_node: 1117 of_node_put(syscon_node); 1118 return regmap; 1119 } 1120 1121 static int sun8i_dwmac_probe(struct platform_device *pdev) 1122 { 1123 struct plat_stmmacenet_data *plat_dat; 1124 struct stmmac_resources stmmac_res; 1125 struct sunxi_priv_data *gmac; 1126 struct device *dev = &pdev->dev; 1127 phy_interface_t interface; 1128 int ret; 1129 struct stmmac_priv *priv; 1130 struct net_device *ndev; 1131 struct regmap *regmap; 1132 1133 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1134 if (ret) 1135 return ret; 1136 1137 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1138 if (IS_ERR(plat_dat)) 1139 return PTR_ERR(plat_dat); 1140 1141 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1142 if (!gmac) 1143 return -ENOMEM; 1144 1145 gmac->variant = of_device_get_match_data(&pdev->dev); 1146 if (!gmac->variant) { 1147 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1148 return -EINVAL; 1149 } 1150 1151 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1152 if (IS_ERR(gmac->tx_clk)) { 1153 dev_err(dev, "Could not get TX clock\n"); 1154 return PTR_ERR(gmac->tx_clk); 1155 } 1156 1157 /* Optional regulator for PHY */ 1158 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1159 if (IS_ERR(gmac->regulator)) { 1160 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1161 return -EPROBE_DEFER; 1162 dev_info(dev, "No regulator found\n"); 1163 gmac->regulator = NULL; 1164 } 1165 1166 /* The "GMAC clock control" register might be located in the 1167 * CCU address range (on the R40), or the system control address 1168 * range (on most other sun8i and later SoCs). 1169 * 1170 * The former controls most if not all clocks in the SoC. The 1171 * latter has an SoC identification register, and on some SoCs, 1172 * controls to map device specific SRAM to either the intended 1173 * peripheral, or the CPU address space. 1174 * 1175 * In either case, there should be a coordinated and restricted 1176 * method of accessing the register needed here. This is done by 1177 * having the device export a custom regmap, instead of a generic 1178 * syscon, which grants all access to all registers. 1179 * 1180 * To support old device trees, we fall back to using the syscon 1181 * interface if possible. 1182 */ 1183 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1184 if (IS_ERR(regmap)) 1185 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1186 "syscon"); 1187 if (IS_ERR(regmap)) { 1188 ret = PTR_ERR(regmap); 1189 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1190 return ret; 1191 } 1192 1193 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1194 *gmac->variant->syscon_field); 1195 if (IS_ERR(gmac->regmap_field)) { 1196 ret = PTR_ERR(gmac->regmap_field); 1197 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1198 return ret; 1199 } 1200 1201 ret = of_get_phy_mode(dev->of_node, &interface); 1202 if (ret) 1203 return -EINVAL; 1204 plat_dat->interface = interface; 1205 1206 /* platform data specifying hardware features and callbacks. 1207 * hardware features were copied from Allwinner drivers. 1208 */ 1209 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1210 plat_dat->tx_coe = 1; 1211 plat_dat->has_sun8i = true; 1212 plat_dat->bsp_priv = gmac; 1213 plat_dat->init = sun8i_dwmac_init; 1214 plat_dat->exit = sun8i_dwmac_exit; 1215 plat_dat->setup = sun8i_dwmac_setup; 1216 1217 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1218 if (ret) 1219 return ret; 1220 1221 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1222 if (ret) 1223 goto dwmac_exit; 1224 1225 ndev = dev_get_drvdata(&pdev->dev); 1226 priv = netdev_priv(ndev); 1227 /* The mux must be registered after parent MDIO 1228 * so after stmmac_dvr_probe() 1229 */ 1230 if (gmac->variant->soc_has_internal_phy) { 1231 ret = get_ephy_nodes(priv); 1232 if (ret) 1233 goto dwmac_exit; 1234 ret = sun8i_dwmac_register_mdio_mux(priv); 1235 if (ret) { 1236 dev_err(&pdev->dev, "Failed to register mux\n"); 1237 goto dwmac_mux; 1238 } 1239 } else { 1240 ret = sun8i_dwmac_reset(priv); 1241 if (ret) 1242 goto dwmac_exit; 1243 } 1244 1245 return ret; 1246 dwmac_mux: 1247 sun8i_dwmac_unset_syscon(gmac); 1248 dwmac_exit: 1249 stmmac_pltfr_remove(pdev); 1250 return ret; 1251 } 1252 1253 static const struct of_device_id sun8i_dwmac_match[] = { 1254 { .compatible = "allwinner,sun8i-h3-emac", 1255 .data = &emac_variant_h3 }, 1256 { .compatible = "allwinner,sun8i-v3s-emac", 1257 .data = &emac_variant_v3s }, 1258 { .compatible = "allwinner,sun8i-a83t-emac", 1259 .data = &emac_variant_a83t }, 1260 { .compatible = "allwinner,sun8i-r40-gmac", 1261 .data = &emac_variant_r40 }, 1262 { .compatible = "allwinner,sun50i-a64-emac", 1263 .data = &emac_variant_a64 }, 1264 { .compatible = "allwinner,sun50i-h6-emac", 1265 .data = &emac_variant_h6 }, 1266 { } 1267 }; 1268 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1269 1270 static struct platform_driver sun8i_dwmac_driver = { 1271 .probe = sun8i_dwmac_probe, 1272 .remove = stmmac_pltfr_remove, 1273 .driver = { 1274 .name = "dwmac-sun8i", 1275 .pm = &stmmac_pltfr_pm_ops, 1276 .of_match_table = sun8i_dwmac_match, 1277 }, 1278 }; 1279 module_platform_driver(sun8i_dwmac_driver); 1280 1281 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1282 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1283 MODULE_LICENSE("GPL"); 1284