1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 4 * 5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/mdio-mux.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/stmmac.h> 22 23 #include "stmmac.h" 24 #include "stmmac_platform.h" 25 26 /* General notes on dwmac-sun8i: 27 * Locking: no locking is necessary in this file because all necessary locking 28 * is done in the "stmmac files" 29 */ 30 31 /* struct emac_variant - Describe dwmac-sun8i hardware variant 32 * @default_syscon_value: The default value of the EMAC register in syscon 33 * This value is used for disabling properly EMAC 34 * and used as a good starting value in case of the 35 * boot process(uboot) leave some stuff. 36 * @syscon_field reg_field for the syscon's gmac register 37 * @soc_has_internal_phy: Does the MAC embed an internal PHY 38 * @support_mii: Does the MAC handle MII 39 * @support_rmii: Does the MAC handle RMII 40 * @support_rgmii: Does the MAC handle RGMII 41 * 42 * @rx_delay_max: Maximum raw value for RX delay chain 43 * @tx_delay_max: Maximum raw value for TX delay chain 44 * These two also indicate the bitmask for 45 * the RX and TX delay chain registers. A 46 * value of zero indicates this is not supported. 47 */ 48 struct emac_variant { 49 u32 default_syscon_value; 50 const struct reg_field *syscon_field; 51 bool soc_has_internal_phy; 52 bool support_mii; 53 bool support_rmii; 54 bool support_rgmii; 55 u8 rx_delay_max; 56 u8 tx_delay_max; 57 }; 58 59 /* struct sunxi_priv_data - hold all sunxi private data 60 * @tx_clk: reference to MAC TX clock 61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY 62 * @regulator: reference to the optional regulator 63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY 64 * @variant: reference to the current board variant 65 * @regmap: regmap for using the syscon 66 * @internal_phy_powered: Does the internal PHY is enabled 67 * @use_internal_phy: Is the internal PHY selected for use 68 * @mux_handle: Internal pointer used by mdio-mux lib 69 */ 70 struct sunxi_priv_data { 71 struct clk *tx_clk; 72 struct clk *ephy_clk; 73 struct regulator *regulator; 74 struct reset_control *rst_ephy; 75 const struct emac_variant *variant; 76 struct regmap_field *regmap_field; 77 bool internal_phy_powered; 78 bool use_internal_phy; 79 void *mux_handle; 80 }; 81 82 /* EMAC clock register @ 0x30 in the "system control" address range */ 83 static const struct reg_field sun8i_syscon_reg_field = { 84 .reg = 0x30, 85 .lsb = 0, 86 .msb = 31, 87 }; 88 89 /* EMAC clock register @ 0x164 in the CCU address range */ 90 static const struct reg_field sun8i_ccu_reg_field = { 91 .reg = 0x164, 92 .lsb = 0, 93 .msb = 31, 94 }; 95 96 static const struct emac_variant emac_variant_h3 = { 97 .default_syscon_value = 0x58000, 98 .syscon_field = &sun8i_syscon_reg_field, 99 .soc_has_internal_phy = true, 100 .support_mii = true, 101 .support_rmii = true, 102 .support_rgmii = true, 103 .rx_delay_max = 31, 104 .tx_delay_max = 7, 105 }; 106 107 static const struct emac_variant emac_variant_v3s = { 108 .default_syscon_value = 0x38000, 109 .syscon_field = &sun8i_syscon_reg_field, 110 .soc_has_internal_phy = true, 111 .support_mii = true 112 }; 113 114 static const struct emac_variant emac_variant_a83t = { 115 .default_syscon_value = 0, 116 .syscon_field = &sun8i_syscon_reg_field, 117 .soc_has_internal_phy = false, 118 .support_mii = true, 119 .support_rgmii = true, 120 .rx_delay_max = 31, 121 .tx_delay_max = 7, 122 }; 123 124 static const struct emac_variant emac_variant_r40 = { 125 .default_syscon_value = 0, 126 .syscon_field = &sun8i_ccu_reg_field, 127 .support_mii = true, 128 .support_rgmii = true, 129 .rx_delay_max = 7, 130 }; 131 132 static const struct emac_variant emac_variant_a64 = { 133 .default_syscon_value = 0, 134 .syscon_field = &sun8i_syscon_reg_field, 135 .soc_has_internal_phy = false, 136 .support_mii = true, 137 .support_rmii = true, 138 .support_rgmii = true, 139 .rx_delay_max = 31, 140 .tx_delay_max = 7, 141 }; 142 143 static const struct emac_variant emac_variant_h6 = { 144 .default_syscon_value = 0x50000, 145 .syscon_field = &sun8i_syscon_reg_field, 146 /* The "Internal PHY" of H6 is not on the die. It's on the 147 * co-packaged AC200 chip instead. 148 */ 149 .soc_has_internal_phy = false, 150 .support_mii = true, 151 .support_rmii = true, 152 .support_rgmii = true, 153 .rx_delay_max = 31, 154 .tx_delay_max = 7, 155 }; 156 157 #define EMAC_BASIC_CTL0 0x00 158 #define EMAC_BASIC_CTL1 0x04 159 #define EMAC_INT_STA 0x08 160 #define EMAC_INT_EN 0x0C 161 #define EMAC_TX_CTL0 0x10 162 #define EMAC_TX_CTL1 0x14 163 #define EMAC_TX_FLOW_CTL 0x1C 164 #define EMAC_TX_DESC_LIST 0x20 165 #define EMAC_RX_CTL0 0x24 166 #define EMAC_RX_CTL1 0x28 167 #define EMAC_RX_DESC_LIST 0x34 168 #define EMAC_RX_FRM_FLT 0x38 169 #define EMAC_MDIO_CMD 0x48 170 #define EMAC_MDIO_DATA 0x4C 171 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 172 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 173 #define EMAC_TX_DMA_STA 0xB0 174 #define EMAC_TX_CUR_DESC 0xB4 175 #define EMAC_TX_CUR_BUF 0xB8 176 #define EMAC_RX_DMA_STA 0xC0 177 #define EMAC_RX_CUR_DESC 0xC4 178 #define EMAC_RX_CUR_BUF 0xC8 179 180 /* Use in EMAC_BASIC_CTL0 */ 181 #define EMAC_DUPLEX_FULL BIT(0) 182 #define EMAC_LOOPBACK BIT(1) 183 #define EMAC_SPEED_1000 0 184 #define EMAC_SPEED_100 (0x03 << 2) 185 #define EMAC_SPEED_10 (0x02 << 2) 186 187 /* Use in EMAC_BASIC_CTL1 */ 188 #define EMAC_BURSTLEN_SHIFT 24 189 190 /* Used in EMAC_RX_FRM_FLT */ 191 #define EMAC_FRM_FLT_RXALL BIT(0) 192 #define EMAC_FRM_FLT_CTL BIT(13) 193 #define EMAC_FRM_FLT_MULTICAST BIT(16) 194 195 /* Used in RX_CTL1*/ 196 #define EMAC_RX_MD BIT(1) 197 #define EMAC_RX_TH_MASK GENMASK(5, 4) 198 #define EMAC_RX_TH_32 0 199 #define EMAC_RX_TH_64 (0x1 << 4) 200 #define EMAC_RX_TH_96 (0x2 << 4) 201 #define EMAC_RX_TH_128 (0x3 << 4) 202 #define EMAC_RX_DMA_EN BIT(30) 203 #define EMAC_RX_DMA_START BIT(31) 204 205 /* Used in TX_CTL1*/ 206 #define EMAC_TX_MD BIT(1) 207 #define EMAC_TX_NEXT_FRM BIT(2) 208 #define EMAC_TX_TH_MASK GENMASK(10, 8) 209 #define EMAC_TX_TH_64 0 210 #define EMAC_TX_TH_128 (0x1 << 8) 211 #define EMAC_TX_TH_192 (0x2 << 8) 212 #define EMAC_TX_TH_256 (0x3 << 8) 213 #define EMAC_TX_DMA_EN BIT(30) 214 #define EMAC_TX_DMA_START BIT(31) 215 216 /* Used in RX_CTL0 */ 217 #define EMAC_RX_RECEIVER_EN BIT(31) 218 #define EMAC_RX_DO_CRC BIT(27) 219 #define EMAC_RX_FLOW_CTL_EN BIT(16) 220 221 /* Used in TX_CTL0 */ 222 #define EMAC_TX_TRANSMITTER_EN BIT(31) 223 224 /* Used in EMAC_TX_FLOW_CTL */ 225 #define EMAC_TX_FLOW_CTL_EN BIT(0) 226 227 /* Used in EMAC_INT_STA */ 228 #define EMAC_TX_INT BIT(0) 229 #define EMAC_TX_DMA_STOP_INT BIT(1) 230 #define EMAC_TX_BUF_UA_INT BIT(2) 231 #define EMAC_TX_TIMEOUT_INT BIT(3) 232 #define EMAC_TX_UNDERFLOW_INT BIT(4) 233 #define EMAC_TX_EARLY_INT BIT(5) 234 #define EMAC_RX_INT BIT(8) 235 #define EMAC_RX_BUF_UA_INT BIT(9) 236 #define EMAC_RX_DMA_STOP_INT BIT(10) 237 #define EMAC_RX_TIMEOUT_INT BIT(11) 238 #define EMAC_RX_OVERFLOW_INT BIT(12) 239 #define EMAC_RX_EARLY_INT BIT(13) 240 #define EMAC_RGMII_STA_INT BIT(16) 241 242 #define EMAC_INT_MSK_COMMON EMAC_RGMII_STA_INT 243 #define EMAC_INT_MSK_TX (EMAC_TX_INT | \ 244 EMAC_TX_DMA_STOP_INT | \ 245 EMAC_TX_BUF_UA_INT | \ 246 EMAC_TX_TIMEOUT_INT | \ 247 EMAC_TX_UNDERFLOW_INT | \ 248 EMAC_TX_EARLY_INT |\ 249 EMAC_INT_MSK_COMMON) 250 #define EMAC_INT_MSK_RX (EMAC_RX_INT | \ 251 EMAC_RX_BUF_UA_INT | \ 252 EMAC_RX_DMA_STOP_INT | \ 253 EMAC_RX_TIMEOUT_INT | \ 254 EMAC_RX_OVERFLOW_INT | \ 255 EMAC_RX_EARLY_INT | \ 256 EMAC_INT_MSK_COMMON) 257 258 #define MAC_ADDR_TYPE_DST BIT(31) 259 260 /* H3 specific bits for EPHY */ 261 #define H3_EPHY_ADDR_SHIFT 20 262 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 263 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 264 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 265 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 266 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 267 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 268 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 269 270 /* H3/A64 specific bits */ 271 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 272 273 /* Generic system control EMAC_CLK bits */ 274 #define SYSCON_ETXDC_SHIFT 10 275 #define SYSCON_ERXDC_SHIFT 5 276 /* EMAC PHY Interface Type */ 277 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 278 #define SYSCON_ETCS_MASK GENMASK(1, 0) 279 #define SYSCON_ETCS_MII 0x0 280 #define SYSCON_ETCS_EXT_GMII 0x1 281 #define SYSCON_ETCS_INT_GMII 0x2 282 283 /* sun8i_dwmac_dma_reset() - reset the EMAC 284 * Called from stmmac via stmmac_dma_ops->reset 285 */ 286 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 287 { 288 writel(0, ioaddr + EMAC_RX_CTL1); 289 writel(0, ioaddr + EMAC_TX_CTL1); 290 writel(0, ioaddr + EMAC_RX_FRM_FLT); 291 writel(0, ioaddr + EMAC_RX_DESC_LIST); 292 writel(0, ioaddr + EMAC_TX_DESC_LIST); 293 writel(0, ioaddr + EMAC_INT_EN); 294 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 295 return 0; 296 } 297 298 /* sun8i_dwmac_dma_init() - initialize the EMAC 299 * Called from stmmac via stmmac_dma_ops->init 300 */ 301 static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 302 struct stmmac_dma_cfg *dma_cfg, int atds) 303 { 304 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 305 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 306 } 307 308 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 309 struct stmmac_dma_cfg *dma_cfg, 310 dma_addr_t dma_rx_phy, u32 chan) 311 { 312 /* Write RX descriptors address */ 313 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 314 } 315 316 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 317 struct stmmac_dma_cfg *dma_cfg, 318 dma_addr_t dma_tx_phy, u32 chan) 319 { 320 /* Write TX descriptors address */ 321 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 322 } 323 324 /* sun8i_dwmac_dump_regs() - Dump EMAC address space 325 * Called from stmmac_dma_ops->dump_regs 326 * Used for ethtool 327 */ 328 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 329 { 330 int i; 331 332 for (i = 0; i < 0xC8; i += 4) { 333 if (i == 0x32 || i == 0x3C) 334 continue; 335 reg_space[i / 4] = readl(ioaddr + i); 336 } 337 } 338 339 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 340 * Called from stmmac_ops->dump_regs 341 * Used for ethtool 342 */ 343 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 344 u32 *reg_space) 345 { 346 int i; 347 void __iomem *ioaddr = hw->pcsr; 348 349 for (i = 0; i < 0xC8; i += 4) { 350 if (i == 0x32 || i == 0x3C) 351 continue; 352 reg_space[i / 4] = readl(ioaddr + i); 353 } 354 } 355 356 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, 357 bool rx, bool tx) 358 { 359 u32 value = readl(ioaddr + EMAC_INT_EN); 360 361 if (rx) 362 value |= EMAC_RX_INT; 363 if (tx) 364 value |= EMAC_TX_INT; 365 366 writel(value, ioaddr + EMAC_INT_EN); 367 } 368 369 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, 370 bool rx, bool tx) 371 { 372 u32 value = readl(ioaddr + EMAC_INT_EN); 373 374 if (rx) 375 value &= ~EMAC_RX_INT; 376 if (tx) 377 value &= ~EMAC_TX_INT; 378 379 writel(value, ioaddr + EMAC_INT_EN); 380 } 381 382 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 383 { 384 u32 v; 385 386 v = readl(ioaddr + EMAC_TX_CTL1); 387 v |= EMAC_TX_DMA_START; 388 v |= EMAC_TX_DMA_EN; 389 writel(v, ioaddr + EMAC_TX_CTL1); 390 } 391 392 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 393 { 394 u32 v; 395 396 v = readl(ioaddr + EMAC_TX_CTL1); 397 v |= EMAC_TX_DMA_START; 398 v |= EMAC_TX_DMA_EN; 399 writel(v, ioaddr + EMAC_TX_CTL1); 400 } 401 402 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 403 { 404 u32 v; 405 406 v = readl(ioaddr + EMAC_TX_CTL1); 407 v &= ~EMAC_TX_DMA_EN; 408 writel(v, ioaddr + EMAC_TX_CTL1); 409 } 410 411 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 412 { 413 u32 v; 414 415 v = readl(ioaddr + EMAC_RX_CTL1); 416 v |= EMAC_RX_DMA_START; 417 v |= EMAC_RX_DMA_EN; 418 writel(v, ioaddr + EMAC_RX_CTL1); 419 } 420 421 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 422 { 423 u32 v; 424 425 v = readl(ioaddr + EMAC_RX_CTL1); 426 v &= ~EMAC_RX_DMA_EN; 427 writel(v, ioaddr + EMAC_RX_CTL1); 428 } 429 430 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 431 struct stmmac_extra_stats *x, u32 chan, 432 u32 dir) 433 { 434 u32 v; 435 int ret = 0; 436 437 v = readl(ioaddr + EMAC_INT_STA); 438 439 if (dir == DMA_DIR_RX) 440 v &= EMAC_INT_MSK_RX; 441 else if (dir == DMA_DIR_TX) 442 v &= EMAC_INT_MSK_TX; 443 444 if (v & EMAC_TX_INT) { 445 ret |= handle_tx; 446 x->tx_normal_irq_n++; 447 } 448 449 if (v & EMAC_TX_DMA_STOP_INT) 450 x->tx_process_stopped_irq++; 451 452 if (v & EMAC_TX_BUF_UA_INT) 453 x->tx_process_stopped_irq++; 454 455 if (v & EMAC_TX_TIMEOUT_INT) 456 ret |= tx_hard_error; 457 458 if (v & EMAC_TX_UNDERFLOW_INT) { 459 ret |= tx_hard_error; 460 x->tx_undeflow_irq++; 461 } 462 463 if (v & EMAC_TX_EARLY_INT) 464 x->tx_early_irq++; 465 466 if (v & EMAC_RX_INT) { 467 ret |= handle_rx; 468 x->rx_normal_irq_n++; 469 } 470 471 if (v & EMAC_RX_BUF_UA_INT) 472 x->rx_buf_unav_irq++; 473 474 if (v & EMAC_RX_DMA_STOP_INT) 475 x->rx_process_stopped_irq++; 476 477 if (v & EMAC_RX_TIMEOUT_INT) 478 ret |= tx_hard_error; 479 480 if (v & EMAC_RX_OVERFLOW_INT) { 481 ret |= tx_hard_error; 482 x->rx_overflow_irq++; 483 } 484 485 if (v & EMAC_RX_EARLY_INT) 486 x->rx_early_irq++; 487 488 if (v & EMAC_RGMII_STA_INT) 489 x->irq_rgmii_n++; 490 491 writel(v, ioaddr + EMAC_INT_STA); 492 493 return ret; 494 } 495 496 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 497 u32 channel, int fifosz, u8 qmode) 498 { 499 u32 v; 500 501 v = readl(ioaddr + EMAC_RX_CTL1); 502 if (mode == SF_DMA_MODE) { 503 v |= EMAC_RX_MD; 504 } else { 505 v &= ~EMAC_RX_MD; 506 v &= ~EMAC_RX_TH_MASK; 507 if (mode < 32) 508 v |= EMAC_RX_TH_32; 509 else if (mode < 64) 510 v |= EMAC_RX_TH_64; 511 else if (mode < 96) 512 v |= EMAC_RX_TH_96; 513 else if (mode < 128) 514 v |= EMAC_RX_TH_128; 515 } 516 writel(v, ioaddr + EMAC_RX_CTL1); 517 } 518 519 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 520 u32 channel, int fifosz, u8 qmode) 521 { 522 u32 v; 523 524 v = readl(ioaddr + EMAC_TX_CTL1); 525 if (mode == SF_DMA_MODE) { 526 v |= EMAC_TX_MD; 527 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 528 * comment is 529 * "Operating on second frame increase the performance 530 * especially when transmit store-and-forward is used." 531 */ 532 v |= EMAC_TX_NEXT_FRM; 533 } else { 534 v &= ~EMAC_TX_MD; 535 v &= ~EMAC_TX_TH_MASK; 536 if (mode < 64) 537 v |= EMAC_TX_TH_64; 538 else if (mode < 128) 539 v |= EMAC_TX_TH_128; 540 else if (mode < 192) 541 v |= EMAC_TX_TH_192; 542 else if (mode < 256) 543 v |= EMAC_TX_TH_256; 544 } 545 writel(v, ioaddr + EMAC_TX_CTL1); 546 } 547 548 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 549 .reset = sun8i_dwmac_dma_reset, 550 .init = sun8i_dwmac_dma_init, 551 .init_rx_chan = sun8i_dwmac_dma_init_rx, 552 .init_tx_chan = sun8i_dwmac_dma_init_tx, 553 .dump_regs = sun8i_dwmac_dump_regs, 554 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 555 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 556 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 557 .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 558 .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 559 .start_tx = sun8i_dwmac_dma_start_tx, 560 .stop_tx = sun8i_dwmac_dma_stop_tx, 561 .start_rx = sun8i_dwmac_dma_start_rx, 562 .stop_rx = sun8i_dwmac_dma_stop_rx, 563 .dma_interrupt = sun8i_dwmac_dma_interrupt, 564 }; 565 566 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); 567 568 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 569 { 570 struct net_device *ndev = platform_get_drvdata(pdev); 571 struct sunxi_priv_data *gmac = priv; 572 int ret; 573 574 if (gmac->regulator) { 575 ret = regulator_enable(gmac->regulator); 576 if (ret) { 577 dev_err(&pdev->dev, "Fail to enable regulator\n"); 578 return ret; 579 } 580 } 581 582 ret = clk_prepare_enable(gmac->tx_clk); 583 if (ret) { 584 dev_err(&pdev->dev, "Could not enable AHB clock\n"); 585 goto err_disable_regulator; 586 } 587 588 if (gmac->use_internal_phy) { 589 ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); 590 if (ret) 591 goto err_disable_clk; 592 } 593 594 return 0; 595 596 err_disable_clk: 597 clk_disable_unprepare(gmac->tx_clk); 598 err_disable_regulator: 599 if (gmac->regulator) 600 regulator_disable(gmac->regulator); 601 602 return ret; 603 } 604 605 static void sun8i_dwmac_core_init(struct mac_device_info *hw, 606 struct net_device *dev) 607 { 608 void __iomem *ioaddr = hw->pcsr; 609 u32 v; 610 611 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 612 writel(v, ioaddr + EMAC_BASIC_CTL1); 613 } 614 615 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 616 { 617 u32 t, r; 618 619 t = readl(ioaddr + EMAC_TX_CTL0); 620 r = readl(ioaddr + EMAC_RX_CTL0); 621 if (enable) { 622 t |= EMAC_TX_TRANSMITTER_EN; 623 r |= EMAC_RX_RECEIVER_EN; 624 } else { 625 t &= ~EMAC_TX_TRANSMITTER_EN; 626 r &= ~EMAC_RX_RECEIVER_EN; 627 } 628 writel(t, ioaddr + EMAC_TX_CTL0); 629 writel(r, ioaddr + EMAC_RX_CTL0); 630 } 631 632 /* Set MAC address at slot reg_n 633 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 634 * If addr is NULL, clear the slot 635 */ 636 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 637 unsigned char *addr, 638 unsigned int reg_n) 639 { 640 void __iomem *ioaddr = hw->pcsr; 641 u32 v; 642 643 if (!addr) { 644 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 645 return; 646 } 647 648 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 649 EMAC_MACADDR_LO(reg_n)); 650 if (reg_n > 0) { 651 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 652 v |= MAC_ADDR_TYPE_DST; 653 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 654 } 655 } 656 657 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 658 unsigned char *addr, 659 unsigned int reg_n) 660 { 661 void __iomem *ioaddr = hw->pcsr; 662 663 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 664 EMAC_MACADDR_LO(reg_n)); 665 } 666 667 /* caution this function must return non 0 to work */ 668 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 669 { 670 void __iomem *ioaddr = hw->pcsr; 671 u32 v; 672 673 v = readl(ioaddr + EMAC_RX_CTL0); 674 v |= EMAC_RX_DO_CRC; 675 writel(v, ioaddr + EMAC_RX_CTL0); 676 677 return 1; 678 } 679 680 static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 681 struct net_device *dev) 682 { 683 void __iomem *ioaddr = hw->pcsr; 684 u32 v; 685 int i = 1; 686 struct netdev_hw_addr *ha; 687 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 688 689 v = EMAC_FRM_FLT_CTL; 690 691 if (dev->flags & IFF_PROMISC) { 692 v = EMAC_FRM_FLT_RXALL; 693 } else if (dev->flags & IFF_ALLMULTI) { 694 v |= EMAC_FRM_FLT_MULTICAST; 695 } else if (macaddrs <= hw->unicast_filter_entries) { 696 if (!netdev_mc_empty(dev)) { 697 netdev_for_each_mc_addr(ha, dev) { 698 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 699 i++; 700 } 701 } 702 if (!netdev_uc_empty(dev)) { 703 netdev_for_each_uc_addr(ha, dev) { 704 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 705 i++; 706 } 707 } 708 } else { 709 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 710 netdev_info(dev, "Too many address, switching to promiscuous\n"); 711 v = EMAC_FRM_FLT_RXALL; 712 } 713 714 /* Disable unused address filter slots */ 715 while (i < hw->unicast_filter_entries) 716 sun8i_dwmac_set_umac_addr(hw, NULL, i++); 717 718 writel(v, ioaddr + EMAC_RX_FRM_FLT); 719 } 720 721 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 722 unsigned int duplex, unsigned int fc, 723 unsigned int pause_time, u32 tx_cnt) 724 { 725 void __iomem *ioaddr = hw->pcsr; 726 u32 v; 727 728 v = readl(ioaddr + EMAC_RX_CTL0); 729 if (fc == FLOW_AUTO) 730 v |= EMAC_RX_FLOW_CTL_EN; 731 else 732 v &= ~EMAC_RX_FLOW_CTL_EN; 733 writel(v, ioaddr + EMAC_RX_CTL0); 734 735 v = readl(ioaddr + EMAC_TX_FLOW_CTL); 736 if (fc == FLOW_AUTO) 737 v |= EMAC_TX_FLOW_CTL_EN; 738 else 739 v &= ~EMAC_TX_FLOW_CTL_EN; 740 writel(v, ioaddr + EMAC_TX_FLOW_CTL); 741 } 742 743 static int sun8i_dwmac_reset(struct stmmac_priv *priv) 744 { 745 u32 v; 746 int err; 747 748 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 749 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 750 751 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 752 * need more if no cable plugged. 100ms seems OK 753 */ 754 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 755 !(v & 0x01), 100, 100000); 756 757 if (err) { 758 dev_err(priv->device, "EMAC reset timeout\n"); 759 return err; 760 } 761 return 0; 762 } 763 764 /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 765 static int get_ephy_nodes(struct stmmac_priv *priv) 766 { 767 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 768 struct device_node *mdio_mux, *iphynode; 769 struct device_node *mdio_internal; 770 int ret; 771 772 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 773 if (!mdio_mux) { 774 dev_err(priv->device, "Cannot get mdio-mux node\n"); 775 return -ENODEV; 776 } 777 778 mdio_internal = of_get_compatible_child(mdio_mux, 779 "allwinner,sun8i-h3-mdio-internal"); 780 of_node_put(mdio_mux); 781 if (!mdio_internal) { 782 dev_err(priv->device, "Cannot get internal_mdio node\n"); 783 return -ENODEV; 784 } 785 786 /* Seek for internal PHY */ 787 for_each_child_of_node(mdio_internal, iphynode) { 788 gmac->ephy_clk = of_clk_get(iphynode, 0); 789 if (IS_ERR(gmac->ephy_clk)) 790 continue; 791 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 792 if (IS_ERR(gmac->rst_ephy)) { 793 ret = PTR_ERR(gmac->rst_ephy); 794 if (ret == -EPROBE_DEFER) { 795 of_node_put(iphynode); 796 of_node_put(mdio_internal); 797 return ret; 798 } 799 continue; 800 } 801 dev_info(priv->device, "Found internal PHY node\n"); 802 of_node_put(iphynode); 803 of_node_put(mdio_internal); 804 return 0; 805 } 806 807 of_node_put(mdio_internal); 808 return -ENODEV; 809 } 810 811 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 812 { 813 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 814 int ret; 815 816 if (gmac->internal_phy_powered) { 817 dev_warn(priv->device, "Internal PHY already powered\n"); 818 return 0; 819 } 820 821 dev_info(priv->device, "Powering internal PHY\n"); 822 ret = clk_prepare_enable(gmac->ephy_clk); 823 if (ret) { 824 dev_err(priv->device, "Cannot enable internal PHY\n"); 825 return ret; 826 } 827 828 /* Make sure the EPHY is properly reseted, as U-Boot may leave 829 * it at deasserted state, and thus it may fail to reset EMAC. 830 * 831 * This assumes the driver has exclusive access to the EPHY reset. 832 */ 833 ret = reset_control_reset(gmac->rst_ephy); 834 if (ret) { 835 dev_err(priv->device, "Cannot reset internal PHY\n"); 836 clk_disable_unprepare(gmac->ephy_clk); 837 return ret; 838 } 839 840 gmac->internal_phy_powered = true; 841 842 return 0; 843 } 844 845 static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 846 { 847 if (!gmac->internal_phy_powered) 848 return; 849 850 clk_disable_unprepare(gmac->ephy_clk); 851 reset_control_assert(gmac->rst_ephy); 852 gmac->internal_phy_powered = false; 853 } 854 855 /* MDIO multiplexing switch function 856 * This function is called by the mdio-mux layer when it thinks the mdio bus 857 * multiplexer needs to switch. 858 * 'current_child' is the current value of the mux register 859 * 'desired_child' is the value of the 'reg' property of the target child MDIO 860 * node. 861 * The first time this function is called, current_child == -1. 862 * If current_child == desired_child, then the mux is already set to the 863 * correct bus. 864 */ 865 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 866 void *data) 867 { 868 struct stmmac_priv *priv = data; 869 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 870 u32 reg, val; 871 int ret = 0; 872 873 if (current_child ^ desired_child) { 874 regmap_field_read(gmac->regmap_field, ®); 875 switch (desired_child) { 876 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 877 dev_info(priv->device, "Switch mux to internal PHY"); 878 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 879 gmac->use_internal_phy = true; 880 break; 881 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 882 dev_info(priv->device, "Switch mux to external PHY"); 883 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 884 gmac->use_internal_phy = false; 885 break; 886 default: 887 dev_err(priv->device, "Invalid child ID %x\n", 888 desired_child); 889 return -EINVAL; 890 } 891 regmap_field_write(gmac->regmap_field, val); 892 if (gmac->use_internal_phy) { 893 ret = sun8i_dwmac_power_internal_phy(priv); 894 if (ret) 895 return ret; 896 } else { 897 sun8i_dwmac_unpower_internal_phy(gmac); 898 } 899 /* After changing syscon value, the MAC need reset or it will 900 * use the last value (and so the last PHY set). 901 */ 902 ret = sun8i_dwmac_reset(priv); 903 } 904 return ret; 905 } 906 907 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 908 { 909 int ret; 910 struct device_node *mdio_mux; 911 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 912 913 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 914 if (!mdio_mux) 915 return -ENODEV; 916 917 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 918 &gmac->mux_handle, priv, priv->mii); 919 of_node_put(mdio_mux); 920 return ret; 921 } 922 923 static int sun8i_dwmac_set_syscon(struct device *dev, 924 struct plat_stmmacenet_data *plat) 925 { 926 struct sunxi_priv_data *gmac = plat->bsp_priv; 927 struct device_node *node = dev->of_node; 928 int ret; 929 u32 reg, val; 930 931 ret = regmap_field_read(gmac->regmap_field, &val); 932 if (ret) { 933 dev_err(dev, "Fail to read from regmap field.\n"); 934 return ret; 935 } 936 937 reg = gmac->variant->default_syscon_value; 938 if (reg != val) 939 dev_warn(dev, 940 "Current syscon value is not the default %x (expect %x)\n", 941 val, reg); 942 943 if (gmac->variant->soc_has_internal_phy) { 944 if (of_property_read_bool(node, "allwinner,leds-active-low")) 945 reg |= H3_EPHY_LED_POL; 946 else 947 reg &= ~H3_EPHY_LED_POL; 948 949 /* Force EPHY xtal frequency to 24MHz. */ 950 reg |= H3_EPHY_CLK_SEL; 951 952 ret = of_mdio_parse_addr(dev, plat->phy_node); 953 if (ret < 0) { 954 dev_err(dev, "Could not parse MDIO addr\n"); 955 return ret; 956 } 957 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 958 * address. No need to mask it again. 959 */ 960 reg |= 1 << H3_EPHY_ADDR_SHIFT; 961 } else { 962 /* For SoCs without internal PHY the PHY selection bit should be 963 * set to 0 (external PHY). 964 */ 965 reg &= ~H3_EPHY_SELECT; 966 } 967 968 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 969 if (val % 100) { 970 dev_err(dev, "tx-delay must be a multiple of 100\n"); 971 return -EINVAL; 972 } 973 val /= 100; 974 dev_dbg(dev, "set tx-delay to %x\n", val); 975 if (val <= gmac->variant->tx_delay_max) { 976 reg &= ~(gmac->variant->tx_delay_max << 977 SYSCON_ETXDC_SHIFT); 978 reg |= (val << SYSCON_ETXDC_SHIFT); 979 } else { 980 dev_err(dev, "Invalid TX clock delay: %d\n", 981 val); 982 return -EINVAL; 983 } 984 } 985 986 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 987 if (val % 100) { 988 dev_err(dev, "rx-delay must be a multiple of 100\n"); 989 return -EINVAL; 990 } 991 val /= 100; 992 dev_dbg(dev, "set rx-delay to %x\n", val); 993 if (val <= gmac->variant->rx_delay_max) { 994 reg &= ~(gmac->variant->rx_delay_max << 995 SYSCON_ERXDC_SHIFT); 996 reg |= (val << SYSCON_ERXDC_SHIFT); 997 } else { 998 dev_err(dev, "Invalid RX clock delay: %d\n", 999 val); 1000 return -EINVAL; 1001 } 1002 } 1003 1004 /* Clear interface mode bits */ 1005 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 1006 if (gmac->variant->support_rmii) 1007 reg &= ~SYSCON_RMII_EN; 1008 1009 switch (plat->interface) { 1010 case PHY_INTERFACE_MODE_MII: 1011 /* default */ 1012 break; 1013 case PHY_INTERFACE_MODE_RGMII: 1014 case PHY_INTERFACE_MODE_RGMII_ID: 1015 case PHY_INTERFACE_MODE_RGMII_RXID: 1016 case PHY_INTERFACE_MODE_RGMII_TXID: 1017 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 1018 break; 1019 case PHY_INTERFACE_MODE_RMII: 1020 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 1021 break; 1022 default: 1023 dev_err(dev, "Unsupported interface mode: %s", 1024 phy_modes(plat->interface)); 1025 return -EINVAL; 1026 } 1027 1028 regmap_field_write(gmac->regmap_field, reg); 1029 1030 return 0; 1031 } 1032 1033 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 1034 { 1035 u32 reg = gmac->variant->default_syscon_value; 1036 1037 regmap_field_write(gmac->regmap_field, reg); 1038 } 1039 1040 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 1041 { 1042 struct sunxi_priv_data *gmac = priv; 1043 1044 if (gmac->variant->soc_has_internal_phy) 1045 sun8i_dwmac_unpower_internal_phy(gmac); 1046 1047 clk_disable_unprepare(gmac->tx_clk); 1048 1049 if (gmac->regulator) 1050 regulator_disable(gmac->regulator); 1051 } 1052 1053 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 1054 { 1055 u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 1056 1057 if (enable) 1058 value |= EMAC_LOOPBACK; 1059 else 1060 value &= ~EMAC_LOOPBACK; 1061 1062 writel(value, ioaddr + EMAC_BASIC_CTL0); 1063 } 1064 1065 static const struct stmmac_ops sun8i_dwmac_ops = { 1066 .core_init = sun8i_dwmac_core_init, 1067 .set_mac = sun8i_dwmac_set_mac, 1068 .dump_regs = sun8i_dwmac_dump_mac_regs, 1069 .rx_ipc = sun8i_dwmac_rx_ipc_enable, 1070 .set_filter = sun8i_dwmac_set_filter, 1071 .flow_ctrl = sun8i_dwmac_flow_ctrl, 1072 .set_umac_addr = sun8i_dwmac_set_umac_addr, 1073 .get_umac_addr = sun8i_dwmac_get_umac_addr, 1074 .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 1075 }; 1076 1077 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 1078 { 1079 struct mac_device_info *mac; 1080 struct stmmac_priv *priv = ppriv; 1081 1082 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 1083 if (!mac) 1084 return NULL; 1085 1086 mac->pcsr = priv->ioaddr; 1087 mac->mac = &sun8i_dwmac_ops; 1088 mac->dma = &sun8i_dwmac_dma_ops; 1089 1090 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1091 1092 /* The loopback bit seems to be re-set when link change 1093 * Simply mask it each time 1094 * Speed 10/100/1000 are set in BIT(2)/BIT(3) 1095 */ 1096 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 1097 mac->link.speed10 = EMAC_SPEED_10; 1098 mac->link.speed100 = EMAC_SPEED_100; 1099 mac->link.speed1000 = EMAC_SPEED_1000; 1100 mac->link.duplex = EMAC_DUPLEX_FULL; 1101 mac->mii.addr = EMAC_MDIO_CMD; 1102 mac->mii.data = EMAC_MDIO_DATA; 1103 mac->mii.reg_shift = 4; 1104 mac->mii.reg_mask = GENMASK(8, 4); 1105 mac->mii.addr_shift = 12; 1106 mac->mii.addr_mask = GENMASK(16, 12); 1107 mac->mii.clk_csr_shift = 20; 1108 mac->mii.clk_csr_mask = GENMASK(22, 20); 1109 mac->unicast_filter_entries = 8; 1110 1111 /* Synopsys Id is not available */ 1112 priv->synopsys_id = 0; 1113 1114 return mac; 1115 } 1116 1117 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 1118 { 1119 struct device_node *syscon_node; 1120 struct platform_device *syscon_pdev; 1121 struct regmap *regmap = NULL; 1122 1123 syscon_node = of_parse_phandle(node, "syscon", 0); 1124 if (!syscon_node) 1125 return ERR_PTR(-ENODEV); 1126 1127 syscon_pdev = of_find_device_by_node(syscon_node); 1128 if (!syscon_pdev) { 1129 /* platform device might not be probed yet */ 1130 regmap = ERR_PTR(-EPROBE_DEFER); 1131 goto out_put_node; 1132 } 1133 1134 /* If no regmap is found then the other device driver is at fault */ 1135 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 1136 if (!regmap) 1137 regmap = ERR_PTR(-EINVAL); 1138 1139 platform_device_put(syscon_pdev); 1140 out_put_node: 1141 of_node_put(syscon_node); 1142 return regmap; 1143 } 1144 1145 static int sun8i_dwmac_probe(struct platform_device *pdev) 1146 { 1147 struct plat_stmmacenet_data *plat_dat; 1148 struct stmmac_resources stmmac_res; 1149 struct sunxi_priv_data *gmac; 1150 struct device *dev = &pdev->dev; 1151 phy_interface_t interface; 1152 int ret; 1153 struct stmmac_priv *priv; 1154 struct net_device *ndev; 1155 struct regmap *regmap; 1156 1157 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1158 if (ret) 1159 return ret; 1160 1161 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 1162 if (!gmac) 1163 return -ENOMEM; 1164 1165 gmac->variant = of_device_get_match_data(&pdev->dev); 1166 if (!gmac->variant) { 1167 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 1168 return -EINVAL; 1169 } 1170 1171 gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 1172 if (IS_ERR(gmac->tx_clk)) { 1173 dev_err(dev, "Could not get TX clock\n"); 1174 return PTR_ERR(gmac->tx_clk); 1175 } 1176 1177 /* Optional regulator for PHY */ 1178 gmac->regulator = devm_regulator_get_optional(dev, "phy"); 1179 if (IS_ERR(gmac->regulator)) { 1180 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 1181 return -EPROBE_DEFER; 1182 dev_info(dev, "No regulator found\n"); 1183 gmac->regulator = NULL; 1184 } 1185 1186 /* The "GMAC clock control" register might be located in the 1187 * CCU address range (on the R40), or the system control address 1188 * range (on most other sun8i and later SoCs). 1189 * 1190 * The former controls most if not all clocks in the SoC. The 1191 * latter has an SoC identification register, and on some SoCs, 1192 * controls to map device specific SRAM to either the intended 1193 * peripheral, or the CPU address space. 1194 * 1195 * In either case, there should be a coordinated and restricted 1196 * method of accessing the register needed here. This is done by 1197 * having the device export a custom regmap, instead of a generic 1198 * syscon, which grants all access to all registers. 1199 * 1200 * To support old device trees, we fall back to using the syscon 1201 * interface if possible. 1202 */ 1203 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 1204 if (IS_ERR(regmap)) 1205 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1206 "syscon"); 1207 if (IS_ERR(regmap)) { 1208 ret = PTR_ERR(regmap); 1209 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 1210 return ret; 1211 } 1212 1213 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 1214 *gmac->variant->syscon_field); 1215 if (IS_ERR(gmac->regmap_field)) { 1216 ret = PTR_ERR(gmac->regmap_field); 1217 dev_err(dev, "Unable to map syscon register: %d\n", ret); 1218 return ret; 1219 } 1220 1221 ret = of_get_phy_mode(dev->of_node, &interface); 1222 if (ret) 1223 return -EINVAL; 1224 1225 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 1226 if (IS_ERR(plat_dat)) 1227 return PTR_ERR(plat_dat); 1228 1229 /* platform data specifying hardware features and callbacks. 1230 * hardware features were copied from Allwinner drivers. 1231 */ 1232 plat_dat->interface = interface; 1233 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 1234 plat_dat->tx_coe = 1; 1235 plat_dat->has_sun8i = true; 1236 plat_dat->bsp_priv = gmac; 1237 plat_dat->init = sun8i_dwmac_init; 1238 plat_dat->exit = sun8i_dwmac_exit; 1239 plat_dat->setup = sun8i_dwmac_setup; 1240 plat_dat->tx_fifo_size = 4096; 1241 plat_dat->rx_fifo_size = 16384; 1242 1243 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); 1244 if (ret) 1245 goto dwmac_deconfig; 1246 1247 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 1248 if (ret) 1249 goto dwmac_syscon; 1250 1251 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1252 if (ret) 1253 goto dwmac_exit; 1254 1255 ndev = dev_get_drvdata(&pdev->dev); 1256 priv = netdev_priv(ndev); 1257 1258 /* The mux must be registered after parent MDIO 1259 * so after stmmac_dvr_probe() 1260 */ 1261 if (gmac->variant->soc_has_internal_phy) { 1262 ret = get_ephy_nodes(priv); 1263 if (ret) 1264 goto dwmac_remove; 1265 ret = sun8i_dwmac_register_mdio_mux(priv); 1266 if (ret) { 1267 dev_err(&pdev->dev, "Failed to register mux\n"); 1268 goto dwmac_mux; 1269 } 1270 } else { 1271 ret = sun8i_dwmac_reset(priv); 1272 if (ret) 1273 goto dwmac_remove; 1274 } 1275 1276 return 0; 1277 1278 dwmac_mux: 1279 reset_control_put(gmac->rst_ephy); 1280 clk_put(gmac->ephy_clk); 1281 dwmac_remove: 1282 stmmac_dvr_remove(&pdev->dev); 1283 dwmac_exit: 1284 sun8i_dwmac_exit(pdev, gmac); 1285 dwmac_syscon: 1286 sun8i_dwmac_unset_syscon(gmac); 1287 dwmac_deconfig: 1288 stmmac_remove_config_dt(pdev, plat_dat); 1289 1290 return ret; 1291 } 1292 1293 static int sun8i_dwmac_remove(struct platform_device *pdev) 1294 { 1295 struct net_device *ndev = platform_get_drvdata(pdev); 1296 struct stmmac_priv *priv = netdev_priv(ndev); 1297 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1298 1299 if (gmac->variant->soc_has_internal_phy) { 1300 mdio_mux_uninit(gmac->mux_handle); 1301 sun8i_dwmac_unpower_internal_phy(gmac); 1302 reset_control_put(gmac->rst_ephy); 1303 clk_put(gmac->ephy_clk); 1304 } 1305 1306 stmmac_pltfr_remove(pdev); 1307 sun8i_dwmac_unset_syscon(gmac); 1308 1309 return 0; 1310 } 1311 1312 static void sun8i_dwmac_shutdown(struct platform_device *pdev) 1313 { 1314 struct net_device *ndev = platform_get_drvdata(pdev); 1315 struct stmmac_priv *priv = netdev_priv(ndev); 1316 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 1317 1318 sun8i_dwmac_exit(pdev, gmac); 1319 } 1320 1321 static const struct of_device_id sun8i_dwmac_match[] = { 1322 { .compatible = "allwinner,sun8i-h3-emac", 1323 .data = &emac_variant_h3 }, 1324 { .compatible = "allwinner,sun8i-v3s-emac", 1325 .data = &emac_variant_v3s }, 1326 { .compatible = "allwinner,sun8i-a83t-emac", 1327 .data = &emac_variant_a83t }, 1328 { .compatible = "allwinner,sun8i-r40-gmac", 1329 .data = &emac_variant_r40 }, 1330 { .compatible = "allwinner,sun50i-a64-emac", 1331 .data = &emac_variant_a64 }, 1332 { .compatible = "allwinner,sun50i-h6-emac", 1333 .data = &emac_variant_h6 }, 1334 { } 1335 }; 1336 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 1337 1338 static struct platform_driver sun8i_dwmac_driver = { 1339 .probe = sun8i_dwmac_probe, 1340 .remove = sun8i_dwmac_remove, 1341 .shutdown = sun8i_dwmac_shutdown, 1342 .driver = { 1343 .name = "dwmac-sun8i", 1344 .pm = &stmmac_pltfr_pm_ops, 1345 .of_match_table = sun8i_dwmac_match, 1346 }, 1347 }; 1348 module_platform_driver(sun8i_dwmac_driver); 1349 1350 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 1351 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 1352 MODULE_LICENSE("GPL"); 1353