1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 29f93ac8dSLABBE Corentin /* 39f93ac8dSLABBE Corentin * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 49f93ac8dSLABBE Corentin * 59f93ac8dSLABBE Corentin * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 69f93ac8dSLABBE Corentin */ 79f93ac8dSLABBE Corentin 89f93ac8dSLABBE Corentin #include <linux/clk.h> 99f93ac8dSLABBE Corentin #include <linux/io.h> 109f93ac8dSLABBE Corentin #include <linux/iopoll.h> 11634db83bSCorentin Labbe #include <linux/mdio-mux.h> 129f93ac8dSLABBE Corentin #include <linux/mfd/syscon.h> 139f93ac8dSLABBE Corentin #include <linux/module.h> 149f93ac8dSLABBE Corentin #include <linux/of_device.h> 159f93ac8dSLABBE Corentin #include <linux/of_mdio.h> 169f93ac8dSLABBE Corentin #include <linux/of_net.h> 179f93ac8dSLABBE Corentin #include <linux/phy.h> 189f93ac8dSLABBE Corentin #include <linux/platform_device.h> 199f93ac8dSLABBE Corentin #include <linux/regulator/consumer.h> 209f93ac8dSLABBE Corentin #include <linux/regmap.h> 219f93ac8dSLABBE Corentin #include <linux/stmmac.h> 229f93ac8dSLABBE Corentin 239f93ac8dSLABBE Corentin #include "stmmac.h" 249f93ac8dSLABBE Corentin #include "stmmac_platform.h" 259f93ac8dSLABBE Corentin 269f93ac8dSLABBE Corentin /* General notes on dwmac-sun8i: 279f93ac8dSLABBE Corentin * Locking: no locking is necessary in this file because all necessary locking 289f93ac8dSLABBE Corentin * is done in the "stmmac files" 299f93ac8dSLABBE Corentin */ 309f93ac8dSLABBE Corentin 3156c266dcSCorentin Labbe /* struct emac_variant - Describe dwmac-sun8i hardware variant 329f93ac8dSLABBE Corentin * @default_syscon_value: The default value of the EMAC register in syscon 339f93ac8dSLABBE Corentin * This value is used for disabling properly EMAC 349f93ac8dSLABBE Corentin * and used as a good starting value in case of the 359f93ac8dSLABBE Corentin * boot process(uboot) leave some stuff. 3625ae15fbSChen-Yu Tsai * @syscon_field reg_field for the syscon's gmac register 37634db83bSCorentin Labbe * @soc_has_internal_phy: Does the MAC embed an internal PHY 389f93ac8dSLABBE Corentin * @support_mii: Does the MAC handle MII 399f93ac8dSLABBE Corentin * @support_rmii: Does the MAC handle RMII 409f93ac8dSLABBE Corentin * @support_rgmii: Does the MAC handle RGMII 417b270b72SChen-Yu Tsai * 427b270b72SChen-Yu Tsai * @rx_delay_max: Maximum raw value for RX delay chain 437b270b72SChen-Yu Tsai * @tx_delay_max: Maximum raw value for TX delay chain 447b270b72SChen-Yu Tsai * These two also indicate the bitmask for 457b270b72SChen-Yu Tsai * the RX and TX delay chain registers. A 467b270b72SChen-Yu Tsai * value of zero indicates this is not supported. 479f93ac8dSLABBE Corentin */ 489f93ac8dSLABBE Corentin struct emac_variant { 499f93ac8dSLABBE Corentin u32 default_syscon_value; 5025ae15fbSChen-Yu Tsai const struct reg_field *syscon_field; 51634db83bSCorentin Labbe bool soc_has_internal_phy; 529f93ac8dSLABBE Corentin bool support_mii; 539f93ac8dSLABBE Corentin bool support_rmii; 549f93ac8dSLABBE Corentin bool support_rgmii; 557b270b72SChen-Yu Tsai u8 rx_delay_max; 567b270b72SChen-Yu Tsai u8 tx_delay_max; 579f93ac8dSLABBE Corentin }; 589f93ac8dSLABBE Corentin 599f93ac8dSLABBE Corentin /* struct sunxi_priv_data - hold all sunxi private data 609f93ac8dSLABBE Corentin * @tx_clk: reference to MAC TX clock 619f93ac8dSLABBE Corentin * @ephy_clk: reference to the optional EPHY clock for the internal PHY 629f93ac8dSLABBE Corentin * @regulator: reference to the optional regulator 639f93ac8dSLABBE Corentin * @rst_ephy: reference to the optional EPHY reset for the internal PHY 649f93ac8dSLABBE Corentin * @variant: reference to the current board variant 659f93ac8dSLABBE Corentin * @regmap: regmap for using the syscon 66634db83bSCorentin Labbe * @internal_phy_powered: Does the internal PHY is enabled 67634db83bSCorentin Labbe * @mux_handle: Internal pointer used by mdio-mux lib 689f93ac8dSLABBE Corentin */ 699f93ac8dSLABBE Corentin struct sunxi_priv_data { 709f93ac8dSLABBE Corentin struct clk *tx_clk; 719f93ac8dSLABBE Corentin struct clk *ephy_clk; 729f93ac8dSLABBE Corentin struct regulator *regulator; 739f93ac8dSLABBE Corentin struct reset_control *rst_ephy; 749f93ac8dSLABBE Corentin const struct emac_variant *variant; 7525ae15fbSChen-Yu Tsai struct regmap_field *regmap_field; 76634db83bSCorentin Labbe bool internal_phy_powered; 77634db83bSCorentin Labbe void *mux_handle; 789f93ac8dSLABBE Corentin }; 799f93ac8dSLABBE Corentin 8025ae15fbSChen-Yu Tsai /* EMAC clock register @ 0x30 in the "system control" address range */ 8125ae15fbSChen-Yu Tsai static const struct reg_field sun8i_syscon_reg_field = { 8225ae15fbSChen-Yu Tsai .reg = 0x30, 8325ae15fbSChen-Yu Tsai .lsb = 0, 8425ae15fbSChen-Yu Tsai .msb = 31, 8525ae15fbSChen-Yu Tsai }; 8625ae15fbSChen-Yu Tsai 879bf5085aSChen-Yu Tsai /* EMAC clock register @ 0x164 in the CCU address range */ 889bf5085aSChen-Yu Tsai static const struct reg_field sun8i_ccu_reg_field = { 899bf5085aSChen-Yu Tsai .reg = 0x164, 909bf5085aSChen-Yu Tsai .lsb = 0, 919bf5085aSChen-Yu Tsai .msb = 31, 929bf5085aSChen-Yu Tsai }; 939bf5085aSChen-Yu Tsai 949f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_h3 = { 959f93ac8dSLABBE Corentin .default_syscon_value = 0x58000, 9625ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 97634db83bSCorentin Labbe .soc_has_internal_phy = true, 989f93ac8dSLABBE Corentin .support_mii = true, 999f93ac8dSLABBE Corentin .support_rmii = true, 1007b270b72SChen-Yu Tsai .support_rgmii = true, 1017b270b72SChen-Yu Tsai .rx_delay_max = 31, 1027b270b72SChen-Yu Tsai .tx_delay_max = 7, 1039f93ac8dSLABBE Corentin }; 1049f93ac8dSLABBE Corentin 10557fde47dSIcenowy Zheng static const struct emac_variant emac_variant_v3s = { 10657fde47dSIcenowy Zheng .default_syscon_value = 0x38000, 10725ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 108634db83bSCorentin Labbe .soc_has_internal_phy = true, 10957fde47dSIcenowy Zheng .support_mii = true 11057fde47dSIcenowy Zheng }; 11157fde47dSIcenowy Zheng 1129f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_a83t = { 1139f93ac8dSLABBE Corentin .default_syscon_value = 0, 11425ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 115634db83bSCorentin Labbe .soc_has_internal_phy = false, 1169f93ac8dSLABBE Corentin .support_mii = true, 1177b270b72SChen-Yu Tsai .support_rgmii = true, 1187b270b72SChen-Yu Tsai .rx_delay_max = 31, 1197b270b72SChen-Yu Tsai .tx_delay_max = 7, 1209f93ac8dSLABBE Corentin }; 1219f93ac8dSLABBE Corentin 1229bf5085aSChen-Yu Tsai static const struct emac_variant emac_variant_r40 = { 1239bf5085aSChen-Yu Tsai .default_syscon_value = 0, 1249bf5085aSChen-Yu Tsai .syscon_field = &sun8i_ccu_reg_field, 1259bf5085aSChen-Yu Tsai .support_mii = true, 1269bf5085aSChen-Yu Tsai .support_rgmii = true, 1279bf5085aSChen-Yu Tsai .rx_delay_max = 7, 1289bf5085aSChen-Yu Tsai }; 1299bf5085aSChen-Yu Tsai 1309f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_a64 = { 1319f93ac8dSLABBE Corentin .default_syscon_value = 0, 13225ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 133634db83bSCorentin Labbe .soc_has_internal_phy = false, 1349f93ac8dSLABBE Corentin .support_mii = true, 1359f93ac8dSLABBE Corentin .support_rmii = true, 1367b270b72SChen-Yu Tsai .support_rgmii = true, 1377b270b72SChen-Yu Tsai .rx_delay_max = 31, 1387b270b72SChen-Yu Tsai .tx_delay_max = 7, 1399f93ac8dSLABBE Corentin }; 1409f93ac8dSLABBE Corentin 141adadd38cSIcenowy Zheng static const struct emac_variant emac_variant_h6 = { 142adadd38cSIcenowy Zheng .default_syscon_value = 0x50000, 143adadd38cSIcenowy Zheng .syscon_field = &sun8i_syscon_reg_field, 144adadd38cSIcenowy Zheng /* The "Internal PHY" of H6 is not on the die. It's on the 145adadd38cSIcenowy Zheng * co-packaged AC200 chip instead. 146adadd38cSIcenowy Zheng */ 147adadd38cSIcenowy Zheng .soc_has_internal_phy = false, 148adadd38cSIcenowy Zheng .support_mii = true, 149adadd38cSIcenowy Zheng .support_rmii = true, 150adadd38cSIcenowy Zheng .support_rgmii = true, 151adadd38cSIcenowy Zheng .rx_delay_max = 31, 152adadd38cSIcenowy Zheng .tx_delay_max = 7, 153adadd38cSIcenowy Zheng }; 154adadd38cSIcenowy Zheng 1559f93ac8dSLABBE Corentin #define EMAC_BASIC_CTL0 0x00 1569f93ac8dSLABBE Corentin #define EMAC_BASIC_CTL1 0x04 1579f93ac8dSLABBE Corentin #define EMAC_INT_STA 0x08 1589f93ac8dSLABBE Corentin #define EMAC_INT_EN 0x0C 1599f93ac8dSLABBE Corentin #define EMAC_TX_CTL0 0x10 1609f93ac8dSLABBE Corentin #define EMAC_TX_CTL1 0x14 1619f93ac8dSLABBE Corentin #define EMAC_TX_FLOW_CTL 0x1C 1629f93ac8dSLABBE Corentin #define EMAC_TX_DESC_LIST 0x20 1639f93ac8dSLABBE Corentin #define EMAC_RX_CTL0 0x24 1649f93ac8dSLABBE Corentin #define EMAC_RX_CTL1 0x28 1659f93ac8dSLABBE Corentin #define EMAC_RX_DESC_LIST 0x34 1669f93ac8dSLABBE Corentin #define EMAC_RX_FRM_FLT 0x38 1679f93ac8dSLABBE Corentin #define EMAC_MDIO_CMD 0x48 1689f93ac8dSLABBE Corentin #define EMAC_MDIO_DATA 0x4C 1699f93ac8dSLABBE Corentin #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 1709f93ac8dSLABBE Corentin #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 1719f93ac8dSLABBE Corentin #define EMAC_TX_DMA_STA 0xB0 1729f93ac8dSLABBE Corentin #define EMAC_TX_CUR_DESC 0xB4 1739f93ac8dSLABBE Corentin #define EMAC_TX_CUR_BUF 0xB8 1749f93ac8dSLABBE Corentin #define EMAC_RX_DMA_STA 0xC0 1759f93ac8dSLABBE Corentin #define EMAC_RX_CUR_DESC 0xC4 1769f93ac8dSLABBE Corentin #define EMAC_RX_CUR_BUF 0xC8 1779f93ac8dSLABBE Corentin 1789f93ac8dSLABBE Corentin /* Use in EMAC_BASIC_CTL0 */ 1799f93ac8dSLABBE Corentin #define EMAC_DUPLEX_FULL BIT(0) 1809f93ac8dSLABBE Corentin #define EMAC_LOOPBACK BIT(1) 1819f93ac8dSLABBE Corentin #define EMAC_SPEED_1000 0 1829f93ac8dSLABBE Corentin #define EMAC_SPEED_100 (0x03 << 2) 1839f93ac8dSLABBE Corentin #define EMAC_SPEED_10 (0x02 << 2) 1849f93ac8dSLABBE Corentin 1859f93ac8dSLABBE Corentin /* Use in EMAC_BASIC_CTL1 */ 1869f93ac8dSLABBE Corentin #define EMAC_BURSTLEN_SHIFT 24 1879f93ac8dSLABBE Corentin 1889f93ac8dSLABBE Corentin /* Used in EMAC_RX_FRM_FLT */ 1899f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_RXALL BIT(0) 1909f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_CTL BIT(13) 1919f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_MULTICAST BIT(16) 1929f93ac8dSLABBE Corentin 1939f93ac8dSLABBE Corentin /* Used in RX_CTL1*/ 1949f93ac8dSLABBE Corentin #define EMAC_RX_MD BIT(1) 1959f93ac8dSLABBE Corentin #define EMAC_RX_TH_MASK GENMASK(4, 5) 1969f93ac8dSLABBE Corentin #define EMAC_RX_TH_32 0 1979f93ac8dSLABBE Corentin #define EMAC_RX_TH_64 (0x1 << 4) 1989f93ac8dSLABBE Corentin #define EMAC_RX_TH_96 (0x2 << 4) 1999f93ac8dSLABBE Corentin #define EMAC_RX_TH_128 (0x3 << 4) 2009f93ac8dSLABBE Corentin #define EMAC_RX_DMA_EN BIT(30) 2019f93ac8dSLABBE Corentin #define EMAC_RX_DMA_START BIT(31) 2029f93ac8dSLABBE Corentin 2039f93ac8dSLABBE Corentin /* Used in TX_CTL1*/ 2049f93ac8dSLABBE Corentin #define EMAC_TX_MD BIT(1) 2059f93ac8dSLABBE Corentin #define EMAC_TX_NEXT_FRM BIT(2) 2069f93ac8dSLABBE Corentin #define EMAC_TX_TH_MASK GENMASK(8, 10) 2079f93ac8dSLABBE Corentin #define EMAC_TX_TH_64 0 2089f93ac8dSLABBE Corentin #define EMAC_TX_TH_128 (0x1 << 8) 2099f93ac8dSLABBE Corentin #define EMAC_TX_TH_192 (0x2 << 8) 2109f93ac8dSLABBE Corentin #define EMAC_TX_TH_256 (0x3 << 8) 2119f93ac8dSLABBE Corentin #define EMAC_TX_DMA_EN BIT(30) 2129f93ac8dSLABBE Corentin #define EMAC_TX_DMA_START BIT(31) 2139f93ac8dSLABBE Corentin 2149f93ac8dSLABBE Corentin /* Used in RX_CTL0 */ 2159f93ac8dSLABBE Corentin #define EMAC_RX_RECEIVER_EN BIT(31) 2169f93ac8dSLABBE Corentin #define EMAC_RX_DO_CRC BIT(27) 2179f93ac8dSLABBE Corentin #define EMAC_RX_FLOW_CTL_EN BIT(16) 2189f93ac8dSLABBE Corentin 2199f93ac8dSLABBE Corentin /* Used in TX_CTL0 */ 2209f93ac8dSLABBE Corentin #define EMAC_TX_TRANSMITTER_EN BIT(31) 2219f93ac8dSLABBE Corentin 2229f93ac8dSLABBE Corentin /* Used in EMAC_TX_FLOW_CTL */ 2239f93ac8dSLABBE Corentin #define EMAC_TX_FLOW_CTL_EN BIT(0) 2249f93ac8dSLABBE Corentin 2259f93ac8dSLABBE Corentin /* Used in EMAC_INT_STA */ 2269f93ac8dSLABBE Corentin #define EMAC_TX_INT BIT(0) 2279f93ac8dSLABBE Corentin #define EMAC_TX_DMA_STOP_INT BIT(1) 2289f93ac8dSLABBE Corentin #define EMAC_TX_BUF_UA_INT BIT(2) 2299f93ac8dSLABBE Corentin #define EMAC_TX_TIMEOUT_INT BIT(3) 2309f93ac8dSLABBE Corentin #define EMAC_TX_UNDERFLOW_INT BIT(4) 2319f93ac8dSLABBE Corentin #define EMAC_TX_EARLY_INT BIT(5) 2329f93ac8dSLABBE Corentin #define EMAC_RX_INT BIT(8) 2339f93ac8dSLABBE Corentin #define EMAC_RX_BUF_UA_INT BIT(9) 2349f93ac8dSLABBE Corentin #define EMAC_RX_DMA_STOP_INT BIT(10) 2359f93ac8dSLABBE Corentin #define EMAC_RX_TIMEOUT_INT BIT(11) 2369f93ac8dSLABBE Corentin #define EMAC_RX_OVERFLOW_INT BIT(12) 2379f93ac8dSLABBE Corentin #define EMAC_RX_EARLY_INT BIT(13) 2389f93ac8dSLABBE Corentin #define EMAC_RGMII_STA_INT BIT(16) 2399f93ac8dSLABBE Corentin 2409f93ac8dSLABBE Corentin #define MAC_ADDR_TYPE_DST BIT(31) 2419f93ac8dSLABBE Corentin 2429f93ac8dSLABBE Corentin /* H3 specific bits for EPHY */ 2439f93ac8dSLABBE Corentin #define H3_EPHY_ADDR_SHIFT 20 2441450ba8aSIcenowy Zheng #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 2459f93ac8dSLABBE Corentin #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 2469f93ac8dSLABBE Corentin #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 2479f93ac8dSLABBE Corentin #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 248634db83bSCorentin Labbe #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 249634db83bSCorentin Labbe #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 250634db83bSCorentin Labbe #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 2519f93ac8dSLABBE Corentin 2529f93ac8dSLABBE Corentin /* H3/A64 specific bits */ 2539f93ac8dSLABBE Corentin #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 2549f93ac8dSLABBE Corentin 2559f93ac8dSLABBE Corentin /* Generic system control EMAC_CLK bits */ 2569f93ac8dSLABBE Corentin #define SYSCON_ETXDC_SHIFT 10 2579f93ac8dSLABBE Corentin #define SYSCON_ERXDC_SHIFT 5 2589f93ac8dSLABBE Corentin /* EMAC PHY Interface Type */ 2599f93ac8dSLABBE Corentin #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 2609f93ac8dSLABBE Corentin #define SYSCON_ETCS_MASK GENMASK(1, 0) 2619f93ac8dSLABBE Corentin #define SYSCON_ETCS_MII 0x0 2629f93ac8dSLABBE Corentin #define SYSCON_ETCS_EXT_GMII 0x1 2639f93ac8dSLABBE Corentin #define SYSCON_ETCS_INT_GMII 0x2 2649f93ac8dSLABBE Corentin 2659f93ac8dSLABBE Corentin /* sun8i_dwmac_dma_reset() - reset the EMAC 2669f93ac8dSLABBE Corentin * Called from stmmac via stmmac_dma_ops->reset 2679f93ac8dSLABBE Corentin */ 2689f93ac8dSLABBE Corentin static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 2699f93ac8dSLABBE Corentin { 2709f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_CTL1); 2719f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_TX_CTL1); 2729f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_FRM_FLT); 2739f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_DESC_LIST); 2749f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_TX_DESC_LIST); 2759f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_INT_EN); 2769f93ac8dSLABBE Corentin writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 2779f93ac8dSLABBE Corentin return 0; 2789f93ac8dSLABBE Corentin } 2799f93ac8dSLABBE Corentin 2809f93ac8dSLABBE Corentin /* sun8i_dwmac_dma_init() - initialize the EMAC 2819f93ac8dSLABBE Corentin * Called from stmmac via stmmac_dma_ops->init 2829f93ac8dSLABBE Corentin */ 2839f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 28424aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 2859f93ac8dSLABBE Corentin { 2869f93ac8dSLABBE Corentin writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 2879f93ac8dSLABBE Corentin writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 2889f93ac8dSLABBE Corentin } 2899f93ac8dSLABBE Corentin 29024aaed0cSJose Abreu static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 29124aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, 29224aaed0cSJose Abreu u32 dma_rx_phy, u32 chan) 29324aaed0cSJose Abreu { 29424aaed0cSJose Abreu /* Write RX descriptors address */ 29524aaed0cSJose Abreu writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST); 29624aaed0cSJose Abreu } 29724aaed0cSJose Abreu 29824aaed0cSJose Abreu static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 29924aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, 30024aaed0cSJose Abreu u32 dma_tx_phy, u32 chan) 30124aaed0cSJose Abreu { 30224aaed0cSJose Abreu /* Write TX descriptors address */ 30324aaed0cSJose Abreu writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST); 30424aaed0cSJose Abreu } 30524aaed0cSJose Abreu 3069f93ac8dSLABBE Corentin /* sun8i_dwmac_dump_regs() - Dump EMAC address space 3079f93ac8dSLABBE Corentin * Called from stmmac_dma_ops->dump_regs 3089f93ac8dSLABBE Corentin * Used for ethtool 3099f93ac8dSLABBE Corentin */ 3109f93ac8dSLABBE Corentin static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 3119f93ac8dSLABBE Corentin { 3129f93ac8dSLABBE Corentin int i; 3139f93ac8dSLABBE Corentin 3149f93ac8dSLABBE Corentin for (i = 0; i < 0xC8; i += 4) { 3159f93ac8dSLABBE Corentin if (i == 0x32 || i == 0x3C) 3169f93ac8dSLABBE Corentin continue; 3179f93ac8dSLABBE Corentin reg_space[i / 4] = readl(ioaddr + i); 3189f93ac8dSLABBE Corentin } 3199f93ac8dSLABBE Corentin } 3209f93ac8dSLABBE Corentin 3219f93ac8dSLABBE Corentin /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 3229f93ac8dSLABBE Corentin * Called from stmmac_ops->dump_regs 3239f93ac8dSLABBE Corentin * Used for ethtool 3249f93ac8dSLABBE Corentin */ 3259f93ac8dSLABBE Corentin static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 3269f93ac8dSLABBE Corentin u32 *reg_space) 3279f93ac8dSLABBE Corentin { 3289f93ac8dSLABBE Corentin int i; 3299f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 3309f93ac8dSLABBE Corentin 3319f93ac8dSLABBE Corentin for (i = 0; i < 0xC8; i += 4) { 3329f93ac8dSLABBE Corentin if (i == 0x32 || i == 0x3C) 3339f93ac8dSLABBE Corentin continue; 3349f93ac8dSLABBE Corentin reg_space[i / 4] = readl(ioaddr + i); 3359f93ac8dSLABBE Corentin } 3369f93ac8dSLABBE Corentin } 3379f93ac8dSLABBE Corentin 3389f93ac8dSLABBE Corentin static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) 3399f93ac8dSLABBE Corentin { 3409f93ac8dSLABBE Corentin writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 3419f93ac8dSLABBE Corentin } 3429f93ac8dSLABBE Corentin 3439f93ac8dSLABBE Corentin static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 3449f93ac8dSLABBE Corentin { 3459f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_INT_EN); 3469f93ac8dSLABBE Corentin } 3479f93ac8dSLABBE Corentin 3489f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 3499f93ac8dSLABBE Corentin { 3509f93ac8dSLABBE Corentin u32 v; 3519f93ac8dSLABBE Corentin 3529f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3539f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_START; 3549f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_EN; 3559f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3569f93ac8dSLABBE Corentin } 3579f93ac8dSLABBE Corentin 3589f93ac8dSLABBE Corentin static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 3599f93ac8dSLABBE Corentin { 3609f93ac8dSLABBE Corentin u32 v; 3619f93ac8dSLABBE Corentin 3629f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3639f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_START; 3649f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_EN; 3659f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3669f93ac8dSLABBE Corentin } 3679f93ac8dSLABBE Corentin 3689f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 3699f93ac8dSLABBE Corentin { 3709f93ac8dSLABBE Corentin u32 v; 3719f93ac8dSLABBE Corentin 3729f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3739f93ac8dSLABBE Corentin v &= ~EMAC_TX_DMA_EN; 3749f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3759f93ac8dSLABBE Corentin } 3769f93ac8dSLABBE Corentin 3779f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 3789f93ac8dSLABBE Corentin { 3799f93ac8dSLABBE Corentin u32 v; 3809f93ac8dSLABBE Corentin 3819f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 3829f93ac8dSLABBE Corentin v |= EMAC_RX_DMA_START; 3839f93ac8dSLABBE Corentin v |= EMAC_RX_DMA_EN; 3849f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 3859f93ac8dSLABBE Corentin } 3869f93ac8dSLABBE Corentin 3879f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 3889f93ac8dSLABBE Corentin { 3899f93ac8dSLABBE Corentin u32 v; 3909f93ac8dSLABBE Corentin 3919f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 3929f93ac8dSLABBE Corentin v &= ~EMAC_RX_DMA_EN; 3939f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 3949f93ac8dSLABBE Corentin } 3959f93ac8dSLABBE Corentin 3969f93ac8dSLABBE Corentin static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 3979f93ac8dSLABBE Corentin struct stmmac_extra_stats *x, u32 chan) 3989f93ac8dSLABBE Corentin { 3999f93ac8dSLABBE Corentin u32 v; 4009f93ac8dSLABBE Corentin int ret = 0; 4019f93ac8dSLABBE Corentin 4029f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_INT_STA); 4039f93ac8dSLABBE Corentin 4049f93ac8dSLABBE Corentin if (v & EMAC_TX_INT) { 4059f93ac8dSLABBE Corentin ret |= handle_tx; 4069f93ac8dSLABBE Corentin x->tx_normal_irq_n++; 4079f93ac8dSLABBE Corentin } 4089f93ac8dSLABBE Corentin 4099f93ac8dSLABBE Corentin if (v & EMAC_TX_DMA_STOP_INT) 4109f93ac8dSLABBE Corentin x->tx_process_stopped_irq++; 4119f93ac8dSLABBE Corentin 4129f93ac8dSLABBE Corentin if (v & EMAC_TX_BUF_UA_INT) 4139f93ac8dSLABBE Corentin x->tx_process_stopped_irq++; 4149f93ac8dSLABBE Corentin 4159f93ac8dSLABBE Corentin if (v & EMAC_TX_TIMEOUT_INT) 4169f93ac8dSLABBE Corentin ret |= tx_hard_error; 4179f93ac8dSLABBE Corentin 4189f93ac8dSLABBE Corentin if (v & EMAC_TX_UNDERFLOW_INT) { 4199f93ac8dSLABBE Corentin ret |= tx_hard_error; 4209f93ac8dSLABBE Corentin x->tx_undeflow_irq++; 4219f93ac8dSLABBE Corentin } 4229f93ac8dSLABBE Corentin 4239f93ac8dSLABBE Corentin if (v & EMAC_TX_EARLY_INT) 4249f93ac8dSLABBE Corentin x->tx_early_irq++; 4259f93ac8dSLABBE Corentin 4269f93ac8dSLABBE Corentin if (v & EMAC_RX_INT) { 4279f93ac8dSLABBE Corentin ret |= handle_rx; 4289f93ac8dSLABBE Corentin x->rx_normal_irq_n++; 4299f93ac8dSLABBE Corentin } 4309f93ac8dSLABBE Corentin 4319f93ac8dSLABBE Corentin if (v & EMAC_RX_BUF_UA_INT) 4329f93ac8dSLABBE Corentin x->rx_buf_unav_irq++; 4339f93ac8dSLABBE Corentin 4349f93ac8dSLABBE Corentin if (v & EMAC_RX_DMA_STOP_INT) 4359f93ac8dSLABBE Corentin x->rx_process_stopped_irq++; 4369f93ac8dSLABBE Corentin 4379f93ac8dSLABBE Corentin if (v & EMAC_RX_TIMEOUT_INT) 4389f93ac8dSLABBE Corentin ret |= tx_hard_error; 4399f93ac8dSLABBE Corentin 4409f93ac8dSLABBE Corentin if (v & EMAC_RX_OVERFLOW_INT) { 4419f93ac8dSLABBE Corentin ret |= tx_hard_error; 4429f93ac8dSLABBE Corentin x->rx_overflow_irq++; 4439f93ac8dSLABBE Corentin } 4449f93ac8dSLABBE Corentin 4459f93ac8dSLABBE Corentin if (v & EMAC_RX_EARLY_INT) 4469f93ac8dSLABBE Corentin x->rx_early_irq++; 4479f93ac8dSLABBE Corentin 4489f93ac8dSLABBE Corentin if (v & EMAC_RGMII_STA_INT) 4499f93ac8dSLABBE Corentin x->irq_rgmii_n++; 4509f93ac8dSLABBE Corentin 4519f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_INT_STA); 4529f93ac8dSLABBE Corentin 4539f93ac8dSLABBE Corentin return ret; 4549f93ac8dSLABBE Corentin } 4559f93ac8dSLABBE Corentin 456ab0204e3SJose Abreu static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 457ab0204e3SJose Abreu u32 channel, int fifosz, u8 qmode) 458ab0204e3SJose Abreu { 459ab0204e3SJose Abreu u32 v; 460ab0204e3SJose Abreu 461ab0204e3SJose Abreu v = readl(ioaddr + EMAC_RX_CTL1); 462ab0204e3SJose Abreu if (mode == SF_DMA_MODE) { 463ab0204e3SJose Abreu v |= EMAC_RX_MD; 464ab0204e3SJose Abreu } else { 465ab0204e3SJose Abreu v &= ~EMAC_RX_MD; 466ab0204e3SJose Abreu v &= ~EMAC_RX_TH_MASK; 467ab0204e3SJose Abreu if (mode < 32) 468ab0204e3SJose Abreu v |= EMAC_RX_TH_32; 469ab0204e3SJose Abreu else if (mode < 64) 470ab0204e3SJose Abreu v |= EMAC_RX_TH_64; 471ab0204e3SJose Abreu else if (mode < 96) 472ab0204e3SJose Abreu v |= EMAC_RX_TH_96; 473ab0204e3SJose Abreu else if (mode < 128) 474ab0204e3SJose Abreu v |= EMAC_RX_TH_128; 475ab0204e3SJose Abreu } 476ab0204e3SJose Abreu writel(v, ioaddr + EMAC_RX_CTL1); 477ab0204e3SJose Abreu } 478ab0204e3SJose Abreu 479ab0204e3SJose Abreu static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 480ab0204e3SJose Abreu u32 channel, int fifosz, u8 qmode) 4819f93ac8dSLABBE Corentin { 4829f93ac8dSLABBE Corentin u32 v; 4839f93ac8dSLABBE Corentin 4849f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 485ab0204e3SJose Abreu if (mode == SF_DMA_MODE) { 4869f93ac8dSLABBE Corentin v |= EMAC_TX_MD; 4879f93ac8dSLABBE Corentin /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 4889f93ac8dSLABBE Corentin * comment is 4899f93ac8dSLABBE Corentin * "Operating on second frame increase the performance 4909f93ac8dSLABBE Corentin * especially when transmit store-and-forward is used." 4919f93ac8dSLABBE Corentin */ 4929f93ac8dSLABBE Corentin v |= EMAC_TX_NEXT_FRM; 4939f93ac8dSLABBE Corentin } else { 4949f93ac8dSLABBE Corentin v &= ~EMAC_TX_MD; 4959f93ac8dSLABBE Corentin v &= ~EMAC_TX_TH_MASK; 496ab0204e3SJose Abreu if (mode < 64) 4979f93ac8dSLABBE Corentin v |= EMAC_TX_TH_64; 498ab0204e3SJose Abreu else if (mode < 128) 4999f93ac8dSLABBE Corentin v |= EMAC_TX_TH_128; 500ab0204e3SJose Abreu else if (mode < 192) 5019f93ac8dSLABBE Corentin v |= EMAC_TX_TH_192; 502ab0204e3SJose Abreu else if (mode < 256) 5039f93ac8dSLABBE Corentin v |= EMAC_TX_TH_256; 5049f93ac8dSLABBE Corentin } 5059f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 5069f93ac8dSLABBE Corentin } 5079f93ac8dSLABBE Corentin 5089f93ac8dSLABBE Corentin static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 5099f93ac8dSLABBE Corentin .reset = sun8i_dwmac_dma_reset, 5109f93ac8dSLABBE Corentin .init = sun8i_dwmac_dma_init, 51124aaed0cSJose Abreu .init_rx_chan = sun8i_dwmac_dma_init_rx, 51224aaed0cSJose Abreu .init_tx_chan = sun8i_dwmac_dma_init_tx, 5139f93ac8dSLABBE Corentin .dump_regs = sun8i_dwmac_dump_regs, 514ab0204e3SJose Abreu .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 515ab0204e3SJose Abreu .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 5169f93ac8dSLABBE Corentin .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 5179f93ac8dSLABBE Corentin .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 5189f93ac8dSLABBE Corentin .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 5199f93ac8dSLABBE Corentin .start_tx = sun8i_dwmac_dma_start_tx, 5209f93ac8dSLABBE Corentin .stop_tx = sun8i_dwmac_dma_stop_tx, 5219f93ac8dSLABBE Corentin .start_rx = sun8i_dwmac_dma_start_rx, 5229f93ac8dSLABBE Corentin .stop_rx = sun8i_dwmac_dma_stop_rx, 5239f93ac8dSLABBE Corentin .dma_interrupt = sun8i_dwmac_dma_interrupt, 5249f93ac8dSLABBE Corentin }; 5259f93ac8dSLABBE Corentin 5269f93ac8dSLABBE Corentin static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 5279f93ac8dSLABBE Corentin { 5289f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv; 5299f93ac8dSLABBE Corentin int ret; 5309f93ac8dSLABBE Corentin 5319f93ac8dSLABBE Corentin if (gmac->regulator) { 5329f93ac8dSLABBE Corentin ret = regulator_enable(gmac->regulator); 5339f93ac8dSLABBE Corentin if (ret) { 5349f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Fail to enable regulator\n"); 5359f93ac8dSLABBE Corentin return ret; 5369f93ac8dSLABBE Corentin } 5379f93ac8dSLABBE Corentin } 5389f93ac8dSLABBE Corentin 5399f93ac8dSLABBE Corentin ret = clk_prepare_enable(gmac->tx_clk); 5409f93ac8dSLABBE Corentin if (ret) { 5419f93ac8dSLABBE Corentin if (gmac->regulator) 5429f93ac8dSLABBE Corentin regulator_disable(gmac->regulator); 5439f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Could not enable AHB clock\n"); 5449f93ac8dSLABBE Corentin return ret; 5459f93ac8dSLABBE Corentin } 5469f93ac8dSLABBE Corentin 5479f93ac8dSLABBE Corentin return 0; 5489f93ac8dSLABBE Corentin } 5499f93ac8dSLABBE Corentin 5508cad443eSFlorian Fainelli static void sun8i_dwmac_core_init(struct mac_device_info *hw, 5518cad443eSFlorian Fainelli struct net_device *dev) 5529f93ac8dSLABBE Corentin { 5539f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5549f93ac8dSLABBE Corentin u32 v; 5559f93ac8dSLABBE Corentin 5569f93ac8dSLABBE Corentin v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 5579f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_BASIC_CTL1); 5589f93ac8dSLABBE Corentin } 5599f93ac8dSLABBE Corentin 5609f93ac8dSLABBE Corentin static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 5619f93ac8dSLABBE Corentin { 5629f93ac8dSLABBE Corentin u32 t, r; 5639f93ac8dSLABBE Corentin 5649f93ac8dSLABBE Corentin t = readl(ioaddr + EMAC_TX_CTL0); 5659f93ac8dSLABBE Corentin r = readl(ioaddr + EMAC_RX_CTL0); 5669f93ac8dSLABBE Corentin if (enable) { 5679f93ac8dSLABBE Corentin t |= EMAC_TX_TRANSMITTER_EN; 5689f93ac8dSLABBE Corentin r |= EMAC_RX_RECEIVER_EN; 5699f93ac8dSLABBE Corentin } else { 5709f93ac8dSLABBE Corentin t &= ~EMAC_TX_TRANSMITTER_EN; 5719f93ac8dSLABBE Corentin r &= ~EMAC_RX_RECEIVER_EN; 5729f93ac8dSLABBE Corentin } 5739f93ac8dSLABBE Corentin writel(t, ioaddr + EMAC_TX_CTL0); 5749f93ac8dSLABBE Corentin writel(r, ioaddr + EMAC_RX_CTL0); 5759f93ac8dSLABBE Corentin } 5769f93ac8dSLABBE Corentin 5779f93ac8dSLABBE Corentin /* Set MAC address at slot reg_n 5789f93ac8dSLABBE Corentin * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 5799f93ac8dSLABBE Corentin * If addr is NULL, clear the slot 5809f93ac8dSLABBE Corentin */ 5819f93ac8dSLABBE Corentin static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 5829f93ac8dSLABBE Corentin unsigned char *addr, 5839f93ac8dSLABBE Corentin unsigned int reg_n) 5849f93ac8dSLABBE Corentin { 5859f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5869f93ac8dSLABBE Corentin u32 v; 5879f93ac8dSLABBE Corentin 5889f93ac8dSLABBE Corentin if (!addr) { 5899f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 5909f93ac8dSLABBE Corentin return; 5919f93ac8dSLABBE Corentin } 5929f93ac8dSLABBE Corentin 5939f93ac8dSLABBE Corentin stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 5949f93ac8dSLABBE Corentin EMAC_MACADDR_LO(reg_n)); 5959f93ac8dSLABBE Corentin if (reg_n > 0) { 5969f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 5979f93ac8dSLABBE Corentin v |= MAC_ADDR_TYPE_DST; 5989f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 5999f93ac8dSLABBE Corentin } 6009f93ac8dSLABBE Corentin } 6019f93ac8dSLABBE Corentin 6029f93ac8dSLABBE Corentin static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 6039f93ac8dSLABBE Corentin unsigned char *addr, 6049f93ac8dSLABBE Corentin unsigned int reg_n) 6059f93ac8dSLABBE Corentin { 6069f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6079f93ac8dSLABBE Corentin 6089f93ac8dSLABBE Corentin stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 6099f93ac8dSLABBE Corentin EMAC_MACADDR_LO(reg_n)); 6109f93ac8dSLABBE Corentin } 6119f93ac8dSLABBE Corentin 6129f93ac8dSLABBE Corentin /* caution this function must return non 0 to work */ 6139f93ac8dSLABBE Corentin static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 6149f93ac8dSLABBE Corentin { 6159f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6169f93ac8dSLABBE Corentin u32 v; 6179f93ac8dSLABBE Corentin 6189f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL0); 6199f93ac8dSLABBE Corentin v |= EMAC_RX_DO_CRC; 6209f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL0); 6219f93ac8dSLABBE Corentin 6229f93ac8dSLABBE Corentin return 1; 6239f93ac8dSLABBE Corentin } 6249f93ac8dSLABBE Corentin 6259f93ac8dSLABBE Corentin static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 6269f93ac8dSLABBE Corentin struct net_device *dev) 6279f93ac8dSLABBE Corentin { 6289f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6299f93ac8dSLABBE Corentin u32 v; 6309f93ac8dSLABBE Corentin int i = 1; 6319f93ac8dSLABBE Corentin struct netdev_hw_addr *ha; 6329f93ac8dSLABBE Corentin int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 6339f93ac8dSLABBE Corentin 6349f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_CTL; 6359f93ac8dSLABBE Corentin 6369f93ac8dSLABBE Corentin if (dev->flags & IFF_PROMISC) { 6379f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_RXALL; 6389f93ac8dSLABBE Corentin } else if (dev->flags & IFF_ALLMULTI) { 6399f93ac8dSLABBE Corentin v |= EMAC_FRM_FLT_MULTICAST; 6409f93ac8dSLABBE Corentin } else if (macaddrs <= hw->unicast_filter_entries) { 6419f93ac8dSLABBE Corentin if (!netdev_mc_empty(dev)) { 6429f93ac8dSLABBE Corentin netdev_for_each_mc_addr(ha, dev) { 6439f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 6449f93ac8dSLABBE Corentin i++; 6459f93ac8dSLABBE Corentin } 6469f93ac8dSLABBE Corentin } 6479f93ac8dSLABBE Corentin if (!netdev_uc_empty(dev)) { 6489f93ac8dSLABBE Corentin netdev_for_each_uc_addr(ha, dev) { 6499f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 6509f93ac8dSLABBE Corentin i++; 6519f93ac8dSLABBE Corentin } 6529f93ac8dSLABBE Corentin } 6539f93ac8dSLABBE Corentin } else { 6549f93ac8dSLABBE Corentin netdev_info(dev, "Too many address, switching to promiscuous\n"); 6559f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_RXALL; 6569f93ac8dSLABBE Corentin } 6579f93ac8dSLABBE Corentin 6589f93ac8dSLABBE Corentin /* Disable unused address filter slots */ 6599f93ac8dSLABBE Corentin while (i < hw->unicast_filter_entries) 6609f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, NULL, i++); 6619f93ac8dSLABBE Corentin 6629f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_FRM_FLT); 6639f93ac8dSLABBE Corentin } 6649f93ac8dSLABBE Corentin 6659f93ac8dSLABBE Corentin static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 6669f93ac8dSLABBE Corentin unsigned int duplex, unsigned int fc, 6679f93ac8dSLABBE Corentin unsigned int pause_time, u32 tx_cnt) 6689f93ac8dSLABBE Corentin { 6699f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6709f93ac8dSLABBE Corentin u32 v; 6719f93ac8dSLABBE Corentin 6729f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL0); 6739f93ac8dSLABBE Corentin if (fc == FLOW_AUTO) 6749f93ac8dSLABBE Corentin v |= EMAC_RX_FLOW_CTL_EN; 6759f93ac8dSLABBE Corentin else 6769f93ac8dSLABBE Corentin v &= ~EMAC_RX_FLOW_CTL_EN; 6779f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL0); 6789f93ac8dSLABBE Corentin 6799f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_FLOW_CTL); 6809f93ac8dSLABBE Corentin if (fc == FLOW_AUTO) 6819f93ac8dSLABBE Corentin v |= EMAC_TX_FLOW_CTL_EN; 6829f93ac8dSLABBE Corentin else 6839f93ac8dSLABBE Corentin v &= ~EMAC_TX_FLOW_CTL_EN; 6849f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_FLOW_CTL); 6859f93ac8dSLABBE Corentin } 6869f93ac8dSLABBE Corentin 6879f93ac8dSLABBE Corentin static int sun8i_dwmac_reset(struct stmmac_priv *priv) 6889f93ac8dSLABBE Corentin { 6899f93ac8dSLABBE Corentin u32 v; 6909f93ac8dSLABBE Corentin int err; 6919f93ac8dSLABBE Corentin 6929f93ac8dSLABBE Corentin v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 6939f93ac8dSLABBE Corentin writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 6949f93ac8dSLABBE Corentin 6959f93ac8dSLABBE Corentin /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 6969f93ac8dSLABBE Corentin * need more if no cable plugged. 100ms seems OK 6979f93ac8dSLABBE Corentin */ 6989f93ac8dSLABBE Corentin err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 6999f93ac8dSLABBE Corentin !(v & 0x01), 100, 100000); 7009f93ac8dSLABBE Corentin 7019f93ac8dSLABBE Corentin if (err) { 7029f93ac8dSLABBE Corentin dev_err(priv->device, "EMAC reset timeout\n"); 7039f93ac8dSLABBE Corentin return -EFAULT; 7049f93ac8dSLABBE Corentin } 7059f93ac8dSLABBE Corentin return 0; 7069f93ac8dSLABBE Corentin } 7079f93ac8dSLABBE Corentin 708634db83bSCorentin Labbe /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 709634db83bSCorentin Labbe static int get_ephy_nodes(struct stmmac_priv *priv) 710634db83bSCorentin Labbe { 711634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 712634db83bSCorentin Labbe struct device_node *mdio_mux, *iphynode; 713634db83bSCorentin Labbe struct device_node *mdio_internal; 714634db83bSCorentin Labbe int ret; 715634db83bSCorentin Labbe 716634db83bSCorentin Labbe mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 717634db83bSCorentin Labbe if (!mdio_mux) { 718634db83bSCorentin Labbe dev_err(priv->device, "Cannot get mdio-mux node\n"); 719634db83bSCorentin Labbe return -ENODEV; 720634db83bSCorentin Labbe } 721634db83bSCorentin Labbe 722ac63043dSJohan Hovold mdio_internal = of_get_compatible_child(mdio_mux, 723634db83bSCorentin Labbe "allwinner,sun8i-h3-mdio-internal"); 724ac63043dSJohan Hovold of_node_put(mdio_mux); 725634db83bSCorentin Labbe if (!mdio_internal) { 726634db83bSCorentin Labbe dev_err(priv->device, "Cannot get internal_mdio node\n"); 727634db83bSCorentin Labbe return -ENODEV; 728634db83bSCorentin Labbe } 729634db83bSCorentin Labbe 730634db83bSCorentin Labbe /* Seek for internal PHY */ 731634db83bSCorentin Labbe for_each_child_of_node(mdio_internal, iphynode) { 732634db83bSCorentin Labbe gmac->ephy_clk = of_clk_get(iphynode, 0); 733634db83bSCorentin Labbe if (IS_ERR(gmac->ephy_clk)) 734634db83bSCorentin Labbe continue; 735634db83bSCorentin Labbe gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 736634db83bSCorentin Labbe if (IS_ERR(gmac->rst_ephy)) { 737634db83bSCorentin Labbe ret = PTR_ERR(gmac->rst_ephy); 738ac63043dSJohan Hovold if (ret == -EPROBE_DEFER) { 739ac63043dSJohan Hovold of_node_put(iphynode); 740ac63043dSJohan Hovold of_node_put(mdio_internal); 741634db83bSCorentin Labbe return ret; 742ac63043dSJohan Hovold } 743634db83bSCorentin Labbe continue; 744634db83bSCorentin Labbe } 745634db83bSCorentin Labbe dev_info(priv->device, "Found internal PHY node\n"); 746ac63043dSJohan Hovold of_node_put(iphynode); 747ac63043dSJohan Hovold of_node_put(mdio_internal); 748634db83bSCorentin Labbe return 0; 749634db83bSCorentin Labbe } 750ac63043dSJohan Hovold 751ac63043dSJohan Hovold of_node_put(mdio_internal); 752634db83bSCorentin Labbe return -ENODEV; 753634db83bSCorentin Labbe } 754634db83bSCorentin Labbe 755634db83bSCorentin Labbe static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 756634db83bSCorentin Labbe { 757634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 758634db83bSCorentin Labbe int ret; 759634db83bSCorentin Labbe 760634db83bSCorentin Labbe if (gmac->internal_phy_powered) { 761634db83bSCorentin Labbe dev_warn(priv->device, "Internal PHY already powered\n"); 762634db83bSCorentin Labbe return 0; 763634db83bSCorentin Labbe } 764634db83bSCorentin Labbe 765634db83bSCorentin Labbe dev_info(priv->device, "Powering internal PHY\n"); 766634db83bSCorentin Labbe ret = clk_prepare_enable(gmac->ephy_clk); 767634db83bSCorentin Labbe if (ret) { 768634db83bSCorentin Labbe dev_err(priv->device, "Cannot enable internal PHY\n"); 769634db83bSCorentin Labbe return ret; 770634db83bSCorentin Labbe } 771634db83bSCorentin Labbe 772634db83bSCorentin Labbe /* Make sure the EPHY is properly reseted, as U-Boot may leave 773634db83bSCorentin Labbe * it at deasserted state, and thus it may fail to reset EMAC. 774634db83bSCorentin Labbe */ 775634db83bSCorentin Labbe reset_control_assert(gmac->rst_ephy); 776634db83bSCorentin Labbe 777634db83bSCorentin Labbe ret = reset_control_deassert(gmac->rst_ephy); 778634db83bSCorentin Labbe if (ret) { 779634db83bSCorentin Labbe dev_err(priv->device, "Cannot deassert internal phy\n"); 780634db83bSCorentin Labbe clk_disable_unprepare(gmac->ephy_clk); 781634db83bSCorentin Labbe return ret; 782634db83bSCorentin Labbe } 783634db83bSCorentin Labbe 784634db83bSCorentin Labbe gmac->internal_phy_powered = true; 785634db83bSCorentin Labbe 786634db83bSCorentin Labbe return 0; 787634db83bSCorentin Labbe } 788634db83bSCorentin Labbe 789634db83bSCorentin Labbe static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 790634db83bSCorentin Labbe { 791634db83bSCorentin Labbe if (!gmac->internal_phy_powered) 792634db83bSCorentin Labbe return 0; 793634db83bSCorentin Labbe 794634db83bSCorentin Labbe clk_disable_unprepare(gmac->ephy_clk); 795634db83bSCorentin Labbe reset_control_assert(gmac->rst_ephy); 796634db83bSCorentin Labbe gmac->internal_phy_powered = false; 797634db83bSCorentin Labbe return 0; 798634db83bSCorentin Labbe } 799634db83bSCorentin Labbe 800634db83bSCorentin Labbe /* MDIO multiplexing switch function 801634db83bSCorentin Labbe * This function is called by the mdio-mux layer when it thinks the mdio bus 802634db83bSCorentin Labbe * multiplexer needs to switch. 803634db83bSCorentin Labbe * 'current_child' is the current value of the mux register 804634db83bSCorentin Labbe * 'desired_child' is the value of the 'reg' property of the target child MDIO 805634db83bSCorentin Labbe * node. 806634db83bSCorentin Labbe * The first time this function is called, current_child == -1. 807634db83bSCorentin Labbe * If current_child == desired_child, then the mux is already set to the 808634db83bSCorentin Labbe * correct bus. 809634db83bSCorentin Labbe */ 810634db83bSCorentin Labbe static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 811634db83bSCorentin Labbe void *data) 812634db83bSCorentin Labbe { 813634db83bSCorentin Labbe struct stmmac_priv *priv = data; 814634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 815634db83bSCorentin Labbe u32 reg, val; 816634db83bSCorentin Labbe int ret = 0; 817634db83bSCorentin Labbe bool need_power_ephy = false; 818634db83bSCorentin Labbe 819634db83bSCorentin Labbe if (current_child ^ desired_child) { 82025ae15fbSChen-Yu Tsai regmap_field_read(gmac->regmap_field, ®); 821634db83bSCorentin Labbe switch (desired_child) { 822634db83bSCorentin Labbe case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 823634db83bSCorentin Labbe dev_info(priv->device, "Switch mux to internal PHY"); 824634db83bSCorentin Labbe val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 825634db83bSCorentin Labbe 826634db83bSCorentin Labbe need_power_ephy = true; 827634db83bSCorentin Labbe break; 828634db83bSCorentin Labbe case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 829634db83bSCorentin Labbe dev_info(priv->device, "Switch mux to external PHY"); 830634db83bSCorentin Labbe val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 831634db83bSCorentin Labbe need_power_ephy = false; 832634db83bSCorentin Labbe break; 833634db83bSCorentin Labbe default: 834634db83bSCorentin Labbe dev_err(priv->device, "Invalid child ID %x\n", 835634db83bSCorentin Labbe desired_child); 836634db83bSCorentin Labbe return -EINVAL; 837634db83bSCorentin Labbe } 83825ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, val); 839634db83bSCorentin Labbe if (need_power_ephy) { 840634db83bSCorentin Labbe ret = sun8i_dwmac_power_internal_phy(priv); 841634db83bSCorentin Labbe if (ret) 842634db83bSCorentin Labbe return ret; 843634db83bSCorentin Labbe } else { 844634db83bSCorentin Labbe sun8i_dwmac_unpower_internal_phy(gmac); 845634db83bSCorentin Labbe } 846634db83bSCorentin Labbe /* After changing syscon value, the MAC need reset or it will 847634db83bSCorentin Labbe * use the last value (and so the last PHY set). 848634db83bSCorentin Labbe */ 849634db83bSCorentin Labbe ret = sun8i_dwmac_reset(priv); 850634db83bSCorentin Labbe } 851634db83bSCorentin Labbe return ret; 852634db83bSCorentin Labbe } 853634db83bSCorentin Labbe 854634db83bSCorentin Labbe static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 855634db83bSCorentin Labbe { 856634db83bSCorentin Labbe int ret; 857634db83bSCorentin Labbe struct device_node *mdio_mux; 858634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 859634db83bSCorentin Labbe 860634db83bSCorentin Labbe mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 861634db83bSCorentin Labbe if (!mdio_mux) 862634db83bSCorentin Labbe return -ENODEV; 863634db83bSCorentin Labbe 864634db83bSCorentin Labbe ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 865634db83bSCorentin Labbe &gmac->mux_handle, priv, priv->mii); 866634db83bSCorentin Labbe return ret; 867634db83bSCorentin Labbe } 868634db83bSCorentin Labbe 8699f93ac8dSLABBE Corentin static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 8709f93ac8dSLABBE Corentin { 8719f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 8729f93ac8dSLABBE Corentin struct device_node *node = priv->device->of_node; 873d93b07f8SLABBE Corentin int ret; 8749f93ac8dSLABBE Corentin u32 reg, val; 8759f93ac8dSLABBE Corentin 87625ae15fbSChen-Yu Tsai regmap_field_read(gmac->regmap_field, &val); 8779f93ac8dSLABBE Corentin reg = gmac->variant->default_syscon_value; 8789f93ac8dSLABBE Corentin if (reg != val) 8799f93ac8dSLABBE Corentin dev_warn(priv->device, 8809f93ac8dSLABBE Corentin "Current syscon value is not the default %x (expect %x)\n", 8819f93ac8dSLABBE Corentin val, reg); 8829f93ac8dSLABBE Corentin 883634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 8841c08ac0cSCorentin Labbe if (of_property_read_bool(node, "allwinner,leds-active-low")) 8859f93ac8dSLABBE Corentin reg |= H3_EPHY_LED_POL; 8869f93ac8dSLABBE Corentin else 8879f93ac8dSLABBE Corentin reg &= ~H3_EPHY_LED_POL; 8889f93ac8dSLABBE Corentin 8891450ba8aSIcenowy Zheng /* Force EPHY xtal frequency to 24MHz. */ 8901450ba8aSIcenowy Zheng reg |= H3_EPHY_CLK_SEL; 8911450ba8aSIcenowy Zheng 892634db83bSCorentin Labbe ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 8939f93ac8dSLABBE Corentin if (ret < 0) { 8949f93ac8dSLABBE Corentin dev_err(priv->device, "Could not parse MDIO addr\n"); 8959f93ac8dSLABBE Corentin return ret; 8969f93ac8dSLABBE Corentin } 8979f93ac8dSLABBE Corentin /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 8989f93ac8dSLABBE Corentin * address. No need to mask it again. 8999f93ac8dSLABBE Corentin */ 900634db83bSCorentin Labbe reg |= 1 << H3_EPHY_ADDR_SHIFT; 9019f93ac8dSLABBE Corentin } 9029f93ac8dSLABBE Corentin 9039f93ac8dSLABBE Corentin if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 9049f93ac8dSLABBE Corentin if (val % 100) { 9059f93ac8dSLABBE Corentin dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 9069f93ac8dSLABBE Corentin return -EINVAL; 9079f93ac8dSLABBE Corentin } 9089f93ac8dSLABBE Corentin val /= 100; 9099f93ac8dSLABBE Corentin dev_dbg(priv->device, "set tx-delay to %x\n", val); 9107b270b72SChen-Yu Tsai if (val <= gmac->variant->tx_delay_max) { 9117b270b72SChen-Yu Tsai reg &= ~(gmac->variant->tx_delay_max << 9127b270b72SChen-Yu Tsai SYSCON_ETXDC_SHIFT); 9139f93ac8dSLABBE Corentin reg |= (val << SYSCON_ETXDC_SHIFT); 9149f93ac8dSLABBE Corentin } else { 9159f93ac8dSLABBE Corentin dev_err(priv->device, "Invalid TX clock delay: %d\n", 9169f93ac8dSLABBE Corentin val); 9179f93ac8dSLABBE Corentin return -EINVAL; 9189f93ac8dSLABBE Corentin } 9199f93ac8dSLABBE Corentin } 9209f93ac8dSLABBE Corentin 9219f93ac8dSLABBE Corentin if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 9229f93ac8dSLABBE Corentin if (val % 100) { 9239f93ac8dSLABBE Corentin dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 9249f93ac8dSLABBE Corentin return -EINVAL; 9259f93ac8dSLABBE Corentin } 9269f93ac8dSLABBE Corentin val /= 100; 9279f93ac8dSLABBE Corentin dev_dbg(priv->device, "set rx-delay to %x\n", val); 9287b270b72SChen-Yu Tsai if (val <= gmac->variant->rx_delay_max) { 9297b270b72SChen-Yu Tsai reg &= ~(gmac->variant->rx_delay_max << 9307b270b72SChen-Yu Tsai SYSCON_ERXDC_SHIFT); 9319f93ac8dSLABBE Corentin reg |= (val << SYSCON_ERXDC_SHIFT); 9329f93ac8dSLABBE Corentin } else { 9339f93ac8dSLABBE Corentin dev_err(priv->device, "Invalid RX clock delay: %d\n", 9349f93ac8dSLABBE Corentin val); 9359f93ac8dSLABBE Corentin return -EINVAL; 9369f93ac8dSLABBE Corentin } 9379f93ac8dSLABBE Corentin } 9389f93ac8dSLABBE Corentin 9399f93ac8dSLABBE Corentin /* Clear interface mode bits */ 9409f93ac8dSLABBE Corentin reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 9419f93ac8dSLABBE Corentin if (gmac->variant->support_rmii) 9429f93ac8dSLABBE Corentin reg &= ~SYSCON_RMII_EN; 9439f93ac8dSLABBE Corentin 944d93b07f8SLABBE Corentin switch (priv->plat->interface) { 9459f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_MII: 9469f93ac8dSLABBE Corentin /* default */ 9479f93ac8dSLABBE Corentin break; 9489f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_RGMII: 9499f93ac8dSLABBE Corentin reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 9509f93ac8dSLABBE Corentin break; 9519f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_RMII: 9529f93ac8dSLABBE Corentin reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 9539f93ac8dSLABBE Corentin break; 9549f93ac8dSLABBE Corentin default: 9559f93ac8dSLABBE Corentin dev_err(priv->device, "Unsupported interface mode: %s", 9569f93ac8dSLABBE Corentin phy_modes(priv->plat->interface)); 9579f93ac8dSLABBE Corentin return -EINVAL; 9589f93ac8dSLABBE Corentin } 9599f93ac8dSLABBE Corentin 96025ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, reg); 9619f93ac8dSLABBE Corentin 9629f93ac8dSLABBE Corentin return 0; 9639f93ac8dSLABBE Corentin } 9649f93ac8dSLABBE Corentin 9659f93ac8dSLABBE Corentin static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 9669f93ac8dSLABBE Corentin { 9679f93ac8dSLABBE Corentin u32 reg = gmac->variant->default_syscon_value; 9689f93ac8dSLABBE Corentin 96925ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, reg); 9709f93ac8dSLABBE Corentin } 9719f93ac8dSLABBE Corentin 9729f93ac8dSLABBE Corentin static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 9739f93ac8dSLABBE Corentin { 9749f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv; 9759f93ac8dSLABBE Corentin 976634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 977634db83bSCorentin Labbe /* sun8i_dwmac_exit could be called with mdiomux uninit */ 978634db83bSCorentin Labbe if (gmac->mux_handle) 979634db83bSCorentin Labbe mdio_mux_uninit(gmac->mux_handle); 980634db83bSCorentin Labbe if (gmac->internal_phy_powered) 981634db83bSCorentin Labbe sun8i_dwmac_unpower_internal_phy(gmac); 982634db83bSCorentin Labbe } 983634db83bSCorentin Labbe 984634db83bSCorentin Labbe sun8i_dwmac_unset_syscon(gmac); 985634db83bSCorentin Labbe 986634db83bSCorentin Labbe reset_control_put(gmac->rst_ephy); 9879f93ac8dSLABBE Corentin 9889f93ac8dSLABBE Corentin clk_disable_unprepare(gmac->tx_clk); 9899f93ac8dSLABBE Corentin 9909f93ac8dSLABBE Corentin if (gmac->regulator) 9919f93ac8dSLABBE Corentin regulator_disable(gmac->regulator); 9929f93ac8dSLABBE Corentin } 9939f93ac8dSLABBE Corentin 9948edb1271SCorentin Labbe static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 9958edb1271SCorentin Labbe { 9968edb1271SCorentin Labbe u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 9978edb1271SCorentin Labbe 9988edb1271SCorentin Labbe if (enable) 9998edb1271SCorentin Labbe value |= EMAC_LOOPBACK; 10008edb1271SCorentin Labbe else 10018edb1271SCorentin Labbe value &= ~EMAC_LOOPBACK; 10028edb1271SCorentin Labbe 10038edb1271SCorentin Labbe writel(value, ioaddr + EMAC_BASIC_CTL0); 10048edb1271SCorentin Labbe } 10058edb1271SCorentin Labbe 10069f93ac8dSLABBE Corentin static const struct stmmac_ops sun8i_dwmac_ops = { 10079f93ac8dSLABBE Corentin .core_init = sun8i_dwmac_core_init, 10089f93ac8dSLABBE Corentin .set_mac = sun8i_dwmac_set_mac, 10099f93ac8dSLABBE Corentin .dump_regs = sun8i_dwmac_dump_mac_regs, 10109f93ac8dSLABBE Corentin .rx_ipc = sun8i_dwmac_rx_ipc_enable, 10119f93ac8dSLABBE Corentin .set_filter = sun8i_dwmac_set_filter, 10129f93ac8dSLABBE Corentin .flow_ctrl = sun8i_dwmac_flow_ctrl, 10139f93ac8dSLABBE Corentin .set_umac_addr = sun8i_dwmac_set_umac_addr, 10149f93ac8dSLABBE Corentin .get_umac_addr = sun8i_dwmac_get_umac_addr, 10158edb1271SCorentin Labbe .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 10169f93ac8dSLABBE Corentin }; 10179f93ac8dSLABBE Corentin 10189f93ac8dSLABBE Corentin static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 10199f93ac8dSLABBE Corentin { 10209f93ac8dSLABBE Corentin struct mac_device_info *mac; 10219f93ac8dSLABBE Corentin struct stmmac_priv *priv = ppriv; 10229f93ac8dSLABBE Corentin int ret; 10239f93ac8dSLABBE Corentin 10249f93ac8dSLABBE Corentin mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 10259f93ac8dSLABBE Corentin if (!mac) 10269f93ac8dSLABBE Corentin return NULL; 10279f93ac8dSLABBE Corentin 1028634db83bSCorentin Labbe ret = sun8i_dwmac_set_syscon(priv); 10299f93ac8dSLABBE Corentin if (ret) 10309f93ac8dSLABBE Corentin return NULL; 10319f93ac8dSLABBE Corentin 10329f93ac8dSLABBE Corentin mac->pcsr = priv->ioaddr; 10339f93ac8dSLABBE Corentin mac->mac = &sun8i_dwmac_ops; 10349f93ac8dSLABBE Corentin mac->dma = &sun8i_dwmac_dma_ops; 10359f93ac8dSLABBE Corentin 1036d4c26eb6SCorentin Labbe priv->dev->priv_flags |= IFF_UNICAST_FLT; 1037d4c26eb6SCorentin Labbe 10389f93ac8dSLABBE Corentin /* The loopback bit seems to be re-set when link change 10399f93ac8dSLABBE Corentin * Simply mask it each time 10409f93ac8dSLABBE Corentin * Speed 10/100/1000 are set in BIT(2)/BIT(3) 10419f93ac8dSLABBE Corentin */ 10429f93ac8dSLABBE Corentin mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 10439f93ac8dSLABBE Corentin mac->link.speed10 = EMAC_SPEED_10; 10449f93ac8dSLABBE Corentin mac->link.speed100 = EMAC_SPEED_100; 10459f93ac8dSLABBE Corentin mac->link.speed1000 = EMAC_SPEED_1000; 10469f93ac8dSLABBE Corentin mac->link.duplex = EMAC_DUPLEX_FULL; 10479f93ac8dSLABBE Corentin mac->mii.addr = EMAC_MDIO_CMD; 10489f93ac8dSLABBE Corentin mac->mii.data = EMAC_MDIO_DATA; 10499f93ac8dSLABBE Corentin mac->mii.reg_shift = 4; 10509f93ac8dSLABBE Corentin mac->mii.reg_mask = GENMASK(8, 4); 10519f93ac8dSLABBE Corentin mac->mii.addr_shift = 12; 10529f93ac8dSLABBE Corentin mac->mii.addr_mask = GENMASK(16, 12); 10539f93ac8dSLABBE Corentin mac->mii.clk_csr_shift = 20; 10549f93ac8dSLABBE Corentin mac->mii.clk_csr_mask = GENMASK(22, 20); 10559f93ac8dSLABBE Corentin mac->unicast_filter_entries = 8; 10569f93ac8dSLABBE Corentin 10579f93ac8dSLABBE Corentin /* Synopsys Id is not available */ 10589f93ac8dSLABBE Corentin priv->synopsys_id = 0; 10599f93ac8dSLABBE Corentin 10609f93ac8dSLABBE Corentin return mac; 10619f93ac8dSLABBE Corentin } 10629f93ac8dSLABBE Corentin 106349a06caeSChen-Yu Tsai static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 106449a06caeSChen-Yu Tsai { 106549a06caeSChen-Yu Tsai struct device_node *syscon_node; 106649a06caeSChen-Yu Tsai struct platform_device *syscon_pdev; 106749a06caeSChen-Yu Tsai struct regmap *regmap = NULL; 106849a06caeSChen-Yu Tsai 106949a06caeSChen-Yu Tsai syscon_node = of_parse_phandle(node, "syscon", 0); 107049a06caeSChen-Yu Tsai if (!syscon_node) 107149a06caeSChen-Yu Tsai return ERR_PTR(-ENODEV); 107249a06caeSChen-Yu Tsai 107349a06caeSChen-Yu Tsai syscon_pdev = of_find_device_by_node(syscon_node); 107449a06caeSChen-Yu Tsai if (!syscon_pdev) { 107549a06caeSChen-Yu Tsai /* platform device might not be probed yet */ 107649a06caeSChen-Yu Tsai regmap = ERR_PTR(-EPROBE_DEFER); 107749a06caeSChen-Yu Tsai goto out_put_node; 107849a06caeSChen-Yu Tsai } 107949a06caeSChen-Yu Tsai 108049a06caeSChen-Yu Tsai /* If no regmap is found then the other device driver is at fault */ 108149a06caeSChen-Yu Tsai regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 108249a06caeSChen-Yu Tsai if (!regmap) 108349a06caeSChen-Yu Tsai regmap = ERR_PTR(-EINVAL); 108449a06caeSChen-Yu Tsai 108549a06caeSChen-Yu Tsai platform_device_put(syscon_pdev); 108649a06caeSChen-Yu Tsai out_put_node: 108749a06caeSChen-Yu Tsai of_node_put(syscon_node); 108849a06caeSChen-Yu Tsai return regmap; 108949a06caeSChen-Yu Tsai } 109049a06caeSChen-Yu Tsai 10919f93ac8dSLABBE Corentin static int sun8i_dwmac_probe(struct platform_device *pdev) 10929f93ac8dSLABBE Corentin { 10939f93ac8dSLABBE Corentin struct plat_stmmacenet_data *plat_dat; 10949f93ac8dSLABBE Corentin struct stmmac_resources stmmac_res; 10959f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac; 10969f93ac8dSLABBE Corentin struct device *dev = &pdev->dev; 10979f93ac8dSLABBE Corentin int ret; 1098634db83bSCorentin Labbe struct stmmac_priv *priv; 1099634db83bSCorentin Labbe struct net_device *ndev; 110025ae15fbSChen-Yu Tsai struct regmap *regmap; 11019f93ac8dSLABBE Corentin 11029f93ac8dSLABBE Corentin ret = stmmac_get_platform_resources(pdev, &stmmac_res); 11039f93ac8dSLABBE Corentin if (ret) 11049f93ac8dSLABBE Corentin return ret; 11059f93ac8dSLABBE Corentin 11069f93ac8dSLABBE Corentin plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 11079f93ac8dSLABBE Corentin if (IS_ERR(plat_dat)) 11089f93ac8dSLABBE Corentin return PTR_ERR(plat_dat); 11099f93ac8dSLABBE Corentin 11109f93ac8dSLABBE Corentin gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 11119f93ac8dSLABBE Corentin if (!gmac) 11129f93ac8dSLABBE Corentin return -ENOMEM; 11139f93ac8dSLABBE Corentin 11149f93ac8dSLABBE Corentin gmac->variant = of_device_get_match_data(&pdev->dev); 11159f93ac8dSLABBE Corentin if (!gmac->variant) { 11169f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 11179f93ac8dSLABBE Corentin return -EINVAL; 11189f93ac8dSLABBE Corentin } 11199f93ac8dSLABBE Corentin 11209f93ac8dSLABBE Corentin gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 11219f93ac8dSLABBE Corentin if (IS_ERR(gmac->tx_clk)) { 11229f93ac8dSLABBE Corentin dev_err(dev, "Could not get TX clock\n"); 11239f93ac8dSLABBE Corentin return PTR_ERR(gmac->tx_clk); 11249f93ac8dSLABBE Corentin } 11259f93ac8dSLABBE Corentin 11269f93ac8dSLABBE Corentin /* Optional regulator for PHY */ 11279f93ac8dSLABBE Corentin gmac->regulator = devm_regulator_get_optional(dev, "phy"); 11289f93ac8dSLABBE Corentin if (IS_ERR(gmac->regulator)) { 11299f93ac8dSLABBE Corentin if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 11309f93ac8dSLABBE Corentin return -EPROBE_DEFER; 11319f93ac8dSLABBE Corentin dev_info(dev, "No regulator found\n"); 11329f93ac8dSLABBE Corentin gmac->regulator = NULL; 11339f93ac8dSLABBE Corentin } 11349f93ac8dSLABBE Corentin 113549a06caeSChen-Yu Tsai /* The "GMAC clock control" register might be located in the 113649a06caeSChen-Yu Tsai * CCU address range (on the R40), or the system control address 113749a06caeSChen-Yu Tsai * range (on most other sun8i and later SoCs). 113849a06caeSChen-Yu Tsai * 113949a06caeSChen-Yu Tsai * The former controls most if not all clocks in the SoC. The 114049a06caeSChen-Yu Tsai * latter has an SoC identification register, and on some SoCs, 114149a06caeSChen-Yu Tsai * controls to map device specific SRAM to either the intended 114249a06caeSChen-Yu Tsai * peripheral, or the CPU address space. 114349a06caeSChen-Yu Tsai * 114449a06caeSChen-Yu Tsai * In either case, there should be a coordinated and restricted 114549a06caeSChen-Yu Tsai * method of accessing the register needed here. This is done by 114649a06caeSChen-Yu Tsai * having the device export a custom regmap, instead of a generic 114749a06caeSChen-Yu Tsai * syscon, which grants all access to all registers. 114849a06caeSChen-Yu Tsai * 114949a06caeSChen-Yu Tsai * To support old device trees, we fall back to using the syscon 115049a06caeSChen-Yu Tsai * interface if possible. 115149a06caeSChen-Yu Tsai */ 115249a06caeSChen-Yu Tsai regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 115349a06caeSChen-Yu Tsai if (IS_ERR(regmap)) 115449a06caeSChen-Yu Tsai regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 115549a06caeSChen-Yu Tsai "syscon"); 115625ae15fbSChen-Yu Tsai if (IS_ERR(regmap)) { 115725ae15fbSChen-Yu Tsai ret = PTR_ERR(regmap); 11589f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 11599f93ac8dSLABBE Corentin return ret; 11609f93ac8dSLABBE Corentin } 11619f93ac8dSLABBE Corentin 116225ae15fbSChen-Yu Tsai gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 116325ae15fbSChen-Yu Tsai *gmac->variant->syscon_field); 116425ae15fbSChen-Yu Tsai if (IS_ERR(gmac->regmap_field)) { 116525ae15fbSChen-Yu Tsai ret = PTR_ERR(gmac->regmap_field); 116625ae15fbSChen-Yu Tsai dev_err(dev, "Unable to map syscon register: %d\n", ret); 116725ae15fbSChen-Yu Tsai return ret; 116825ae15fbSChen-Yu Tsai } 116925ae15fbSChen-Yu Tsai 11704ec850e5SKangjie Lu ret = of_get_phy_mode(dev->of_node); 11714ec850e5SKangjie Lu if (ret < 0) 11724ec850e5SKangjie Lu return -EINVAL; 11734ec850e5SKangjie Lu plat_dat->interface = ret; 11749f93ac8dSLABBE Corentin 11759f93ac8dSLABBE Corentin /* platform data specifying hardware features and callbacks. 11769f93ac8dSLABBE Corentin * hardware features were copied from Allwinner drivers. 11779f93ac8dSLABBE Corentin */ 11789f93ac8dSLABBE Corentin plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 11799f93ac8dSLABBE Corentin plat_dat->tx_coe = 1; 11809f93ac8dSLABBE Corentin plat_dat->has_sun8i = true; 11819f93ac8dSLABBE Corentin plat_dat->bsp_priv = gmac; 11829f93ac8dSLABBE Corentin plat_dat->init = sun8i_dwmac_init; 11839f93ac8dSLABBE Corentin plat_dat->exit = sun8i_dwmac_exit; 11849f93ac8dSLABBE Corentin plat_dat->setup = sun8i_dwmac_setup; 11859f93ac8dSLABBE Corentin 11869f93ac8dSLABBE Corentin ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 11879f93ac8dSLABBE Corentin if (ret) 11889f93ac8dSLABBE Corentin return ret; 11899f93ac8dSLABBE Corentin 11909f93ac8dSLABBE Corentin ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 11919f93ac8dSLABBE Corentin if (ret) 1192634db83bSCorentin Labbe goto dwmac_exit; 11939f93ac8dSLABBE Corentin 1194634db83bSCorentin Labbe ndev = dev_get_drvdata(&pdev->dev); 1195634db83bSCorentin Labbe priv = netdev_priv(ndev); 1196634db83bSCorentin Labbe /* The mux must be registered after parent MDIO 1197634db83bSCorentin Labbe * so after stmmac_dvr_probe() 1198634db83bSCorentin Labbe */ 1199634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 1200634db83bSCorentin Labbe ret = get_ephy_nodes(priv); 1201634db83bSCorentin Labbe if (ret) 1202634db83bSCorentin Labbe goto dwmac_exit; 1203634db83bSCorentin Labbe ret = sun8i_dwmac_register_mdio_mux(priv); 1204634db83bSCorentin Labbe if (ret) { 1205634db83bSCorentin Labbe dev_err(&pdev->dev, "Failed to register mux\n"); 1206634db83bSCorentin Labbe goto dwmac_mux; 1207634db83bSCorentin Labbe } 1208634db83bSCorentin Labbe } else { 1209634db83bSCorentin Labbe ret = sun8i_dwmac_reset(priv); 1210634db83bSCorentin Labbe if (ret) 1211634db83bSCorentin Labbe goto dwmac_exit; 1212634db83bSCorentin Labbe } 1213634db83bSCorentin Labbe 1214634db83bSCorentin Labbe return ret; 1215634db83bSCorentin Labbe dwmac_mux: 1216634db83bSCorentin Labbe sun8i_dwmac_unset_syscon(gmac); 1217634db83bSCorentin Labbe dwmac_exit: 1218634db83bSCorentin Labbe sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); 12199f93ac8dSLABBE Corentin return ret; 12209f93ac8dSLABBE Corentin } 12219f93ac8dSLABBE Corentin 12229f93ac8dSLABBE Corentin static const struct of_device_id sun8i_dwmac_match[] = { 1223a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-h3-emac", 1224a8ff8ccbSCorentin Labbe .data = &emac_variant_h3 }, 1225a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-v3s-emac", 1226a8ff8ccbSCorentin Labbe .data = &emac_variant_v3s }, 1227a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-a83t-emac", 1228a8ff8ccbSCorentin Labbe .data = &emac_variant_a83t }, 12299bf5085aSChen-Yu Tsai { .compatible = "allwinner,sun8i-r40-gmac", 12309bf5085aSChen-Yu Tsai .data = &emac_variant_r40 }, 1231a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun50i-a64-emac", 1232a8ff8ccbSCorentin Labbe .data = &emac_variant_a64 }, 1233adadd38cSIcenowy Zheng { .compatible = "allwinner,sun50i-h6-emac", 1234adadd38cSIcenowy Zheng .data = &emac_variant_h6 }, 12359f93ac8dSLABBE Corentin { } 12369f93ac8dSLABBE Corentin }; 12379f93ac8dSLABBE Corentin MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 12389f93ac8dSLABBE Corentin 12399f93ac8dSLABBE Corentin static struct platform_driver sun8i_dwmac_driver = { 12409f93ac8dSLABBE Corentin .probe = sun8i_dwmac_probe, 12419f93ac8dSLABBE Corentin .remove = stmmac_pltfr_remove, 12429f93ac8dSLABBE Corentin .driver = { 12439f93ac8dSLABBE Corentin .name = "dwmac-sun8i", 12449f93ac8dSLABBE Corentin .pm = &stmmac_pltfr_pm_ops, 12459f93ac8dSLABBE Corentin .of_match_table = sun8i_dwmac_match, 12469f93ac8dSLABBE Corentin }, 12479f93ac8dSLABBE Corentin }; 12489f93ac8dSLABBE Corentin module_platform_driver(sun8i_dwmac_driver); 12499f93ac8dSLABBE Corentin 12509f93ac8dSLABBE Corentin MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 12519f93ac8dSLABBE Corentin MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 12529f93ac8dSLABBE Corentin MODULE_LICENSE("GPL"); 1253