19f93ac8dSLABBE Corentin /* 29f93ac8dSLABBE Corentin * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 39f93ac8dSLABBE Corentin * 49f93ac8dSLABBE Corentin * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 59f93ac8dSLABBE Corentin * 69f93ac8dSLABBE Corentin * This program is free software; you can redistribute it and/or modify 79f93ac8dSLABBE Corentin * it under the terms of the GNU General Public License as published by 89f93ac8dSLABBE Corentin * the Free Software Foundation; either version 2 of the License, or 99f93ac8dSLABBE Corentin * (at your option) any later version. 109f93ac8dSLABBE Corentin * 119f93ac8dSLABBE Corentin * This program is distributed in the hope that it will be useful, 129f93ac8dSLABBE Corentin * but WITHOUT ANY WARRANTY; without even the implied warranty of 139f93ac8dSLABBE Corentin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 149f93ac8dSLABBE Corentin * GNU General Public License for more details. 159f93ac8dSLABBE Corentin */ 169f93ac8dSLABBE Corentin 179f93ac8dSLABBE Corentin #include <linux/clk.h> 189f93ac8dSLABBE Corentin #include <linux/io.h> 199f93ac8dSLABBE Corentin #include <linux/iopoll.h> 20634db83bSCorentin Labbe #include <linux/mdio-mux.h> 219f93ac8dSLABBE Corentin #include <linux/mfd/syscon.h> 229f93ac8dSLABBE Corentin #include <linux/module.h> 239f93ac8dSLABBE Corentin #include <linux/of_device.h> 249f93ac8dSLABBE Corentin #include <linux/of_mdio.h> 259f93ac8dSLABBE Corentin #include <linux/of_net.h> 269f93ac8dSLABBE Corentin #include <linux/phy.h> 279f93ac8dSLABBE Corentin #include <linux/platform_device.h> 289f93ac8dSLABBE Corentin #include <linux/regulator/consumer.h> 299f93ac8dSLABBE Corentin #include <linux/regmap.h> 309f93ac8dSLABBE Corentin #include <linux/stmmac.h> 319f93ac8dSLABBE Corentin 329f93ac8dSLABBE Corentin #include "stmmac.h" 339f93ac8dSLABBE Corentin #include "stmmac_platform.h" 349f93ac8dSLABBE Corentin 359f93ac8dSLABBE Corentin /* General notes on dwmac-sun8i: 369f93ac8dSLABBE Corentin * Locking: no locking is necessary in this file because all necessary locking 379f93ac8dSLABBE Corentin * is done in the "stmmac files" 389f93ac8dSLABBE Corentin */ 399f93ac8dSLABBE Corentin 409f93ac8dSLABBE Corentin /* struct emac_variant - Descrive dwmac-sun8i hardware variant 419f93ac8dSLABBE Corentin * @default_syscon_value: The default value of the EMAC register in syscon 429f93ac8dSLABBE Corentin * This value is used for disabling properly EMAC 439f93ac8dSLABBE Corentin * and used as a good starting value in case of the 449f93ac8dSLABBE Corentin * boot process(uboot) leave some stuff. 4525ae15fbSChen-Yu Tsai * @syscon_field reg_field for the syscon's gmac register 46634db83bSCorentin Labbe * @soc_has_internal_phy: Does the MAC embed an internal PHY 479f93ac8dSLABBE Corentin * @support_mii: Does the MAC handle MII 489f93ac8dSLABBE Corentin * @support_rmii: Does the MAC handle RMII 499f93ac8dSLABBE Corentin * @support_rgmii: Does the MAC handle RGMII 507b270b72SChen-Yu Tsai * 517b270b72SChen-Yu Tsai * @rx_delay_max: Maximum raw value for RX delay chain 527b270b72SChen-Yu Tsai * @tx_delay_max: Maximum raw value for TX delay chain 537b270b72SChen-Yu Tsai * These two also indicate the bitmask for 547b270b72SChen-Yu Tsai * the RX and TX delay chain registers. A 557b270b72SChen-Yu Tsai * value of zero indicates this is not supported. 569f93ac8dSLABBE Corentin */ 579f93ac8dSLABBE Corentin struct emac_variant { 589f93ac8dSLABBE Corentin u32 default_syscon_value; 5925ae15fbSChen-Yu Tsai const struct reg_field *syscon_field; 60634db83bSCorentin Labbe bool soc_has_internal_phy; 619f93ac8dSLABBE Corentin bool support_mii; 629f93ac8dSLABBE Corentin bool support_rmii; 639f93ac8dSLABBE Corentin bool support_rgmii; 647b270b72SChen-Yu Tsai u8 rx_delay_max; 657b270b72SChen-Yu Tsai u8 tx_delay_max; 669f93ac8dSLABBE Corentin }; 679f93ac8dSLABBE Corentin 689f93ac8dSLABBE Corentin /* struct sunxi_priv_data - hold all sunxi private data 699f93ac8dSLABBE Corentin * @tx_clk: reference to MAC TX clock 709f93ac8dSLABBE Corentin * @ephy_clk: reference to the optional EPHY clock for the internal PHY 719f93ac8dSLABBE Corentin * @regulator: reference to the optional regulator 729f93ac8dSLABBE Corentin * @rst_ephy: reference to the optional EPHY reset for the internal PHY 739f93ac8dSLABBE Corentin * @variant: reference to the current board variant 749f93ac8dSLABBE Corentin * @regmap: regmap for using the syscon 75634db83bSCorentin Labbe * @internal_phy_powered: Does the internal PHY is enabled 76634db83bSCorentin Labbe * @mux_handle: Internal pointer used by mdio-mux lib 779f93ac8dSLABBE Corentin */ 789f93ac8dSLABBE Corentin struct sunxi_priv_data { 799f93ac8dSLABBE Corentin struct clk *tx_clk; 809f93ac8dSLABBE Corentin struct clk *ephy_clk; 819f93ac8dSLABBE Corentin struct regulator *regulator; 829f93ac8dSLABBE Corentin struct reset_control *rst_ephy; 839f93ac8dSLABBE Corentin const struct emac_variant *variant; 8425ae15fbSChen-Yu Tsai struct regmap_field *regmap_field; 85634db83bSCorentin Labbe bool internal_phy_powered; 86634db83bSCorentin Labbe void *mux_handle; 879f93ac8dSLABBE Corentin }; 889f93ac8dSLABBE Corentin 8925ae15fbSChen-Yu Tsai /* EMAC clock register @ 0x30 in the "system control" address range */ 9025ae15fbSChen-Yu Tsai static const struct reg_field sun8i_syscon_reg_field = { 9125ae15fbSChen-Yu Tsai .reg = 0x30, 9225ae15fbSChen-Yu Tsai .lsb = 0, 9325ae15fbSChen-Yu Tsai .msb = 31, 9425ae15fbSChen-Yu Tsai }; 9525ae15fbSChen-Yu Tsai 969f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_h3 = { 979f93ac8dSLABBE Corentin .default_syscon_value = 0x58000, 9825ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 99634db83bSCorentin Labbe .soc_has_internal_phy = true, 1009f93ac8dSLABBE Corentin .support_mii = true, 1019f93ac8dSLABBE Corentin .support_rmii = true, 1027b270b72SChen-Yu Tsai .support_rgmii = true, 1037b270b72SChen-Yu Tsai .rx_delay_max = 31, 1047b270b72SChen-Yu Tsai .tx_delay_max = 7, 1059f93ac8dSLABBE Corentin }; 1069f93ac8dSLABBE Corentin 10757fde47dSIcenowy Zheng static const struct emac_variant emac_variant_v3s = { 10857fde47dSIcenowy Zheng .default_syscon_value = 0x38000, 10925ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 110634db83bSCorentin Labbe .soc_has_internal_phy = true, 11157fde47dSIcenowy Zheng .support_mii = true 11257fde47dSIcenowy Zheng }; 11357fde47dSIcenowy Zheng 1149f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_a83t = { 1159f93ac8dSLABBE Corentin .default_syscon_value = 0, 11625ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 117634db83bSCorentin Labbe .soc_has_internal_phy = false, 1189f93ac8dSLABBE Corentin .support_mii = true, 1197b270b72SChen-Yu Tsai .support_rgmii = true, 1207b270b72SChen-Yu Tsai .rx_delay_max = 31, 1217b270b72SChen-Yu Tsai .tx_delay_max = 7, 1229f93ac8dSLABBE Corentin }; 1239f93ac8dSLABBE Corentin 1249f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_a64 = { 1259f93ac8dSLABBE Corentin .default_syscon_value = 0, 12625ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 127634db83bSCorentin Labbe .soc_has_internal_phy = false, 1289f93ac8dSLABBE Corentin .support_mii = true, 1299f93ac8dSLABBE Corentin .support_rmii = true, 1307b270b72SChen-Yu Tsai .support_rgmii = true, 1317b270b72SChen-Yu Tsai .rx_delay_max = 31, 1327b270b72SChen-Yu Tsai .tx_delay_max = 7, 1339f93ac8dSLABBE Corentin }; 1349f93ac8dSLABBE Corentin 1359f93ac8dSLABBE Corentin #define EMAC_BASIC_CTL0 0x00 1369f93ac8dSLABBE Corentin #define EMAC_BASIC_CTL1 0x04 1379f93ac8dSLABBE Corentin #define EMAC_INT_STA 0x08 1389f93ac8dSLABBE Corentin #define EMAC_INT_EN 0x0C 1399f93ac8dSLABBE Corentin #define EMAC_TX_CTL0 0x10 1409f93ac8dSLABBE Corentin #define EMAC_TX_CTL1 0x14 1419f93ac8dSLABBE Corentin #define EMAC_TX_FLOW_CTL 0x1C 1429f93ac8dSLABBE Corentin #define EMAC_TX_DESC_LIST 0x20 1439f93ac8dSLABBE Corentin #define EMAC_RX_CTL0 0x24 1449f93ac8dSLABBE Corentin #define EMAC_RX_CTL1 0x28 1459f93ac8dSLABBE Corentin #define EMAC_RX_DESC_LIST 0x34 1469f93ac8dSLABBE Corentin #define EMAC_RX_FRM_FLT 0x38 1479f93ac8dSLABBE Corentin #define EMAC_MDIO_CMD 0x48 1489f93ac8dSLABBE Corentin #define EMAC_MDIO_DATA 0x4C 1499f93ac8dSLABBE Corentin #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 1509f93ac8dSLABBE Corentin #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 1519f93ac8dSLABBE Corentin #define EMAC_TX_DMA_STA 0xB0 1529f93ac8dSLABBE Corentin #define EMAC_TX_CUR_DESC 0xB4 1539f93ac8dSLABBE Corentin #define EMAC_TX_CUR_BUF 0xB8 1549f93ac8dSLABBE Corentin #define EMAC_RX_DMA_STA 0xC0 1559f93ac8dSLABBE Corentin #define EMAC_RX_CUR_DESC 0xC4 1569f93ac8dSLABBE Corentin #define EMAC_RX_CUR_BUF 0xC8 1579f93ac8dSLABBE Corentin 1589f93ac8dSLABBE Corentin /* Use in EMAC_BASIC_CTL0 */ 1599f93ac8dSLABBE Corentin #define EMAC_DUPLEX_FULL BIT(0) 1609f93ac8dSLABBE Corentin #define EMAC_LOOPBACK BIT(1) 1619f93ac8dSLABBE Corentin #define EMAC_SPEED_1000 0 1629f93ac8dSLABBE Corentin #define EMAC_SPEED_100 (0x03 << 2) 1639f93ac8dSLABBE Corentin #define EMAC_SPEED_10 (0x02 << 2) 1649f93ac8dSLABBE Corentin 1659f93ac8dSLABBE Corentin /* Use in EMAC_BASIC_CTL1 */ 1669f93ac8dSLABBE Corentin #define EMAC_BURSTLEN_SHIFT 24 1679f93ac8dSLABBE Corentin 1689f93ac8dSLABBE Corentin /* Used in EMAC_RX_FRM_FLT */ 1699f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_RXALL BIT(0) 1709f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_CTL BIT(13) 1719f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_MULTICAST BIT(16) 1729f93ac8dSLABBE Corentin 1739f93ac8dSLABBE Corentin /* Used in RX_CTL1*/ 1749f93ac8dSLABBE Corentin #define EMAC_RX_MD BIT(1) 1759f93ac8dSLABBE Corentin #define EMAC_RX_TH_MASK GENMASK(4, 5) 1769f93ac8dSLABBE Corentin #define EMAC_RX_TH_32 0 1779f93ac8dSLABBE Corentin #define EMAC_RX_TH_64 (0x1 << 4) 1789f93ac8dSLABBE Corentin #define EMAC_RX_TH_96 (0x2 << 4) 1799f93ac8dSLABBE Corentin #define EMAC_RX_TH_128 (0x3 << 4) 1809f93ac8dSLABBE Corentin #define EMAC_RX_DMA_EN BIT(30) 1819f93ac8dSLABBE Corentin #define EMAC_RX_DMA_START BIT(31) 1829f93ac8dSLABBE Corentin 1839f93ac8dSLABBE Corentin /* Used in TX_CTL1*/ 1849f93ac8dSLABBE Corentin #define EMAC_TX_MD BIT(1) 1859f93ac8dSLABBE Corentin #define EMAC_TX_NEXT_FRM BIT(2) 1869f93ac8dSLABBE Corentin #define EMAC_TX_TH_MASK GENMASK(8, 10) 1879f93ac8dSLABBE Corentin #define EMAC_TX_TH_64 0 1889f93ac8dSLABBE Corentin #define EMAC_TX_TH_128 (0x1 << 8) 1899f93ac8dSLABBE Corentin #define EMAC_TX_TH_192 (0x2 << 8) 1909f93ac8dSLABBE Corentin #define EMAC_TX_TH_256 (0x3 << 8) 1919f93ac8dSLABBE Corentin #define EMAC_TX_DMA_EN BIT(30) 1929f93ac8dSLABBE Corentin #define EMAC_TX_DMA_START BIT(31) 1939f93ac8dSLABBE Corentin 1949f93ac8dSLABBE Corentin /* Used in RX_CTL0 */ 1959f93ac8dSLABBE Corentin #define EMAC_RX_RECEIVER_EN BIT(31) 1969f93ac8dSLABBE Corentin #define EMAC_RX_DO_CRC BIT(27) 1979f93ac8dSLABBE Corentin #define EMAC_RX_FLOW_CTL_EN BIT(16) 1989f93ac8dSLABBE Corentin 1999f93ac8dSLABBE Corentin /* Used in TX_CTL0 */ 2009f93ac8dSLABBE Corentin #define EMAC_TX_TRANSMITTER_EN BIT(31) 2019f93ac8dSLABBE Corentin 2029f93ac8dSLABBE Corentin /* Used in EMAC_TX_FLOW_CTL */ 2039f93ac8dSLABBE Corentin #define EMAC_TX_FLOW_CTL_EN BIT(0) 2049f93ac8dSLABBE Corentin 2059f93ac8dSLABBE Corentin /* Used in EMAC_INT_STA */ 2069f93ac8dSLABBE Corentin #define EMAC_TX_INT BIT(0) 2079f93ac8dSLABBE Corentin #define EMAC_TX_DMA_STOP_INT BIT(1) 2089f93ac8dSLABBE Corentin #define EMAC_TX_BUF_UA_INT BIT(2) 2099f93ac8dSLABBE Corentin #define EMAC_TX_TIMEOUT_INT BIT(3) 2109f93ac8dSLABBE Corentin #define EMAC_TX_UNDERFLOW_INT BIT(4) 2119f93ac8dSLABBE Corentin #define EMAC_TX_EARLY_INT BIT(5) 2129f93ac8dSLABBE Corentin #define EMAC_RX_INT BIT(8) 2139f93ac8dSLABBE Corentin #define EMAC_RX_BUF_UA_INT BIT(9) 2149f93ac8dSLABBE Corentin #define EMAC_RX_DMA_STOP_INT BIT(10) 2159f93ac8dSLABBE Corentin #define EMAC_RX_TIMEOUT_INT BIT(11) 2169f93ac8dSLABBE Corentin #define EMAC_RX_OVERFLOW_INT BIT(12) 2179f93ac8dSLABBE Corentin #define EMAC_RX_EARLY_INT BIT(13) 2189f93ac8dSLABBE Corentin #define EMAC_RGMII_STA_INT BIT(16) 2199f93ac8dSLABBE Corentin 2209f93ac8dSLABBE Corentin #define MAC_ADDR_TYPE_DST BIT(31) 2219f93ac8dSLABBE Corentin 2229f93ac8dSLABBE Corentin /* H3 specific bits for EPHY */ 2239f93ac8dSLABBE Corentin #define H3_EPHY_ADDR_SHIFT 20 2241450ba8aSIcenowy Zheng #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 2259f93ac8dSLABBE Corentin #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 2269f93ac8dSLABBE Corentin #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 2279f93ac8dSLABBE Corentin #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 228634db83bSCorentin Labbe #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 229634db83bSCorentin Labbe #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 230634db83bSCorentin Labbe #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 2319f93ac8dSLABBE Corentin 2329f93ac8dSLABBE Corentin /* H3/A64 specific bits */ 2339f93ac8dSLABBE Corentin #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 2349f93ac8dSLABBE Corentin 2359f93ac8dSLABBE Corentin /* Generic system control EMAC_CLK bits */ 2369f93ac8dSLABBE Corentin #define SYSCON_ETXDC_SHIFT 10 2379f93ac8dSLABBE Corentin #define SYSCON_ERXDC_SHIFT 5 2389f93ac8dSLABBE Corentin /* EMAC PHY Interface Type */ 2399f93ac8dSLABBE Corentin #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 2409f93ac8dSLABBE Corentin #define SYSCON_ETCS_MASK GENMASK(1, 0) 2419f93ac8dSLABBE Corentin #define SYSCON_ETCS_MII 0x0 2429f93ac8dSLABBE Corentin #define SYSCON_ETCS_EXT_GMII 0x1 2439f93ac8dSLABBE Corentin #define SYSCON_ETCS_INT_GMII 0x2 2449f93ac8dSLABBE Corentin 2459f93ac8dSLABBE Corentin /* sun8i_dwmac_dma_reset() - reset the EMAC 2469f93ac8dSLABBE Corentin * Called from stmmac via stmmac_dma_ops->reset 2479f93ac8dSLABBE Corentin */ 2489f93ac8dSLABBE Corentin static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 2499f93ac8dSLABBE Corentin { 2509f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_CTL1); 2519f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_TX_CTL1); 2529f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_FRM_FLT); 2539f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_DESC_LIST); 2549f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_TX_DESC_LIST); 2559f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_INT_EN); 2569f93ac8dSLABBE Corentin writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 2579f93ac8dSLABBE Corentin return 0; 2589f93ac8dSLABBE Corentin } 2599f93ac8dSLABBE Corentin 2609f93ac8dSLABBE Corentin /* sun8i_dwmac_dma_init() - initialize the EMAC 2619f93ac8dSLABBE Corentin * Called from stmmac via stmmac_dma_ops->init 2629f93ac8dSLABBE Corentin */ 2639f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 2649f93ac8dSLABBE Corentin struct stmmac_dma_cfg *dma_cfg, 2659f93ac8dSLABBE Corentin u32 dma_tx, u32 dma_rx, int atds) 2669f93ac8dSLABBE Corentin { 2679f93ac8dSLABBE Corentin /* Write TX and RX descriptors address */ 2689f93ac8dSLABBE Corentin writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST); 2699f93ac8dSLABBE Corentin writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST); 2709f93ac8dSLABBE Corentin 2719f93ac8dSLABBE Corentin writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 2729f93ac8dSLABBE Corentin writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 2739f93ac8dSLABBE Corentin } 2749f93ac8dSLABBE Corentin 2759f93ac8dSLABBE Corentin /* sun8i_dwmac_dump_regs() - Dump EMAC address space 2769f93ac8dSLABBE Corentin * Called from stmmac_dma_ops->dump_regs 2779f93ac8dSLABBE Corentin * Used for ethtool 2789f93ac8dSLABBE Corentin */ 2799f93ac8dSLABBE Corentin static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) 2809f93ac8dSLABBE Corentin { 2819f93ac8dSLABBE Corentin int i; 2829f93ac8dSLABBE Corentin 2839f93ac8dSLABBE Corentin for (i = 0; i < 0xC8; i += 4) { 2849f93ac8dSLABBE Corentin if (i == 0x32 || i == 0x3C) 2859f93ac8dSLABBE Corentin continue; 2869f93ac8dSLABBE Corentin reg_space[i / 4] = readl(ioaddr + i); 2879f93ac8dSLABBE Corentin } 2889f93ac8dSLABBE Corentin } 2899f93ac8dSLABBE Corentin 2909f93ac8dSLABBE Corentin /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 2919f93ac8dSLABBE Corentin * Called from stmmac_ops->dump_regs 2929f93ac8dSLABBE Corentin * Used for ethtool 2939f93ac8dSLABBE Corentin */ 2949f93ac8dSLABBE Corentin static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 2959f93ac8dSLABBE Corentin u32 *reg_space) 2969f93ac8dSLABBE Corentin { 2979f93ac8dSLABBE Corentin int i; 2989f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 2999f93ac8dSLABBE Corentin 3009f93ac8dSLABBE Corentin for (i = 0; i < 0xC8; i += 4) { 3019f93ac8dSLABBE Corentin if (i == 0x32 || i == 0x3C) 3029f93ac8dSLABBE Corentin continue; 3039f93ac8dSLABBE Corentin reg_space[i / 4] = readl(ioaddr + i); 3049f93ac8dSLABBE Corentin } 3059f93ac8dSLABBE Corentin } 3069f93ac8dSLABBE Corentin 3079f93ac8dSLABBE Corentin static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) 3089f93ac8dSLABBE Corentin { 3099f93ac8dSLABBE Corentin writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 3109f93ac8dSLABBE Corentin } 3119f93ac8dSLABBE Corentin 3129f93ac8dSLABBE Corentin static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 3139f93ac8dSLABBE Corentin { 3149f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_INT_EN); 3159f93ac8dSLABBE Corentin } 3169f93ac8dSLABBE Corentin 3179f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) 3189f93ac8dSLABBE Corentin { 3199f93ac8dSLABBE Corentin u32 v; 3209f93ac8dSLABBE Corentin 3219f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3229f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_START; 3239f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_EN; 3249f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3259f93ac8dSLABBE Corentin } 3269f93ac8dSLABBE Corentin 3279f93ac8dSLABBE Corentin static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 3289f93ac8dSLABBE Corentin { 3299f93ac8dSLABBE Corentin u32 v; 3309f93ac8dSLABBE Corentin 3319f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3329f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_START; 3339f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_EN; 3349f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3359f93ac8dSLABBE Corentin } 3369f93ac8dSLABBE Corentin 3379f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 3389f93ac8dSLABBE Corentin { 3399f93ac8dSLABBE Corentin u32 v; 3409f93ac8dSLABBE Corentin 3419f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3429f93ac8dSLABBE Corentin v &= ~EMAC_TX_DMA_EN; 3439f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3449f93ac8dSLABBE Corentin } 3459f93ac8dSLABBE Corentin 3469f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 3479f93ac8dSLABBE Corentin { 3489f93ac8dSLABBE Corentin u32 v; 3499f93ac8dSLABBE Corentin 3509f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 3519f93ac8dSLABBE Corentin v |= EMAC_RX_DMA_START; 3529f93ac8dSLABBE Corentin v |= EMAC_RX_DMA_EN; 3539f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 3549f93ac8dSLABBE Corentin } 3559f93ac8dSLABBE Corentin 3569f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 3579f93ac8dSLABBE Corentin { 3589f93ac8dSLABBE Corentin u32 v; 3599f93ac8dSLABBE Corentin 3609f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 3619f93ac8dSLABBE Corentin v &= ~EMAC_RX_DMA_EN; 3629f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 3639f93ac8dSLABBE Corentin } 3649f93ac8dSLABBE Corentin 3659f93ac8dSLABBE Corentin static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 3669f93ac8dSLABBE Corentin struct stmmac_extra_stats *x, u32 chan) 3679f93ac8dSLABBE Corentin { 3689f93ac8dSLABBE Corentin u32 v; 3699f93ac8dSLABBE Corentin int ret = 0; 3709f93ac8dSLABBE Corentin 3719f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_INT_STA); 3729f93ac8dSLABBE Corentin 3739f93ac8dSLABBE Corentin if (v & EMAC_TX_INT) { 3749f93ac8dSLABBE Corentin ret |= handle_tx; 3759f93ac8dSLABBE Corentin x->tx_normal_irq_n++; 3769f93ac8dSLABBE Corentin } 3779f93ac8dSLABBE Corentin 3789f93ac8dSLABBE Corentin if (v & EMAC_TX_DMA_STOP_INT) 3799f93ac8dSLABBE Corentin x->tx_process_stopped_irq++; 3809f93ac8dSLABBE Corentin 3819f93ac8dSLABBE Corentin if (v & EMAC_TX_BUF_UA_INT) 3829f93ac8dSLABBE Corentin x->tx_process_stopped_irq++; 3839f93ac8dSLABBE Corentin 3849f93ac8dSLABBE Corentin if (v & EMAC_TX_TIMEOUT_INT) 3859f93ac8dSLABBE Corentin ret |= tx_hard_error; 3869f93ac8dSLABBE Corentin 3879f93ac8dSLABBE Corentin if (v & EMAC_TX_UNDERFLOW_INT) { 3889f93ac8dSLABBE Corentin ret |= tx_hard_error; 3899f93ac8dSLABBE Corentin x->tx_undeflow_irq++; 3909f93ac8dSLABBE Corentin } 3919f93ac8dSLABBE Corentin 3929f93ac8dSLABBE Corentin if (v & EMAC_TX_EARLY_INT) 3939f93ac8dSLABBE Corentin x->tx_early_irq++; 3949f93ac8dSLABBE Corentin 3959f93ac8dSLABBE Corentin if (v & EMAC_RX_INT) { 3969f93ac8dSLABBE Corentin ret |= handle_rx; 3979f93ac8dSLABBE Corentin x->rx_normal_irq_n++; 3989f93ac8dSLABBE Corentin } 3999f93ac8dSLABBE Corentin 4009f93ac8dSLABBE Corentin if (v & EMAC_RX_BUF_UA_INT) 4019f93ac8dSLABBE Corentin x->rx_buf_unav_irq++; 4029f93ac8dSLABBE Corentin 4039f93ac8dSLABBE Corentin if (v & EMAC_RX_DMA_STOP_INT) 4049f93ac8dSLABBE Corentin x->rx_process_stopped_irq++; 4059f93ac8dSLABBE Corentin 4069f93ac8dSLABBE Corentin if (v & EMAC_RX_TIMEOUT_INT) 4079f93ac8dSLABBE Corentin ret |= tx_hard_error; 4089f93ac8dSLABBE Corentin 4099f93ac8dSLABBE Corentin if (v & EMAC_RX_OVERFLOW_INT) { 4109f93ac8dSLABBE Corentin ret |= tx_hard_error; 4119f93ac8dSLABBE Corentin x->rx_overflow_irq++; 4129f93ac8dSLABBE Corentin } 4139f93ac8dSLABBE Corentin 4149f93ac8dSLABBE Corentin if (v & EMAC_RX_EARLY_INT) 4159f93ac8dSLABBE Corentin x->rx_early_irq++; 4169f93ac8dSLABBE Corentin 4179f93ac8dSLABBE Corentin if (v & EMAC_RGMII_STA_INT) 4189f93ac8dSLABBE Corentin x->irq_rgmii_n++; 4199f93ac8dSLABBE Corentin 4209f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_INT_STA); 4219f93ac8dSLABBE Corentin 4229f93ac8dSLABBE Corentin return ret; 4239f93ac8dSLABBE Corentin } 4249f93ac8dSLABBE Corentin 4259f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode, 4269f93ac8dSLABBE Corentin int rxmode, int rxfifosz) 4279f93ac8dSLABBE Corentin { 4289f93ac8dSLABBE Corentin u32 v; 4299f93ac8dSLABBE Corentin 4309f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 4319f93ac8dSLABBE Corentin if (txmode == SF_DMA_MODE) { 4329f93ac8dSLABBE Corentin v |= EMAC_TX_MD; 4339f93ac8dSLABBE Corentin /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 4349f93ac8dSLABBE Corentin * comment is 4359f93ac8dSLABBE Corentin * "Operating on second frame increase the performance 4369f93ac8dSLABBE Corentin * especially when transmit store-and-forward is used." 4379f93ac8dSLABBE Corentin */ 4389f93ac8dSLABBE Corentin v |= EMAC_TX_NEXT_FRM; 4399f93ac8dSLABBE Corentin } else { 4409f93ac8dSLABBE Corentin v &= ~EMAC_TX_MD; 4419f93ac8dSLABBE Corentin v &= ~EMAC_TX_TH_MASK; 4429f93ac8dSLABBE Corentin if (txmode < 64) 4439f93ac8dSLABBE Corentin v |= EMAC_TX_TH_64; 4449f93ac8dSLABBE Corentin else if (txmode < 128) 4459f93ac8dSLABBE Corentin v |= EMAC_TX_TH_128; 4469f93ac8dSLABBE Corentin else if (txmode < 192) 4479f93ac8dSLABBE Corentin v |= EMAC_TX_TH_192; 4489f93ac8dSLABBE Corentin else if (txmode < 256) 4499f93ac8dSLABBE Corentin v |= EMAC_TX_TH_256; 4509f93ac8dSLABBE Corentin } 4519f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 4529f93ac8dSLABBE Corentin 4539f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 4549f93ac8dSLABBE Corentin if (rxmode == SF_DMA_MODE) { 4559f93ac8dSLABBE Corentin v |= EMAC_RX_MD; 4569f93ac8dSLABBE Corentin } else { 4579f93ac8dSLABBE Corentin v &= ~EMAC_RX_MD; 4589f93ac8dSLABBE Corentin v &= ~EMAC_RX_TH_MASK; 4599f93ac8dSLABBE Corentin if (rxmode < 32) 4609f93ac8dSLABBE Corentin v |= EMAC_RX_TH_32; 4619f93ac8dSLABBE Corentin else if (rxmode < 64) 4629f93ac8dSLABBE Corentin v |= EMAC_RX_TH_64; 4639f93ac8dSLABBE Corentin else if (rxmode < 96) 4649f93ac8dSLABBE Corentin v |= EMAC_RX_TH_96; 4659f93ac8dSLABBE Corentin else if (rxmode < 128) 4669f93ac8dSLABBE Corentin v |= EMAC_RX_TH_128; 4679f93ac8dSLABBE Corentin } 4689f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 4699f93ac8dSLABBE Corentin } 4709f93ac8dSLABBE Corentin 4719f93ac8dSLABBE Corentin static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 4729f93ac8dSLABBE Corentin .reset = sun8i_dwmac_dma_reset, 4739f93ac8dSLABBE Corentin .init = sun8i_dwmac_dma_init, 4749f93ac8dSLABBE Corentin .dump_regs = sun8i_dwmac_dump_regs, 4759f93ac8dSLABBE Corentin .dma_mode = sun8i_dwmac_dma_operation_mode, 4769f93ac8dSLABBE Corentin .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 4779f93ac8dSLABBE Corentin .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 4789f93ac8dSLABBE Corentin .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 4799f93ac8dSLABBE Corentin .start_tx = sun8i_dwmac_dma_start_tx, 4809f93ac8dSLABBE Corentin .stop_tx = sun8i_dwmac_dma_stop_tx, 4819f93ac8dSLABBE Corentin .start_rx = sun8i_dwmac_dma_start_rx, 4829f93ac8dSLABBE Corentin .stop_rx = sun8i_dwmac_dma_stop_rx, 4839f93ac8dSLABBE Corentin .dma_interrupt = sun8i_dwmac_dma_interrupt, 4849f93ac8dSLABBE Corentin }; 4859f93ac8dSLABBE Corentin 4869f93ac8dSLABBE Corentin static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 4879f93ac8dSLABBE Corentin { 4889f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv; 4899f93ac8dSLABBE Corentin int ret; 4909f93ac8dSLABBE Corentin 4919f93ac8dSLABBE Corentin if (gmac->regulator) { 4929f93ac8dSLABBE Corentin ret = regulator_enable(gmac->regulator); 4939f93ac8dSLABBE Corentin if (ret) { 4949f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Fail to enable regulator\n"); 4959f93ac8dSLABBE Corentin return ret; 4969f93ac8dSLABBE Corentin } 4979f93ac8dSLABBE Corentin } 4989f93ac8dSLABBE Corentin 4999f93ac8dSLABBE Corentin ret = clk_prepare_enable(gmac->tx_clk); 5009f93ac8dSLABBE Corentin if (ret) { 5019f93ac8dSLABBE Corentin if (gmac->regulator) 5029f93ac8dSLABBE Corentin regulator_disable(gmac->regulator); 5039f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Could not enable AHB clock\n"); 5049f93ac8dSLABBE Corentin return ret; 5059f93ac8dSLABBE Corentin } 5069f93ac8dSLABBE Corentin 5079f93ac8dSLABBE Corentin return 0; 5089f93ac8dSLABBE Corentin } 5099f93ac8dSLABBE Corentin 5108cad443eSFlorian Fainelli static void sun8i_dwmac_core_init(struct mac_device_info *hw, 5118cad443eSFlorian Fainelli struct net_device *dev) 5129f93ac8dSLABBE Corentin { 5139f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5149f93ac8dSLABBE Corentin u32 v; 5159f93ac8dSLABBE Corentin 5169f93ac8dSLABBE Corentin v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 5179f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_BASIC_CTL1); 5189f93ac8dSLABBE Corentin } 5199f93ac8dSLABBE Corentin 5209f93ac8dSLABBE Corentin static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 5219f93ac8dSLABBE Corentin { 5229f93ac8dSLABBE Corentin u32 t, r; 5239f93ac8dSLABBE Corentin 5249f93ac8dSLABBE Corentin t = readl(ioaddr + EMAC_TX_CTL0); 5259f93ac8dSLABBE Corentin r = readl(ioaddr + EMAC_RX_CTL0); 5269f93ac8dSLABBE Corentin if (enable) { 5279f93ac8dSLABBE Corentin t |= EMAC_TX_TRANSMITTER_EN; 5289f93ac8dSLABBE Corentin r |= EMAC_RX_RECEIVER_EN; 5299f93ac8dSLABBE Corentin } else { 5309f93ac8dSLABBE Corentin t &= ~EMAC_TX_TRANSMITTER_EN; 5319f93ac8dSLABBE Corentin r &= ~EMAC_RX_RECEIVER_EN; 5329f93ac8dSLABBE Corentin } 5339f93ac8dSLABBE Corentin writel(t, ioaddr + EMAC_TX_CTL0); 5349f93ac8dSLABBE Corentin writel(r, ioaddr + EMAC_RX_CTL0); 5359f93ac8dSLABBE Corentin } 5369f93ac8dSLABBE Corentin 5379f93ac8dSLABBE Corentin /* Set MAC address at slot reg_n 5389f93ac8dSLABBE Corentin * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 5399f93ac8dSLABBE Corentin * If addr is NULL, clear the slot 5409f93ac8dSLABBE Corentin */ 5419f93ac8dSLABBE Corentin static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 5429f93ac8dSLABBE Corentin unsigned char *addr, 5439f93ac8dSLABBE Corentin unsigned int reg_n) 5449f93ac8dSLABBE Corentin { 5459f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5469f93ac8dSLABBE Corentin u32 v; 5479f93ac8dSLABBE Corentin 5489f93ac8dSLABBE Corentin if (!addr) { 5499f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 5509f93ac8dSLABBE Corentin return; 5519f93ac8dSLABBE Corentin } 5529f93ac8dSLABBE Corentin 5539f93ac8dSLABBE Corentin stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 5549f93ac8dSLABBE Corentin EMAC_MACADDR_LO(reg_n)); 5559f93ac8dSLABBE Corentin if (reg_n > 0) { 5569f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 5579f93ac8dSLABBE Corentin v |= MAC_ADDR_TYPE_DST; 5589f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 5599f93ac8dSLABBE Corentin } 5609f93ac8dSLABBE Corentin } 5619f93ac8dSLABBE Corentin 5629f93ac8dSLABBE Corentin static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 5639f93ac8dSLABBE Corentin unsigned char *addr, 5649f93ac8dSLABBE Corentin unsigned int reg_n) 5659f93ac8dSLABBE Corentin { 5669f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5679f93ac8dSLABBE Corentin 5689f93ac8dSLABBE Corentin stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 5699f93ac8dSLABBE Corentin EMAC_MACADDR_LO(reg_n)); 5709f93ac8dSLABBE Corentin } 5719f93ac8dSLABBE Corentin 5729f93ac8dSLABBE Corentin /* caution this function must return non 0 to work */ 5739f93ac8dSLABBE Corentin static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 5749f93ac8dSLABBE Corentin { 5759f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5769f93ac8dSLABBE Corentin u32 v; 5779f93ac8dSLABBE Corentin 5789f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL0); 5799f93ac8dSLABBE Corentin v |= EMAC_RX_DO_CRC; 5809f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL0); 5819f93ac8dSLABBE Corentin 5829f93ac8dSLABBE Corentin return 1; 5839f93ac8dSLABBE Corentin } 5849f93ac8dSLABBE Corentin 5859f93ac8dSLABBE Corentin static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 5869f93ac8dSLABBE Corentin struct net_device *dev) 5879f93ac8dSLABBE Corentin { 5889f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 5899f93ac8dSLABBE Corentin u32 v; 5909f93ac8dSLABBE Corentin int i = 1; 5919f93ac8dSLABBE Corentin struct netdev_hw_addr *ha; 5929f93ac8dSLABBE Corentin int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 5939f93ac8dSLABBE Corentin 5949f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_CTL; 5959f93ac8dSLABBE Corentin 5969f93ac8dSLABBE Corentin if (dev->flags & IFF_PROMISC) { 5979f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_RXALL; 5989f93ac8dSLABBE Corentin } else if (dev->flags & IFF_ALLMULTI) { 5999f93ac8dSLABBE Corentin v |= EMAC_FRM_FLT_MULTICAST; 6009f93ac8dSLABBE Corentin } else if (macaddrs <= hw->unicast_filter_entries) { 6019f93ac8dSLABBE Corentin if (!netdev_mc_empty(dev)) { 6029f93ac8dSLABBE Corentin netdev_for_each_mc_addr(ha, dev) { 6039f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 6049f93ac8dSLABBE Corentin i++; 6059f93ac8dSLABBE Corentin } 6069f93ac8dSLABBE Corentin } 6079f93ac8dSLABBE Corentin if (!netdev_uc_empty(dev)) { 6089f93ac8dSLABBE Corentin netdev_for_each_uc_addr(ha, dev) { 6099f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 6109f93ac8dSLABBE Corentin i++; 6119f93ac8dSLABBE Corentin } 6129f93ac8dSLABBE Corentin } 6139f93ac8dSLABBE Corentin } else { 6149f93ac8dSLABBE Corentin netdev_info(dev, "Too many address, switching to promiscuous\n"); 6159f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_RXALL; 6169f93ac8dSLABBE Corentin } 6179f93ac8dSLABBE Corentin 6189f93ac8dSLABBE Corentin /* Disable unused address filter slots */ 6199f93ac8dSLABBE Corentin while (i < hw->unicast_filter_entries) 6209f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, NULL, i++); 6219f93ac8dSLABBE Corentin 6229f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_FRM_FLT); 6239f93ac8dSLABBE Corentin } 6249f93ac8dSLABBE Corentin 6259f93ac8dSLABBE Corentin static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 6269f93ac8dSLABBE Corentin unsigned int duplex, unsigned int fc, 6279f93ac8dSLABBE Corentin unsigned int pause_time, u32 tx_cnt) 6289f93ac8dSLABBE Corentin { 6299f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6309f93ac8dSLABBE Corentin u32 v; 6319f93ac8dSLABBE Corentin 6329f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL0); 6339f93ac8dSLABBE Corentin if (fc == FLOW_AUTO) 6349f93ac8dSLABBE Corentin v |= EMAC_RX_FLOW_CTL_EN; 6359f93ac8dSLABBE Corentin else 6369f93ac8dSLABBE Corentin v &= ~EMAC_RX_FLOW_CTL_EN; 6379f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL0); 6389f93ac8dSLABBE Corentin 6399f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_FLOW_CTL); 6409f93ac8dSLABBE Corentin if (fc == FLOW_AUTO) 6419f93ac8dSLABBE Corentin v |= EMAC_TX_FLOW_CTL_EN; 6429f93ac8dSLABBE Corentin else 6439f93ac8dSLABBE Corentin v &= ~EMAC_TX_FLOW_CTL_EN; 6449f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_FLOW_CTL); 6459f93ac8dSLABBE Corentin } 6469f93ac8dSLABBE Corentin 6479f93ac8dSLABBE Corentin static int sun8i_dwmac_reset(struct stmmac_priv *priv) 6489f93ac8dSLABBE Corentin { 6499f93ac8dSLABBE Corentin u32 v; 6509f93ac8dSLABBE Corentin int err; 6519f93ac8dSLABBE Corentin 6529f93ac8dSLABBE Corentin v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 6539f93ac8dSLABBE Corentin writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 6549f93ac8dSLABBE Corentin 6559f93ac8dSLABBE Corentin /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 6569f93ac8dSLABBE Corentin * need more if no cable plugged. 100ms seems OK 6579f93ac8dSLABBE Corentin */ 6589f93ac8dSLABBE Corentin err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 6599f93ac8dSLABBE Corentin !(v & 0x01), 100, 100000); 6609f93ac8dSLABBE Corentin 6619f93ac8dSLABBE Corentin if (err) { 6629f93ac8dSLABBE Corentin dev_err(priv->device, "EMAC reset timeout\n"); 6639f93ac8dSLABBE Corentin return -EFAULT; 6649f93ac8dSLABBE Corentin } 6659f93ac8dSLABBE Corentin return 0; 6669f93ac8dSLABBE Corentin } 6679f93ac8dSLABBE Corentin 668634db83bSCorentin Labbe /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 669634db83bSCorentin Labbe static int get_ephy_nodes(struct stmmac_priv *priv) 670634db83bSCorentin Labbe { 671634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 672634db83bSCorentin Labbe struct device_node *mdio_mux, *iphynode; 673634db83bSCorentin Labbe struct device_node *mdio_internal; 674634db83bSCorentin Labbe int ret; 675634db83bSCorentin Labbe 676634db83bSCorentin Labbe mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 677634db83bSCorentin Labbe if (!mdio_mux) { 678634db83bSCorentin Labbe dev_err(priv->device, "Cannot get mdio-mux node\n"); 679634db83bSCorentin Labbe return -ENODEV; 680634db83bSCorentin Labbe } 681634db83bSCorentin Labbe 682634db83bSCorentin Labbe mdio_internal = of_find_compatible_node(mdio_mux, NULL, 683634db83bSCorentin Labbe "allwinner,sun8i-h3-mdio-internal"); 684634db83bSCorentin Labbe if (!mdio_internal) { 685634db83bSCorentin Labbe dev_err(priv->device, "Cannot get internal_mdio node\n"); 686634db83bSCorentin Labbe return -ENODEV; 687634db83bSCorentin Labbe } 688634db83bSCorentin Labbe 689634db83bSCorentin Labbe /* Seek for internal PHY */ 690634db83bSCorentin Labbe for_each_child_of_node(mdio_internal, iphynode) { 691634db83bSCorentin Labbe gmac->ephy_clk = of_clk_get(iphynode, 0); 692634db83bSCorentin Labbe if (IS_ERR(gmac->ephy_clk)) 693634db83bSCorentin Labbe continue; 694634db83bSCorentin Labbe gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 695634db83bSCorentin Labbe if (IS_ERR(gmac->rst_ephy)) { 696634db83bSCorentin Labbe ret = PTR_ERR(gmac->rst_ephy); 697634db83bSCorentin Labbe if (ret == -EPROBE_DEFER) 698634db83bSCorentin Labbe return ret; 699634db83bSCorentin Labbe continue; 700634db83bSCorentin Labbe } 701634db83bSCorentin Labbe dev_info(priv->device, "Found internal PHY node\n"); 702634db83bSCorentin Labbe return 0; 703634db83bSCorentin Labbe } 704634db83bSCorentin Labbe return -ENODEV; 705634db83bSCorentin Labbe } 706634db83bSCorentin Labbe 707634db83bSCorentin Labbe static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 708634db83bSCorentin Labbe { 709634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 710634db83bSCorentin Labbe int ret; 711634db83bSCorentin Labbe 712634db83bSCorentin Labbe if (gmac->internal_phy_powered) { 713634db83bSCorentin Labbe dev_warn(priv->device, "Internal PHY already powered\n"); 714634db83bSCorentin Labbe return 0; 715634db83bSCorentin Labbe } 716634db83bSCorentin Labbe 717634db83bSCorentin Labbe dev_info(priv->device, "Powering internal PHY\n"); 718634db83bSCorentin Labbe ret = clk_prepare_enable(gmac->ephy_clk); 719634db83bSCorentin Labbe if (ret) { 720634db83bSCorentin Labbe dev_err(priv->device, "Cannot enable internal PHY\n"); 721634db83bSCorentin Labbe return ret; 722634db83bSCorentin Labbe } 723634db83bSCorentin Labbe 724634db83bSCorentin Labbe /* Make sure the EPHY is properly reseted, as U-Boot may leave 725634db83bSCorentin Labbe * it at deasserted state, and thus it may fail to reset EMAC. 726634db83bSCorentin Labbe */ 727634db83bSCorentin Labbe reset_control_assert(gmac->rst_ephy); 728634db83bSCorentin Labbe 729634db83bSCorentin Labbe ret = reset_control_deassert(gmac->rst_ephy); 730634db83bSCorentin Labbe if (ret) { 731634db83bSCorentin Labbe dev_err(priv->device, "Cannot deassert internal phy\n"); 732634db83bSCorentin Labbe clk_disable_unprepare(gmac->ephy_clk); 733634db83bSCorentin Labbe return ret; 734634db83bSCorentin Labbe } 735634db83bSCorentin Labbe 736634db83bSCorentin Labbe gmac->internal_phy_powered = true; 737634db83bSCorentin Labbe 738634db83bSCorentin Labbe return 0; 739634db83bSCorentin Labbe } 740634db83bSCorentin Labbe 741634db83bSCorentin Labbe static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 742634db83bSCorentin Labbe { 743634db83bSCorentin Labbe if (!gmac->internal_phy_powered) 744634db83bSCorentin Labbe return 0; 745634db83bSCorentin Labbe 746634db83bSCorentin Labbe clk_disable_unprepare(gmac->ephy_clk); 747634db83bSCorentin Labbe reset_control_assert(gmac->rst_ephy); 748634db83bSCorentin Labbe gmac->internal_phy_powered = false; 749634db83bSCorentin Labbe return 0; 750634db83bSCorentin Labbe } 751634db83bSCorentin Labbe 752634db83bSCorentin Labbe /* MDIO multiplexing switch function 753634db83bSCorentin Labbe * This function is called by the mdio-mux layer when it thinks the mdio bus 754634db83bSCorentin Labbe * multiplexer needs to switch. 755634db83bSCorentin Labbe * 'current_child' is the current value of the mux register 756634db83bSCorentin Labbe * 'desired_child' is the value of the 'reg' property of the target child MDIO 757634db83bSCorentin Labbe * node. 758634db83bSCorentin Labbe * The first time this function is called, current_child == -1. 759634db83bSCorentin Labbe * If current_child == desired_child, then the mux is already set to the 760634db83bSCorentin Labbe * correct bus. 761634db83bSCorentin Labbe */ 762634db83bSCorentin Labbe static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 763634db83bSCorentin Labbe void *data) 764634db83bSCorentin Labbe { 765634db83bSCorentin Labbe struct stmmac_priv *priv = data; 766634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 767634db83bSCorentin Labbe u32 reg, val; 768634db83bSCorentin Labbe int ret = 0; 769634db83bSCorentin Labbe bool need_power_ephy = false; 770634db83bSCorentin Labbe 771634db83bSCorentin Labbe if (current_child ^ desired_child) { 77225ae15fbSChen-Yu Tsai regmap_field_read(gmac->regmap_field, ®); 773634db83bSCorentin Labbe switch (desired_child) { 774634db83bSCorentin Labbe case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 775634db83bSCorentin Labbe dev_info(priv->device, "Switch mux to internal PHY"); 776634db83bSCorentin Labbe val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 777634db83bSCorentin Labbe 778634db83bSCorentin Labbe need_power_ephy = true; 779634db83bSCorentin Labbe break; 780634db83bSCorentin Labbe case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 781634db83bSCorentin Labbe dev_info(priv->device, "Switch mux to external PHY"); 782634db83bSCorentin Labbe val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 783634db83bSCorentin Labbe need_power_ephy = false; 784634db83bSCorentin Labbe break; 785634db83bSCorentin Labbe default: 786634db83bSCorentin Labbe dev_err(priv->device, "Invalid child ID %x\n", 787634db83bSCorentin Labbe desired_child); 788634db83bSCorentin Labbe return -EINVAL; 789634db83bSCorentin Labbe } 79025ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, val); 791634db83bSCorentin Labbe if (need_power_ephy) { 792634db83bSCorentin Labbe ret = sun8i_dwmac_power_internal_phy(priv); 793634db83bSCorentin Labbe if (ret) 794634db83bSCorentin Labbe return ret; 795634db83bSCorentin Labbe } else { 796634db83bSCorentin Labbe sun8i_dwmac_unpower_internal_phy(gmac); 797634db83bSCorentin Labbe } 798634db83bSCorentin Labbe /* After changing syscon value, the MAC need reset or it will 799634db83bSCorentin Labbe * use the last value (and so the last PHY set). 800634db83bSCorentin Labbe */ 801634db83bSCorentin Labbe ret = sun8i_dwmac_reset(priv); 802634db83bSCorentin Labbe } 803634db83bSCorentin Labbe return ret; 804634db83bSCorentin Labbe } 805634db83bSCorentin Labbe 806634db83bSCorentin Labbe static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 807634db83bSCorentin Labbe { 808634db83bSCorentin Labbe int ret; 809634db83bSCorentin Labbe struct device_node *mdio_mux; 810634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 811634db83bSCorentin Labbe 812634db83bSCorentin Labbe mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 813634db83bSCorentin Labbe if (!mdio_mux) 814634db83bSCorentin Labbe return -ENODEV; 815634db83bSCorentin Labbe 816634db83bSCorentin Labbe ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 817634db83bSCorentin Labbe &gmac->mux_handle, priv, priv->mii); 818634db83bSCorentin Labbe return ret; 819634db83bSCorentin Labbe } 820634db83bSCorentin Labbe 8219f93ac8dSLABBE Corentin static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) 8229f93ac8dSLABBE Corentin { 8239f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 8249f93ac8dSLABBE Corentin struct device_node *node = priv->device->of_node; 825d93b07f8SLABBE Corentin int ret; 8269f93ac8dSLABBE Corentin u32 reg, val; 8279f93ac8dSLABBE Corentin 82825ae15fbSChen-Yu Tsai regmap_field_read(gmac->regmap_field, &val); 8299f93ac8dSLABBE Corentin reg = gmac->variant->default_syscon_value; 8309f93ac8dSLABBE Corentin if (reg != val) 8319f93ac8dSLABBE Corentin dev_warn(priv->device, 8329f93ac8dSLABBE Corentin "Current syscon value is not the default %x (expect %x)\n", 8339f93ac8dSLABBE Corentin val, reg); 8349f93ac8dSLABBE Corentin 835634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 8361c08ac0cSCorentin Labbe if (of_property_read_bool(node, "allwinner,leds-active-low")) 8379f93ac8dSLABBE Corentin reg |= H3_EPHY_LED_POL; 8389f93ac8dSLABBE Corentin else 8399f93ac8dSLABBE Corentin reg &= ~H3_EPHY_LED_POL; 8409f93ac8dSLABBE Corentin 8411450ba8aSIcenowy Zheng /* Force EPHY xtal frequency to 24MHz. */ 8421450ba8aSIcenowy Zheng reg |= H3_EPHY_CLK_SEL; 8431450ba8aSIcenowy Zheng 844634db83bSCorentin Labbe ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); 8459f93ac8dSLABBE Corentin if (ret < 0) { 8469f93ac8dSLABBE Corentin dev_err(priv->device, "Could not parse MDIO addr\n"); 8479f93ac8dSLABBE Corentin return ret; 8489f93ac8dSLABBE Corentin } 8499f93ac8dSLABBE Corentin /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 8509f93ac8dSLABBE Corentin * address. No need to mask it again. 8519f93ac8dSLABBE Corentin */ 852634db83bSCorentin Labbe reg |= 1 << H3_EPHY_ADDR_SHIFT; 8539f93ac8dSLABBE Corentin } 8549f93ac8dSLABBE Corentin 8559f93ac8dSLABBE Corentin if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 8569f93ac8dSLABBE Corentin if (val % 100) { 8579f93ac8dSLABBE Corentin dev_err(priv->device, "tx-delay must be a multiple of 100\n"); 8589f93ac8dSLABBE Corentin return -EINVAL; 8599f93ac8dSLABBE Corentin } 8609f93ac8dSLABBE Corentin val /= 100; 8619f93ac8dSLABBE Corentin dev_dbg(priv->device, "set tx-delay to %x\n", val); 8627b270b72SChen-Yu Tsai if (val <= gmac->variant->tx_delay_max) { 8637b270b72SChen-Yu Tsai reg &= ~(gmac->variant->tx_delay_max << 8647b270b72SChen-Yu Tsai SYSCON_ETXDC_SHIFT); 8659f93ac8dSLABBE Corentin reg |= (val << SYSCON_ETXDC_SHIFT); 8669f93ac8dSLABBE Corentin } else { 8679f93ac8dSLABBE Corentin dev_err(priv->device, "Invalid TX clock delay: %d\n", 8689f93ac8dSLABBE Corentin val); 8699f93ac8dSLABBE Corentin return -EINVAL; 8709f93ac8dSLABBE Corentin } 8719f93ac8dSLABBE Corentin } 8729f93ac8dSLABBE Corentin 8739f93ac8dSLABBE Corentin if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 8749f93ac8dSLABBE Corentin if (val % 100) { 8759f93ac8dSLABBE Corentin dev_err(priv->device, "rx-delay must be a multiple of 100\n"); 8769f93ac8dSLABBE Corentin return -EINVAL; 8779f93ac8dSLABBE Corentin } 8789f93ac8dSLABBE Corentin val /= 100; 8799f93ac8dSLABBE Corentin dev_dbg(priv->device, "set rx-delay to %x\n", val); 8807b270b72SChen-Yu Tsai if (val <= gmac->variant->rx_delay_max) { 8817b270b72SChen-Yu Tsai reg &= ~(gmac->variant->rx_delay_max << 8827b270b72SChen-Yu Tsai SYSCON_ERXDC_SHIFT); 8839f93ac8dSLABBE Corentin reg |= (val << SYSCON_ERXDC_SHIFT); 8849f93ac8dSLABBE Corentin } else { 8859f93ac8dSLABBE Corentin dev_err(priv->device, "Invalid RX clock delay: %d\n", 8869f93ac8dSLABBE Corentin val); 8879f93ac8dSLABBE Corentin return -EINVAL; 8889f93ac8dSLABBE Corentin } 8899f93ac8dSLABBE Corentin } 8909f93ac8dSLABBE Corentin 8919f93ac8dSLABBE Corentin /* Clear interface mode bits */ 8929f93ac8dSLABBE Corentin reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 8939f93ac8dSLABBE Corentin if (gmac->variant->support_rmii) 8949f93ac8dSLABBE Corentin reg &= ~SYSCON_RMII_EN; 8959f93ac8dSLABBE Corentin 896d93b07f8SLABBE Corentin switch (priv->plat->interface) { 8979f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_MII: 8989f93ac8dSLABBE Corentin /* default */ 8999f93ac8dSLABBE Corentin break; 9009f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_RGMII: 9019f93ac8dSLABBE Corentin reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 9029f93ac8dSLABBE Corentin break; 9039f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_RMII: 9049f93ac8dSLABBE Corentin reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 9059f93ac8dSLABBE Corentin break; 9069f93ac8dSLABBE Corentin default: 9079f93ac8dSLABBE Corentin dev_err(priv->device, "Unsupported interface mode: %s", 9089f93ac8dSLABBE Corentin phy_modes(priv->plat->interface)); 9099f93ac8dSLABBE Corentin return -EINVAL; 9109f93ac8dSLABBE Corentin } 9119f93ac8dSLABBE Corentin 91225ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, reg); 9139f93ac8dSLABBE Corentin 9149f93ac8dSLABBE Corentin return 0; 9159f93ac8dSLABBE Corentin } 9169f93ac8dSLABBE Corentin 9179f93ac8dSLABBE Corentin static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 9189f93ac8dSLABBE Corentin { 9199f93ac8dSLABBE Corentin u32 reg = gmac->variant->default_syscon_value; 9209f93ac8dSLABBE Corentin 92125ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, reg); 9229f93ac8dSLABBE Corentin } 9239f93ac8dSLABBE Corentin 9249f93ac8dSLABBE Corentin static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 9259f93ac8dSLABBE Corentin { 9269f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv; 9279f93ac8dSLABBE Corentin 928634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 929634db83bSCorentin Labbe /* sun8i_dwmac_exit could be called with mdiomux uninit */ 930634db83bSCorentin Labbe if (gmac->mux_handle) 931634db83bSCorentin Labbe mdio_mux_uninit(gmac->mux_handle); 932634db83bSCorentin Labbe if (gmac->internal_phy_powered) 933634db83bSCorentin Labbe sun8i_dwmac_unpower_internal_phy(gmac); 934634db83bSCorentin Labbe } 935634db83bSCorentin Labbe 936634db83bSCorentin Labbe sun8i_dwmac_unset_syscon(gmac); 937634db83bSCorentin Labbe 938634db83bSCorentin Labbe reset_control_put(gmac->rst_ephy); 9399f93ac8dSLABBE Corentin 9409f93ac8dSLABBE Corentin clk_disable_unprepare(gmac->tx_clk); 9419f93ac8dSLABBE Corentin 9429f93ac8dSLABBE Corentin if (gmac->regulator) 9439f93ac8dSLABBE Corentin regulator_disable(gmac->regulator); 9449f93ac8dSLABBE Corentin } 9459f93ac8dSLABBE Corentin 9469f93ac8dSLABBE Corentin static const struct stmmac_ops sun8i_dwmac_ops = { 9479f93ac8dSLABBE Corentin .core_init = sun8i_dwmac_core_init, 9489f93ac8dSLABBE Corentin .set_mac = sun8i_dwmac_set_mac, 9499f93ac8dSLABBE Corentin .dump_regs = sun8i_dwmac_dump_mac_regs, 9509f93ac8dSLABBE Corentin .rx_ipc = sun8i_dwmac_rx_ipc_enable, 9519f93ac8dSLABBE Corentin .set_filter = sun8i_dwmac_set_filter, 9529f93ac8dSLABBE Corentin .flow_ctrl = sun8i_dwmac_flow_ctrl, 9539f93ac8dSLABBE Corentin .set_umac_addr = sun8i_dwmac_set_umac_addr, 9549f93ac8dSLABBE Corentin .get_umac_addr = sun8i_dwmac_get_umac_addr, 9559f93ac8dSLABBE Corentin }; 9569f93ac8dSLABBE Corentin 9579f93ac8dSLABBE Corentin static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 9589f93ac8dSLABBE Corentin { 9599f93ac8dSLABBE Corentin struct mac_device_info *mac; 9609f93ac8dSLABBE Corentin struct stmmac_priv *priv = ppriv; 9619f93ac8dSLABBE Corentin int ret; 9629f93ac8dSLABBE Corentin 9639f93ac8dSLABBE Corentin mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 9649f93ac8dSLABBE Corentin if (!mac) 9659f93ac8dSLABBE Corentin return NULL; 9669f93ac8dSLABBE Corentin 967634db83bSCorentin Labbe ret = sun8i_dwmac_set_syscon(priv); 9689f93ac8dSLABBE Corentin if (ret) 9699f93ac8dSLABBE Corentin return NULL; 9709f93ac8dSLABBE Corentin 9719f93ac8dSLABBE Corentin mac->pcsr = priv->ioaddr; 9729f93ac8dSLABBE Corentin mac->mac = &sun8i_dwmac_ops; 9739f93ac8dSLABBE Corentin mac->dma = &sun8i_dwmac_dma_ops; 9749f93ac8dSLABBE Corentin 9759f93ac8dSLABBE Corentin /* The loopback bit seems to be re-set when link change 9769f93ac8dSLABBE Corentin * Simply mask it each time 9779f93ac8dSLABBE Corentin * Speed 10/100/1000 are set in BIT(2)/BIT(3) 9789f93ac8dSLABBE Corentin */ 9799f93ac8dSLABBE Corentin mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 9809f93ac8dSLABBE Corentin mac->link.speed10 = EMAC_SPEED_10; 9819f93ac8dSLABBE Corentin mac->link.speed100 = EMAC_SPEED_100; 9829f93ac8dSLABBE Corentin mac->link.speed1000 = EMAC_SPEED_1000; 9839f93ac8dSLABBE Corentin mac->link.duplex = EMAC_DUPLEX_FULL; 9849f93ac8dSLABBE Corentin mac->mii.addr = EMAC_MDIO_CMD; 9859f93ac8dSLABBE Corentin mac->mii.data = EMAC_MDIO_DATA; 9869f93ac8dSLABBE Corentin mac->mii.reg_shift = 4; 9879f93ac8dSLABBE Corentin mac->mii.reg_mask = GENMASK(8, 4); 9889f93ac8dSLABBE Corentin mac->mii.addr_shift = 12; 9899f93ac8dSLABBE Corentin mac->mii.addr_mask = GENMASK(16, 12); 9909f93ac8dSLABBE Corentin mac->mii.clk_csr_shift = 20; 9919f93ac8dSLABBE Corentin mac->mii.clk_csr_mask = GENMASK(22, 20); 9929f93ac8dSLABBE Corentin mac->unicast_filter_entries = 8; 9939f93ac8dSLABBE Corentin 9949f93ac8dSLABBE Corentin /* Synopsys Id is not available */ 9959f93ac8dSLABBE Corentin priv->synopsys_id = 0; 9969f93ac8dSLABBE Corentin 9979f93ac8dSLABBE Corentin return mac; 9989f93ac8dSLABBE Corentin } 9999f93ac8dSLABBE Corentin 100049a06caeSChen-Yu Tsai static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 100149a06caeSChen-Yu Tsai { 100249a06caeSChen-Yu Tsai struct device_node *syscon_node; 100349a06caeSChen-Yu Tsai struct platform_device *syscon_pdev; 100449a06caeSChen-Yu Tsai struct regmap *regmap = NULL; 100549a06caeSChen-Yu Tsai 100649a06caeSChen-Yu Tsai syscon_node = of_parse_phandle(node, "syscon", 0); 100749a06caeSChen-Yu Tsai if (!syscon_node) 100849a06caeSChen-Yu Tsai return ERR_PTR(-ENODEV); 100949a06caeSChen-Yu Tsai 101049a06caeSChen-Yu Tsai syscon_pdev = of_find_device_by_node(syscon_node); 101149a06caeSChen-Yu Tsai if (!syscon_pdev) { 101249a06caeSChen-Yu Tsai /* platform device might not be probed yet */ 101349a06caeSChen-Yu Tsai regmap = ERR_PTR(-EPROBE_DEFER); 101449a06caeSChen-Yu Tsai goto out_put_node; 101549a06caeSChen-Yu Tsai } 101649a06caeSChen-Yu Tsai 101749a06caeSChen-Yu Tsai /* If no regmap is found then the other device driver is at fault */ 101849a06caeSChen-Yu Tsai regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 101949a06caeSChen-Yu Tsai if (!regmap) 102049a06caeSChen-Yu Tsai regmap = ERR_PTR(-EINVAL); 102149a06caeSChen-Yu Tsai 102249a06caeSChen-Yu Tsai platform_device_put(syscon_pdev); 102349a06caeSChen-Yu Tsai out_put_node: 102449a06caeSChen-Yu Tsai of_node_put(syscon_node); 102549a06caeSChen-Yu Tsai return regmap; 102649a06caeSChen-Yu Tsai } 102749a06caeSChen-Yu Tsai 10289f93ac8dSLABBE Corentin static int sun8i_dwmac_probe(struct platform_device *pdev) 10299f93ac8dSLABBE Corentin { 10309f93ac8dSLABBE Corentin struct plat_stmmacenet_data *plat_dat; 10319f93ac8dSLABBE Corentin struct stmmac_resources stmmac_res; 10329f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac; 10339f93ac8dSLABBE Corentin struct device *dev = &pdev->dev; 10349f93ac8dSLABBE Corentin int ret; 1035634db83bSCorentin Labbe struct stmmac_priv *priv; 1036634db83bSCorentin Labbe struct net_device *ndev; 103725ae15fbSChen-Yu Tsai struct regmap *regmap; 10389f93ac8dSLABBE Corentin 10399f93ac8dSLABBE Corentin ret = stmmac_get_platform_resources(pdev, &stmmac_res); 10409f93ac8dSLABBE Corentin if (ret) 10419f93ac8dSLABBE Corentin return ret; 10429f93ac8dSLABBE Corentin 10439f93ac8dSLABBE Corentin plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 10449f93ac8dSLABBE Corentin if (IS_ERR(plat_dat)) 10459f93ac8dSLABBE Corentin return PTR_ERR(plat_dat); 10469f93ac8dSLABBE Corentin 10479f93ac8dSLABBE Corentin gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 10489f93ac8dSLABBE Corentin if (!gmac) 10499f93ac8dSLABBE Corentin return -ENOMEM; 10509f93ac8dSLABBE Corentin 10519f93ac8dSLABBE Corentin gmac->variant = of_device_get_match_data(&pdev->dev); 10529f93ac8dSLABBE Corentin if (!gmac->variant) { 10539f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 10549f93ac8dSLABBE Corentin return -EINVAL; 10559f93ac8dSLABBE Corentin } 10569f93ac8dSLABBE Corentin 10579f93ac8dSLABBE Corentin gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); 10589f93ac8dSLABBE Corentin if (IS_ERR(gmac->tx_clk)) { 10599f93ac8dSLABBE Corentin dev_err(dev, "Could not get TX clock\n"); 10609f93ac8dSLABBE Corentin return PTR_ERR(gmac->tx_clk); 10619f93ac8dSLABBE Corentin } 10629f93ac8dSLABBE Corentin 10639f93ac8dSLABBE Corentin /* Optional regulator for PHY */ 10649f93ac8dSLABBE Corentin gmac->regulator = devm_regulator_get_optional(dev, "phy"); 10659f93ac8dSLABBE Corentin if (IS_ERR(gmac->regulator)) { 10669f93ac8dSLABBE Corentin if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 10679f93ac8dSLABBE Corentin return -EPROBE_DEFER; 10689f93ac8dSLABBE Corentin dev_info(dev, "No regulator found\n"); 10699f93ac8dSLABBE Corentin gmac->regulator = NULL; 10709f93ac8dSLABBE Corentin } 10719f93ac8dSLABBE Corentin 107249a06caeSChen-Yu Tsai /* The "GMAC clock control" register might be located in the 107349a06caeSChen-Yu Tsai * CCU address range (on the R40), or the system control address 107449a06caeSChen-Yu Tsai * range (on most other sun8i and later SoCs). 107549a06caeSChen-Yu Tsai * 107649a06caeSChen-Yu Tsai * The former controls most if not all clocks in the SoC. The 107749a06caeSChen-Yu Tsai * latter has an SoC identification register, and on some SoCs, 107849a06caeSChen-Yu Tsai * controls to map device specific SRAM to either the intended 107949a06caeSChen-Yu Tsai * peripheral, or the CPU address space. 108049a06caeSChen-Yu Tsai * 108149a06caeSChen-Yu Tsai * In either case, there should be a coordinated and restricted 108249a06caeSChen-Yu Tsai * method of accessing the register needed here. This is done by 108349a06caeSChen-Yu Tsai * having the device export a custom regmap, instead of a generic 108449a06caeSChen-Yu Tsai * syscon, which grants all access to all registers. 108549a06caeSChen-Yu Tsai * 108649a06caeSChen-Yu Tsai * To support old device trees, we fall back to using the syscon 108749a06caeSChen-Yu Tsai * interface if possible. 108849a06caeSChen-Yu Tsai */ 108949a06caeSChen-Yu Tsai regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 109049a06caeSChen-Yu Tsai if (IS_ERR(regmap)) 109149a06caeSChen-Yu Tsai regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 109249a06caeSChen-Yu Tsai "syscon"); 109325ae15fbSChen-Yu Tsai if (IS_ERR(regmap)) { 109425ae15fbSChen-Yu Tsai ret = PTR_ERR(regmap); 10959f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 10969f93ac8dSLABBE Corentin return ret; 10979f93ac8dSLABBE Corentin } 10989f93ac8dSLABBE Corentin 109925ae15fbSChen-Yu Tsai gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 110025ae15fbSChen-Yu Tsai *gmac->variant->syscon_field); 110125ae15fbSChen-Yu Tsai if (IS_ERR(gmac->regmap_field)) { 110225ae15fbSChen-Yu Tsai ret = PTR_ERR(gmac->regmap_field); 110325ae15fbSChen-Yu Tsai dev_err(dev, "Unable to map syscon register: %d\n", ret); 110425ae15fbSChen-Yu Tsai return ret; 110525ae15fbSChen-Yu Tsai } 110625ae15fbSChen-Yu Tsai 11079f93ac8dSLABBE Corentin plat_dat->interface = of_get_phy_mode(dev->of_node); 11089f93ac8dSLABBE Corentin 11099f93ac8dSLABBE Corentin /* platform data specifying hardware features and callbacks. 11109f93ac8dSLABBE Corentin * hardware features were copied from Allwinner drivers. 11119f93ac8dSLABBE Corentin */ 11129f93ac8dSLABBE Corentin plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 11139f93ac8dSLABBE Corentin plat_dat->tx_coe = 1; 11149f93ac8dSLABBE Corentin plat_dat->has_sun8i = true; 11159f93ac8dSLABBE Corentin plat_dat->bsp_priv = gmac; 11169f93ac8dSLABBE Corentin plat_dat->init = sun8i_dwmac_init; 11179f93ac8dSLABBE Corentin plat_dat->exit = sun8i_dwmac_exit; 11189f93ac8dSLABBE Corentin plat_dat->setup = sun8i_dwmac_setup; 11199f93ac8dSLABBE Corentin 11209f93ac8dSLABBE Corentin ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 11219f93ac8dSLABBE Corentin if (ret) 11229f93ac8dSLABBE Corentin return ret; 11239f93ac8dSLABBE Corentin 11249f93ac8dSLABBE Corentin ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 11259f93ac8dSLABBE Corentin if (ret) 1126634db83bSCorentin Labbe goto dwmac_exit; 11279f93ac8dSLABBE Corentin 1128634db83bSCorentin Labbe ndev = dev_get_drvdata(&pdev->dev); 1129634db83bSCorentin Labbe priv = netdev_priv(ndev); 1130634db83bSCorentin Labbe /* The mux must be registered after parent MDIO 1131634db83bSCorentin Labbe * so after stmmac_dvr_probe() 1132634db83bSCorentin Labbe */ 1133634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 1134634db83bSCorentin Labbe ret = get_ephy_nodes(priv); 1135634db83bSCorentin Labbe if (ret) 1136634db83bSCorentin Labbe goto dwmac_exit; 1137634db83bSCorentin Labbe ret = sun8i_dwmac_register_mdio_mux(priv); 1138634db83bSCorentin Labbe if (ret) { 1139634db83bSCorentin Labbe dev_err(&pdev->dev, "Failed to register mux\n"); 1140634db83bSCorentin Labbe goto dwmac_mux; 1141634db83bSCorentin Labbe } 1142634db83bSCorentin Labbe } else { 1143634db83bSCorentin Labbe ret = sun8i_dwmac_reset(priv); 1144634db83bSCorentin Labbe if (ret) 1145634db83bSCorentin Labbe goto dwmac_exit; 1146634db83bSCorentin Labbe } 1147634db83bSCorentin Labbe 1148634db83bSCorentin Labbe return ret; 1149634db83bSCorentin Labbe dwmac_mux: 1150634db83bSCorentin Labbe sun8i_dwmac_unset_syscon(gmac); 1151634db83bSCorentin Labbe dwmac_exit: 1152634db83bSCorentin Labbe sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); 11539f93ac8dSLABBE Corentin return ret; 11549f93ac8dSLABBE Corentin } 11559f93ac8dSLABBE Corentin 11569f93ac8dSLABBE Corentin static const struct of_device_id sun8i_dwmac_match[] = { 1157a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-h3-emac", 1158a8ff8ccbSCorentin Labbe .data = &emac_variant_h3 }, 1159a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-v3s-emac", 1160a8ff8ccbSCorentin Labbe .data = &emac_variant_v3s }, 1161a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-a83t-emac", 1162a8ff8ccbSCorentin Labbe .data = &emac_variant_a83t }, 1163a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun50i-a64-emac", 1164a8ff8ccbSCorentin Labbe .data = &emac_variant_a64 }, 11659f93ac8dSLABBE Corentin { } 11669f93ac8dSLABBE Corentin }; 11679f93ac8dSLABBE Corentin MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 11689f93ac8dSLABBE Corentin 11699f93ac8dSLABBE Corentin static struct platform_driver sun8i_dwmac_driver = { 11709f93ac8dSLABBE Corentin .probe = sun8i_dwmac_probe, 11719f93ac8dSLABBE Corentin .remove = stmmac_pltfr_remove, 11729f93ac8dSLABBE Corentin .driver = { 11739f93ac8dSLABBE Corentin .name = "dwmac-sun8i", 11749f93ac8dSLABBE Corentin .pm = &stmmac_pltfr_pm_ops, 11759f93ac8dSLABBE Corentin .of_match_table = sun8i_dwmac_match, 11769f93ac8dSLABBE Corentin }, 11779f93ac8dSLABBE Corentin }; 11789f93ac8dSLABBE Corentin module_platform_driver(sun8i_dwmac_driver); 11799f93ac8dSLABBE Corentin 11809f93ac8dSLABBE Corentin MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 11819f93ac8dSLABBE Corentin MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 11829f93ac8dSLABBE Corentin MODULE_LICENSE("GPL"); 1183