1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 29f93ac8dSLABBE Corentin /* 39f93ac8dSLABBE Corentin * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer 49f93ac8dSLABBE Corentin * 59f93ac8dSLABBE Corentin * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> 69f93ac8dSLABBE Corentin */ 79f93ac8dSLABBE Corentin 89f93ac8dSLABBE Corentin #include <linux/clk.h> 99f93ac8dSLABBE Corentin #include <linux/io.h> 109f93ac8dSLABBE Corentin #include <linux/iopoll.h> 11634db83bSCorentin Labbe #include <linux/mdio-mux.h> 129f93ac8dSLABBE Corentin #include <linux/mfd/syscon.h> 139f93ac8dSLABBE Corentin #include <linux/module.h> 149f93ac8dSLABBE Corentin #include <linux/of_device.h> 159f93ac8dSLABBE Corentin #include <linux/of_mdio.h> 169f93ac8dSLABBE Corentin #include <linux/of_net.h> 179f93ac8dSLABBE Corentin #include <linux/phy.h> 189f93ac8dSLABBE Corentin #include <linux/platform_device.h> 19b76bbb34SJisheng Zhang #include <linux/pm_runtime.h> 209f93ac8dSLABBE Corentin #include <linux/regulator/consumer.h> 219f93ac8dSLABBE Corentin #include <linux/regmap.h> 229f93ac8dSLABBE Corentin #include <linux/stmmac.h> 239f93ac8dSLABBE Corentin 249f93ac8dSLABBE Corentin #include "stmmac.h" 259f93ac8dSLABBE Corentin #include "stmmac_platform.h" 269f93ac8dSLABBE Corentin 279f93ac8dSLABBE Corentin /* General notes on dwmac-sun8i: 289f93ac8dSLABBE Corentin * Locking: no locking is necessary in this file because all necessary locking 299f93ac8dSLABBE Corentin * is done in the "stmmac files" 309f93ac8dSLABBE Corentin */ 319f93ac8dSLABBE Corentin 3256c266dcSCorentin Labbe /* struct emac_variant - Describe dwmac-sun8i hardware variant 339f93ac8dSLABBE Corentin * @default_syscon_value: The default value of the EMAC register in syscon 349f93ac8dSLABBE Corentin * This value is used for disabling properly EMAC 359f93ac8dSLABBE Corentin * and used as a good starting value in case of the 369f93ac8dSLABBE Corentin * boot process(uboot) leave some stuff. 3725ae15fbSChen-Yu Tsai * @syscon_field reg_field for the syscon's gmac register 38634db83bSCorentin Labbe * @soc_has_internal_phy: Does the MAC embed an internal PHY 399f93ac8dSLABBE Corentin * @support_mii: Does the MAC handle MII 409f93ac8dSLABBE Corentin * @support_rmii: Does the MAC handle RMII 419f93ac8dSLABBE Corentin * @support_rgmii: Does the MAC handle RGMII 427b270b72SChen-Yu Tsai * 437b270b72SChen-Yu Tsai * @rx_delay_max: Maximum raw value for RX delay chain 447b270b72SChen-Yu Tsai * @tx_delay_max: Maximum raw value for TX delay chain 457b270b72SChen-Yu Tsai * These two also indicate the bitmask for 467b270b72SChen-Yu Tsai * the RX and TX delay chain registers. A 477b270b72SChen-Yu Tsai * value of zero indicates this is not supported. 489f93ac8dSLABBE Corentin */ 499f93ac8dSLABBE Corentin struct emac_variant { 509f93ac8dSLABBE Corentin u32 default_syscon_value; 5125ae15fbSChen-Yu Tsai const struct reg_field *syscon_field; 52634db83bSCorentin Labbe bool soc_has_internal_phy; 539f93ac8dSLABBE Corentin bool support_mii; 549f93ac8dSLABBE Corentin bool support_rmii; 559f93ac8dSLABBE Corentin bool support_rgmii; 567b270b72SChen-Yu Tsai u8 rx_delay_max; 577b270b72SChen-Yu Tsai u8 tx_delay_max; 589f93ac8dSLABBE Corentin }; 599f93ac8dSLABBE Corentin 609f93ac8dSLABBE Corentin /* struct sunxi_priv_data - hold all sunxi private data 619f93ac8dSLABBE Corentin * @ephy_clk: reference to the optional EPHY clock for the internal PHY 629f93ac8dSLABBE Corentin * @regulator: reference to the optional regulator 639f93ac8dSLABBE Corentin * @rst_ephy: reference to the optional EPHY reset for the internal PHY 649f93ac8dSLABBE Corentin * @variant: reference to the current board variant 659f93ac8dSLABBE Corentin * @regmap: regmap for using the syscon 66634db83bSCorentin Labbe * @internal_phy_powered: Does the internal PHY is enabled 67b8239638SSamuel Holland * @use_internal_phy: Is the internal PHY selected for use 68634db83bSCorentin Labbe * @mux_handle: Internal pointer used by mdio-mux lib 699f93ac8dSLABBE Corentin */ 709f93ac8dSLABBE Corentin struct sunxi_priv_data { 719f93ac8dSLABBE Corentin struct clk *ephy_clk; 729f93ac8dSLABBE Corentin struct regulator *regulator; 739f93ac8dSLABBE Corentin struct reset_control *rst_ephy; 749f93ac8dSLABBE Corentin const struct emac_variant *variant; 7525ae15fbSChen-Yu Tsai struct regmap_field *regmap_field; 76634db83bSCorentin Labbe bool internal_phy_powered; 77b8239638SSamuel Holland bool use_internal_phy; 78634db83bSCorentin Labbe void *mux_handle; 799f93ac8dSLABBE Corentin }; 809f93ac8dSLABBE Corentin 8125ae15fbSChen-Yu Tsai /* EMAC clock register @ 0x30 in the "system control" address range */ 8225ae15fbSChen-Yu Tsai static const struct reg_field sun8i_syscon_reg_field = { 8325ae15fbSChen-Yu Tsai .reg = 0x30, 8425ae15fbSChen-Yu Tsai .lsb = 0, 8525ae15fbSChen-Yu Tsai .msb = 31, 8625ae15fbSChen-Yu Tsai }; 8725ae15fbSChen-Yu Tsai 889bf5085aSChen-Yu Tsai /* EMAC clock register @ 0x164 in the CCU address range */ 899bf5085aSChen-Yu Tsai static const struct reg_field sun8i_ccu_reg_field = { 909bf5085aSChen-Yu Tsai .reg = 0x164, 919bf5085aSChen-Yu Tsai .lsb = 0, 929bf5085aSChen-Yu Tsai .msb = 31, 939bf5085aSChen-Yu Tsai }; 949bf5085aSChen-Yu Tsai 959f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_h3 = { 969f93ac8dSLABBE Corentin .default_syscon_value = 0x58000, 9725ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 98634db83bSCorentin Labbe .soc_has_internal_phy = true, 999f93ac8dSLABBE Corentin .support_mii = true, 1009f93ac8dSLABBE Corentin .support_rmii = true, 1017b270b72SChen-Yu Tsai .support_rgmii = true, 1027b270b72SChen-Yu Tsai .rx_delay_max = 31, 1037b270b72SChen-Yu Tsai .tx_delay_max = 7, 1049f93ac8dSLABBE Corentin }; 1059f93ac8dSLABBE Corentin 10657fde47dSIcenowy Zheng static const struct emac_variant emac_variant_v3s = { 10757fde47dSIcenowy Zheng .default_syscon_value = 0x38000, 10825ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 109634db83bSCorentin Labbe .soc_has_internal_phy = true, 11057fde47dSIcenowy Zheng .support_mii = true 11157fde47dSIcenowy Zheng }; 11257fde47dSIcenowy Zheng 1139f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_a83t = { 1149f93ac8dSLABBE Corentin .default_syscon_value = 0, 11525ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 116634db83bSCorentin Labbe .soc_has_internal_phy = false, 1179f93ac8dSLABBE Corentin .support_mii = true, 1187b270b72SChen-Yu Tsai .support_rgmii = true, 1197b270b72SChen-Yu Tsai .rx_delay_max = 31, 1207b270b72SChen-Yu Tsai .tx_delay_max = 7, 1219f93ac8dSLABBE Corentin }; 1229f93ac8dSLABBE Corentin 1239bf5085aSChen-Yu Tsai static const struct emac_variant emac_variant_r40 = { 1249bf5085aSChen-Yu Tsai .default_syscon_value = 0, 1259bf5085aSChen-Yu Tsai .syscon_field = &sun8i_ccu_reg_field, 1269bf5085aSChen-Yu Tsai .support_mii = true, 1279bf5085aSChen-Yu Tsai .support_rgmii = true, 1289bf5085aSChen-Yu Tsai .rx_delay_max = 7, 1299bf5085aSChen-Yu Tsai }; 1309bf5085aSChen-Yu Tsai 1319f93ac8dSLABBE Corentin static const struct emac_variant emac_variant_a64 = { 1329f93ac8dSLABBE Corentin .default_syscon_value = 0, 13325ae15fbSChen-Yu Tsai .syscon_field = &sun8i_syscon_reg_field, 134634db83bSCorentin Labbe .soc_has_internal_phy = false, 1359f93ac8dSLABBE Corentin .support_mii = true, 1369f93ac8dSLABBE Corentin .support_rmii = true, 1377b270b72SChen-Yu Tsai .support_rgmii = true, 1387b270b72SChen-Yu Tsai .rx_delay_max = 31, 1397b270b72SChen-Yu Tsai .tx_delay_max = 7, 1409f93ac8dSLABBE Corentin }; 1419f93ac8dSLABBE Corentin 142adadd38cSIcenowy Zheng static const struct emac_variant emac_variant_h6 = { 143adadd38cSIcenowy Zheng .default_syscon_value = 0x50000, 144adadd38cSIcenowy Zheng .syscon_field = &sun8i_syscon_reg_field, 145adadd38cSIcenowy Zheng /* The "Internal PHY" of H6 is not on the die. It's on the 146adadd38cSIcenowy Zheng * co-packaged AC200 chip instead. 147adadd38cSIcenowy Zheng */ 148adadd38cSIcenowy Zheng .soc_has_internal_phy = false, 149adadd38cSIcenowy Zheng .support_mii = true, 150adadd38cSIcenowy Zheng .support_rmii = true, 151adadd38cSIcenowy Zheng .support_rgmii = true, 152adadd38cSIcenowy Zheng .rx_delay_max = 31, 153adadd38cSIcenowy Zheng .tx_delay_max = 7, 154adadd38cSIcenowy Zheng }; 155adadd38cSIcenowy Zheng 1569f93ac8dSLABBE Corentin #define EMAC_BASIC_CTL0 0x00 1579f93ac8dSLABBE Corentin #define EMAC_BASIC_CTL1 0x04 1589f93ac8dSLABBE Corentin #define EMAC_INT_STA 0x08 1599f93ac8dSLABBE Corentin #define EMAC_INT_EN 0x0C 1609f93ac8dSLABBE Corentin #define EMAC_TX_CTL0 0x10 1619f93ac8dSLABBE Corentin #define EMAC_TX_CTL1 0x14 1629f93ac8dSLABBE Corentin #define EMAC_TX_FLOW_CTL 0x1C 1639f93ac8dSLABBE Corentin #define EMAC_TX_DESC_LIST 0x20 1649f93ac8dSLABBE Corentin #define EMAC_RX_CTL0 0x24 1659f93ac8dSLABBE Corentin #define EMAC_RX_CTL1 0x28 1669f93ac8dSLABBE Corentin #define EMAC_RX_DESC_LIST 0x34 1679f93ac8dSLABBE Corentin #define EMAC_RX_FRM_FLT 0x38 1689f93ac8dSLABBE Corentin #define EMAC_MDIO_CMD 0x48 1699f93ac8dSLABBE Corentin #define EMAC_MDIO_DATA 0x4C 1709f93ac8dSLABBE Corentin #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) 1719f93ac8dSLABBE Corentin #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) 1729f93ac8dSLABBE Corentin #define EMAC_TX_DMA_STA 0xB0 1739f93ac8dSLABBE Corentin #define EMAC_TX_CUR_DESC 0xB4 1749f93ac8dSLABBE Corentin #define EMAC_TX_CUR_BUF 0xB8 1759f93ac8dSLABBE Corentin #define EMAC_RX_DMA_STA 0xC0 1769f93ac8dSLABBE Corentin #define EMAC_RX_CUR_DESC 0xC4 1779f93ac8dSLABBE Corentin #define EMAC_RX_CUR_BUF 0xC8 1789f93ac8dSLABBE Corentin 1799f93ac8dSLABBE Corentin /* Use in EMAC_BASIC_CTL0 */ 1809f93ac8dSLABBE Corentin #define EMAC_DUPLEX_FULL BIT(0) 1819f93ac8dSLABBE Corentin #define EMAC_LOOPBACK BIT(1) 1829f93ac8dSLABBE Corentin #define EMAC_SPEED_1000 0 1839f93ac8dSLABBE Corentin #define EMAC_SPEED_100 (0x03 << 2) 1849f93ac8dSLABBE Corentin #define EMAC_SPEED_10 (0x02 << 2) 1859f93ac8dSLABBE Corentin 1869f93ac8dSLABBE Corentin /* Use in EMAC_BASIC_CTL1 */ 1879f93ac8dSLABBE Corentin #define EMAC_BURSTLEN_SHIFT 24 1889f93ac8dSLABBE Corentin 1899f93ac8dSLABBE Corentin /* Used in EMAC_RX_FRM_FLT */ 1909f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_RXALL BIT(0) 1919f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_CTL BIT(13) 1929f93ac8dSLABBE Corentin #define EMAC_FRM_FLT_MULTICAST BIT(16) 1939f93ac8dSLABBE Corentin 1949f93ac8dSLABBE Corentin /* Used in RX_CTL1*/ 1959f93ac8dSLABBE Corentin #define EMAC_RX_MD BIT(1) 196aa4c0c90SJoe Perches #define EMAC_RX_TH_MASK GENMASK(5, 4) 1979f93ac8dSLABBE Corentin #define EMAC_RX_TH_32 0 1989f93ac8dSLABBE Corentin #define EMAC_RX_TH_64 (0x1 << 4) 1999f93ac8dSLABBE Corentin #define EMAC_RX_TH_96 (0x2 << 4) 2009f93ac8dSLABBE Corentin #define EMAC_RX_TH_128 (0x3 << 4) 2019f93ac8dSLABBE Corentin #define EMAC_RX_DMA_EN BIT(30) 2029f93ac8dSLABBE Corentin #define EMAC_RX_DMA_START BIT(31) 2039f93ac8dSLABBE Corentin 2049f93ac8dSLABBE Corentin /* Used in TX_CTL1*/ 2059f93ac8dSLABBE Corentin #define EMAC_TX_MD BIT(1) 2069f93ac8dSLABBE Corentin #define EMAC_TX_NEXT_FRM BIT(2) 207aa4c0c90SJoe Perches #define EMAC_TX_TH_MASK GENMASK(10, 8) 2089f93ac8dSLABBE Corentin #define EMAC_TX_TH_64 0 2099f93ac8dSLABBE Corentin #define EMAC_TX_TH_128 (0x1 << 8) 2109f93ac8dSLABBE Corentin #define EMAC_TX_TH_192 (0x2 << 8) 2119f93ac8dSLABBE Corentin #define EMAC_TX_TH_256 (0x3 << 8) 2129f93ac8dSLABBE Corentin #define EMAC_TX_DMA_EN BIT(30) 2139f93ac8dSLABBE Corentin #define EMAC_TX_DMA_START BIT(31) 2149f93ac8dSLABBE Corentin 2159f93ac8dSLABBE Corentin /* Used in RX_CTL0 */ 2169f93ac8dSLABBE Corentin #define EMAC_RX_RECEIVER_EN BIT(31) 2179f93ac8dSLABBE Corentin #define EMAC_RX_DO_CRC BIT(27) 2189f93ac8dSLABBE Corentin #define EMAC_RX_FLOW_CTL_EN BIT(16) 2199f93ac8dSLABBE Corentin 2209f93ac8dSLABBE Corentin /* Used in TX_CTL0 */ 2219f93ac8dSLABBE Corentin #define EMAC_TX_TRANSMITTER_EN BIT(31) 2229f93ac8dSLABBE Corentin 2239f93ac8dSLABBE Corentin /* Used in EMAC_TX_FLOW_CTL */ 2249f93ac8dSLABBE Corentin #define EMAC_TX_FLOW_CTL_EN BIT(0) 2259f93ac8dSLABBE Corentin 2269f93ac8dSLABBE Corentin /* Used in EMAC_INT_STA */ 2279f93ac8dSLABBE Corentin #define EMAC_TX_INT BIT(0) 2289f93ac8dSLABBE Corentin #define EMAC_TX_DMA_STOP_INT BIT(1) 2299f93ac8dSLABBE Corentin #define EMAC_TX_BUF_UA_INT BIT(2) 2309f93ac8dSLABBE Corentin #define EMAC_TX_TIMEOUT_INT BIT(3) 2319f93ac8dSLABBE Corentin #define EMAC_TX_UNDERFLOW_INT BIT(4) 2329f93ac8dSLABBE Corentin #define EMAC_TX_EARLY_INT BIT(5) 2339f93ac8dSLABBE Corentin #define EMAC_RX_INT BIT(8) 2349f93ac8dSLABBE Corentin #define EMAC_RX_BUF_UA_INT BIT(9) 2359f93ac8dSLABBE Corentin #define EMAC_RX_DMA_STOP_INT BIT(10) 2369f93ac8dSLABBE Corentin #define EMAC_RX_TIMEOUT_INT BIT(11) 2379f93ac8dSLABBE Corentin #define EMAC_RX_OVERFLOW_INT BIT(12) 2389f93ac8dSLABBE Corentin #define EMAC_RX_EARLY_INT BIT(13) 2399f93ac8dSLABBE Corentin #define EMAC_RGMII_STA_INT BIT(16) 2409f93ac8dSLABBE Corentin 2417e1c520cSOng Boon Leong #define EMAC_INT_MSK_COMMON EMAC_RGMII_STA_INT 2427e1c520cSOng Boon Leong #define EMAC_INT_MSK_TX (EMAC_TX_INT | \ 2437e1c520cSOng Boon Leong EMAC_TX_DMA_STOP_INT | \ 2447e1c520cSOng Boon Leong EMAC_TX_BUF_UA_INT | \ 2457e1c520cSOng Boon Leong EMAC_TX_TIMEOUT_INT | \ 2467e1c520cSOng Boon Leong EMAC_TX_UNDERFLOW_INT | \ 2477e1c520cSOng Boon Leong EMAC_TX_EARLY_INT |\ 2487e1c520cSOng Boon Leong EMAC_INT_MSK_COMMON) 2497e1c520cSOng Boon Leong #define EMAC_INT_MSK_RX (EMAC_RX_INT | \ 2507e1c520cSOng Boon Leong EMAC_RX_BUF_UA_INT | \ 2517e1c520cSOng Boon Leong EMAC_RX_DMA_STOP_INT | \ 2527e1c520cSOng Boon Leong EMAC_RX_TIMEOUT_INT | \ 2537e1c520cSOng Boon Leong EMAC_RX_OVERFLOW_INT | \ 2547e1c520cSOng Boon Leong EMAC_RX_EARLY_INT | \ 2557e1c520cSOng Boon Leong EMAC_INT_MSK_COMMON) 2567e1c520cSOng Boon Leong 2579f93ac8dSLABBE Corentin #define MAC_ADDR_TYPE_DST BIT(31) 2589f93ac8dSLABBE Corentin 2599f93ac8dSLABBE Corentin /* H3 specific bits for EPHY */ 2609f93ac8dSLABBE Corentin #define H3_EPHY_ADDR_SHIFT 20 2611450ba8aSIcenowy Zheng #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 2629f93ac8dSLABBE Corentin #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 2639f93ac8dSLABBE Corentin #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 2649f93ac8dSLABBE Corentin #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 265634db83bSCorentin Labbe #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) 266634db83bSCorentin Labbe #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 267634db83bSCorentin Labbe #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 2689f93ac8dSLABBE Corentin 2699f93ac8dSLABBE Corentin /* H3/A64 specific bits */ 2709f93ac8dSLABBE Corentin #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ 2719f93ac8dSLABBE Corentin 2729f93ac8dSLABBE Corentin /* Generic system control EMAC_CLK bits */ 2739f93ac8dSLABBE Corentin #define SYSCON_ETXDC_SHIFT 10 2749f93ac8dSLABBE Corentin #define SYSCON_ERXDC_SHIFT 5 2759f93ac8dSLABBE Corentin /* EMAC PHY Interface Type */ 2769f93ac8dSLABBE Corentin #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ 2779f93ac8dSLABBE Corentin #define SYSCON_ETCS_MASK GENMASK(1, 0) 2789f93ac8dSLABBE Corentin #define SYSCON_ETCS_MII 0x0 2799f93ac8dSLABBE Corentin #define SYSCON_ETCS_EXT_GMII 0x1 2809f93ac8dSLABBE Corentin #define SYSCON_ETCS_INT_GMII 0x2 2819f93ac8dSLABBE Corentin 2829f93ac8dSLABBE Corentin /* sun8i_dwmac_dma_reset() - reset the EMAC 2839f93ac8dSLABBE Corentin * Called from stmmac via stmmac_dma_ops->reset 2849f93ac8dSLABBE Corentin */ 2859f93ac8dSLABBE Corentin static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 2869f93ac8dSLABBE Corentin { 2879f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_CTL1); 2889f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_TX_CTL1); 2899f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_FRM_FLT); 2909f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_RX_DESC_LIST); 2919f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_TX_DESC_LIST); 2929f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_INT_EN); 2939f93ac8dSLABBE Corentin writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 2949f93ac8dSLABBE Corentin return 0; 2959f93ac8dSLABBE Corentin } 2969f93ac8dSLABBE Corentin 2979f93ac8dSLABBE Corentin /* sun8i_dwmac_dma_init() - initialize the EMAC 2989f93ac8dSLABBE Corentin * Called from stmmac via stmmac_dma_ops->init 2999f93ac8dSLABBE Corentin */ 3009f93ac8dSLABBE Corentin static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 30124aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 3029f93ac8dSLABBE Corentin { 3039f93ac8dSLABBE Corentin writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); 3049f93ac8dSLABBE Corentin writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); 3059f93ac8dSLABBE Corentin } 3069f93ac8dSLABBE Corentin 3071d84b487SAndrew Halaney static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv, 3081d84b487SAndrew Halaney void __iomem *ioaddr, 30924aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, 31006a80a7dSJose Abreu dma_addr_t dma_rx_phy, u32 chan) 31124aaed0cSJose Abreu { 31224aaed0cSJose Abreu /* Write RX descriptors address */ 31306a80a7dSJose Abreu writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST); 31424aaed0cSJose Abreu } 31524aaed0cSJose Abreu 3161d84b487SAndrew Halaney static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv, 3171d84b487SAndrew Halaney void __iomem *ioaddr, 31824aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, 31906a80a7dSJose Abreu dma_addr_t dma_tx_phy, u32 chan) 32024aaed0cSJose Abreu { 32124aaed0cSJose Abreu /* Write TX descriptors address */ 32206a80a7dSJose Abreu writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST); 32324aaed0cSJose Abreu } 32424aaed0cSJose Abreu 3259f93ac8dSLABBE Corentin /* sun8i_dwmac_dump_regs() - Dump EMAC address space 3269f93ac8dSLABBE Corentin * Called from stmmac_dma_ops->dump_regs 3279f93ac8dSLABBE Corentin * Used for ethtool 3289f93ac8dSLABBE Corentin */ 3291d84b487SAndrew Halaney static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv, 3301d84b487SAndrew Halaney void __iomem *ioaddr, u32 *reg_space) 3319f93ac8dSLABBE Corentin { 3329f93ac8dSLABBE Corentin int i; 3339f93ac8dSLABBE Corentin 3349f93ac8dSLABBE Corentin for (i = 0; i < 0xC8; i += 4) { 3359f93ac8dSLABBE Corentin if (i == 0x32 || i == 0x3C) 3369f93ac8dSLABBE Corentin continue; 3379f93ac8dSLABBE Corentin reg_space[i / 4] = readl(ioaddr + i); 3389f93ac8dSLABBE Corentin } 3399f93ac8dSLABBE Corentin } 3409f93ac8dSLABBE Corentin 3419f93ac8dSLABBE Corentin /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space 3429f93ac8dSLABBE Corentin * Called from stmmac_ops->dump_regs 3439f93ac8dSLABBE Corentin * Used for ethtool 3449f93ac8dSLABBE Corentin */ 3459f93ac8dSLABBE Corentin static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 3469f93ac8dSLABBE Corentin u32 *reg_space) 3479f93ac8dSLABBE Corentin { 3489f93ac8dSLABBE Corentin int i; 3499f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 3509f93ac8dSLABBE Corentin 3519f93ac8dSLABBE Corentin for (i = 0; i < 0xC8; i += 4) { 3529f93ac8dSLABBE Corentin if (i == 0x32 || i == 0x3C) 3539f93ac8dSLABBE Corentin continue; 3549f93ac8dSLABBE Corentin reg_space[i / 4] = readl(ioaddr + i); 3559f93ac8dSLABBE Corentin } 3569f93ac8dSLABBE Corentin } 3579f93ac8dSLABBE Corentin 3581d84b487SAndrew Halaney static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv, 3591d84b487SAndrew Halaney void __iomem *ioaddr, u32 chan, 360021bd5e3SJose Abreu bool rx, bool tx) 3619f93ac8dSLABBE Corentin { 362021bd5e3SJose Abreu u32 value = readl(ioaddr + EMAC_INT_EN); 363021bd5e3SJose Abreu 364021bd5e3SJose Abreu if (rx) 365021bd5e3SJose Abreu value |= EMAC_RX_INT; 366021bd5e3SJose Abreu if (tx) 367021bd5e3SJose Abreu value |= EMAC_TX_INT; 368021bd5e3SJose Abreu 369021bd5e3SJose Abreu writel(value, ioaddr + EMAC_INT_EN); 3709f93ac8dSLABBE Corentin } 3719f93ac8dSLABBE Corentin 3721d84b487SAndrew Halaney static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv, 3731d84b487SAndrew Halaney void __iomem *ioaddr, u32 chan, 374021bd5e3SJose Abreu bool rx, bool tx) 3759f93ac8dSLABBE Corentin { 376021bd5e3SJose Abreu u32 value = readl(ioaddr + EMAC_INT_EN); 377021bd5e3SJose Abreu 378021bd5e3SJose Abreu if (rx) 379021bd5e3SJose Abreu value &= ~EMAC_RX_INT; 380021bd5e3SJose Abreu if (tx) 381021bd5e3SJose Abreu value &= ~EMAC_TX_INT; 382021bd5e3SJose Abreu 383021bd5e3SJose Abreu writel(value, ioaddr + EMAC_INT_EN); 3849f93ac8dSLABBE Corentin } 3859f93ac8dSLABBE Corentin 3861d84b487SAndrew Halaney static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv, 3871d84b487SAndrew Halaney void __iomem *ioaddr, u32 chan) 3889f93ac8dSLABBE Corentin { 3899f93ac8dSLABBE Corentin u32 v; 3909f93ac8dSLABBE Corentin 3919f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 3929f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_START; 3939f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_EN; 3949f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 3959f93ac8dSLABBE Corentin } 3969f93ac8dSLABBE Corentin 3979f93ac8dSLABBE Corentin static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 3989f93ac8dSLABBE Corentin { 3999f93ac8dSLABBE Corentin u32 v; 4009f93ac8dSLABBE Corentin 4019f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 4029f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_START; 4039f93ac8dSLABBE Corentin v |= EMAC_TX_DMA_EN; 4049f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 4059f93ac8dSLABBE Corentin } 4069f93ac8dSLABBE Corentin 4071d84b487SAndrew Halaney static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv, 4081d84b487SAndrew Halaney void __iomem *ioaddr, u32 chan) 4099f93ac8dSLABBE Corentin { 4109f93ac8dSLABBE Corentin u32 v; 4119f93ac8dSLABBE Corentin 4129f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 4139f93ac8dSLABBE Corentin v &= ~EMAC_TX_DMA_EN; 4149f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 4159f93ac8dSLABBE Corentin } 4169f93ac8dSLABBE Corentin 4171d84b487SAndrew Halaney static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv, 4181d84b487SAndrew Halaney void __iomem *ioaddr, u32 chan) 4199f93ac8dSLABBE Corentin { 4209f93ac8dSLABBE Corentin u32 v; 4219f93ac8dSLABBE Corentin 4229f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 4239f93ac8dSLABBE Corentin v |= EMAC_RX_DMA_START; 4249f93ac8dSLABBE Corentin v |= EMAC_RX_DMA_EN; 4259f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 4269f93ac8dSLABBE Corentin } 4279f93ac8dSLABBE Corentin 4281d84b487SAndrew Halaney static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv, 4291d84b487SAndrew Halaney void __iomem *ioaddr, u32 chan) 4309f93ac8dSLABBE Corentin { 4319f93ac8dSLABBE Corentin u32 v; 4329f93ac8dSLABBE Corentin 4339f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL1); 4349f93ac8dSLABBE Corentin v &= ~EMAC_RX_DMA_EN; 4359f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL1); 4369f93ac8dSLABBE Corentin } 4379f93ac8dSLABBE Corentin 4381d84b487SAndrew Halaney static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv, 4391d84b487SAndrew Halaney void __iomem *ioaddr, 4407e1c520cSOng Boon Leong struct stmmac_extra_stats *x, u32 chan, 4417e1c520cSOng Boon Leong u32 dir) 4429f93ac8dSLABBE Corentin { 443*133466c3SJisheng Zhang struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 444*133466c3SJisheng Zhang struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 4459f93ac8dSLABBE Corentin int ret = 0; 446*133466c3SJisheng Zhang u32 v; 4479f93ac8dSLABBE Corentin 4489f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_INT_STA); 4499f93ac8dSLABBE Corentin 4507e1c520cSOng Boon Leong if (dir == DMA_DIR_RX) 4517e1c520cSOng Boon Leong v &= EMAC_INT_MSK_RX; 4527e1c520cSOng Boon Leong else if (dir == DMA_DIR_TX) 4537e1c520cSOng Boon Leong v &= EMAC_INT_MSK_TX; 4547e1c520cSOng Boon Leong 4559f93ac8dSLABBE Corentin if (v & EMAC_TX_INT) { 4569f93ac8dSLABBE Corentin ret |= handle_tx; 457*133466c3SJisheng Zhang u64_stats_update_begin(&tx_q->txq_stats.syncp); 458*133466c3SJisheng Zhang tx_q->txq_stats.tx_normal_irq_n++; 459*133466c3SJisheng Zhang u64_stats_update_end(&tx_q->txq_stats.syncp); 4609f93ac8dSLABBE Corentin } 4619f93ac8dSLABBE Corentin 4629f93ac8dSLABBE Corentin if (v & EMAC_TX_DMA_STOP_INT) 4639f93ac8dSLABBE Corentin x->tx_process_stopped_irq++; 4649f93ac8dSLABBE Corentin 4659f93ac8dSLABBE Corentin if (v & EMAC_TX_BUF_UA_INT) 4669f93ac8dSLABBE Corentin x->tx_process_stopped_irq++; 4679f93ac8dSLABBE Corentin 4689f93ac8dSLABBE Corentin if (v & EMAC_TX_TIMEOUT_INT) 4699f93ac8dSLABBE Corentin ret |= tx_hard_error; 4709f93ac8dSLABBE Corentin 4719f93ac8dSLABBE Corentin if (v & EMAC_TX_UNDERFLOW_INT) { 4729f93ac8dSLABBE Corentin ret |= tx_hard_error; 4739f93ac8dSLABBE Corentin x->tx_undeflow_irq++; 4749f93ac8dSLABBE Corentin } 4759f93ac8dSLABBE Corentin 4769f93ac8dSLABBE Corentin if (v & EMAC_TX_EARLY_INT) 4779f93ac8dSLABBE Corentin x->tx_early_irq++; 4789f93ac8dSLABBE Corentin 4799f93ac8dSLABBE Corentin if (v & EMAC_RX_INT) { 4809f93ac8dSLABBE Corentin ret |= handle_rx; 481*133466c3SJisheng Zhang u64_stats_update_begin(&rx_q->rxq_stats.syncp); 482*133466c3SJisheng Zhang rx_q->rxq_stats.rx_normal_irq_n++; 483*133466c3SJisheng Zhang u64_stats_update_end(&rx_q->rxq_stats.syncp); 4849f93ac8dSLABBE Corentin } 4859f93ac8dSLABBE Corentin 4869f93ac8dSLABBE Corentin if (v & EMAC_RX_BUF_UA_INT) 4879f93ac8dSLABBE Corentin x->rx_buf_unav_irq++; 4889f93ac8dSLABBE Corentin 4899f93ac8dSLABBE Corentin if (v & EMAC_RX_DMA_STOP_INT) 4909f93ac8dSLABBE Corentin x->rx_process_stopped_irq++; 4919f93ac8dSLABBE Corentin 4929f93ac8dSLABBE Corentin if (v & EMAC_RX_TIMEOUT_INT) 4939f93ac8dSLABBE Corentin ret |= tx_hard_error; 4949f93ac8dSLABBE Corentin 4959f93ac8dSLABBE Corentin if (v & EMAC_RX_OVERFLOW_INT) { 4969f93ac8dSLABBE Corentin ret |= tx_hard_error; 4979f93ac8dSLABBE Corentin x->rx_overflow_irq++; 4989f93ac8dSLABBE Corentin } 4999f93ac8dSLABBE Corentin 5009f93ac8dSLABBE Corentin if (v & EMAC_RX_EARLY_INT) 5019f93ac8dSLABBE Corentin x->rx_early_irq++; 5029f93ac8dSLABBE Corentin 5039f93ac8dSLABBE Corentin if (v & EMAC_RGMII_STA_INT) 5049f93ac8dSLABBE Corentin x->irq_rgmii_n++; 5059f93ac8dSLABBE Corentin 5069f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_INT_STA); 5079f93ac8dSLABBE Corentin 5089f93ac8dSLABBE Corentin return ret; 5099f93ac8dSLABBE Corentin } 5109f93ac8dSLABBE Corentin 5111d84b487SAndrew Halaney static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv, 5121d84b487SAndrew Halaney void __iomem *ioaddr, int mode, 513ab0204e3SJose Abreu u32 channel, int fifosz, u8 qmode) 514ab0204e3SJose Abreu { 515ab0204e3SJose Abreu u32 v; 516ab0204e3SJose Abreu 517ab0204e3SJose Abreu v = readl(ioaddr + EMAC_RX_CTL1); 518ab0204e3SJose Abreu if (mode == SF_DMA_MODE) { 519ab0204e3SJose Abreu v |= EMAC_RX_MD; 520ab0204e3SJose Abreu } else { 521ab0204e3SJose Abreu v &= ~EMAC_RX_MD; 522ab0204e3SJose Abreu v &= ~EMAC_RX_TH_MASK; 523ab0204e3SJose Abreu if (mode < 32) 524ab0204e3SJose Abreu v |= EMAC_RX_TH_32; 525ab0204e3SJose Abreu else if (mode < 64) 526ab0204e3SJose Abreu v |= EMAC_RX_TH_64; 527ab0204e3SJose Abreu else if (mode < 96) 528ab0204e3SJose Abreu v |= EMAC_RX_TH_96; 529ab0204e3SJose Abreu else if (mode < 128) 530ab0204e3SJose Abreu v |= EMAC_RX_TH_128; 531ab0204e3SJose Abreu } 532ab0204e3SJose Abreu writel(v, ioaddr + EMAC_RX_CTL1); 533ab0204e3SJose Abreu } 534ab0204e3SJose Abreu 5351d84b487SAndrew Halaney static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv, 5361d84b487SAndrew Halaney void __iomem *ioaddr, int mode, 537ab0204e3SJose Abreu u32 channel, int fifosz, u8 qmode) 5389f93ac8dSLABBE Corentin { 5399f93ac8dSLABBE Corentin u32 v; 5409f93ac8dSLABBE Corentin 5419f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_CTL1); 542ab0204e3SJose Abreu if (mode == SF_DMA_MODE) { 5439f93ac8dSLABBE Corentin v |= EMAC_TX_MD; 5449f93ac8dSLABBE Corentin /* Undocumented bit (called TX_NEXT_FRM in BSP), the original 5459f93ac8dSLABBE Corentin * comment is 5469f93ac8dSLABBE Corentin * "Operating on second frame increase the performance 5479f93ac8dSLABBE Corentin * especially when transmit store-and-forward is used." 5489f93ac8dSLABBE Corentin */ 5499f93ac8dSLABBE Corentin v |= EMAC_TX_NEXT_FRM; 5509f93ac8dSLABBE Corentin } else { 5519f93ac8dSLABBE Corentin v &= ~EMAC_TX_MD; 5529f93ac8dSLABBE Corentin v &= ~EMAC_TX_TH_MASK; 553ab0204e3SJose Abreu if (mode < 64) 5549f93ac8dSLABBE Corentin v |= EMAC_TX_TH_64; 555ab0204e3SJose Abreu else if (mode < 128) 5569f93ac8dSLABBE Corentin v |= EMAC_TX_TH_128; 557ab0204e3SJose Abreu else if (mode < 192) 5589f93ac8dSLABBE Corentin v |= EMAC_TX_TH_192; 559ab0204e3SJose Abreu else if (mode < 256) 5609f93ac8dSLABBE Corentin v |= EMAC_TX_TH_256; 5619f93ac8dSLABBE Corentin } 5629f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_CTL1); 5639f93ac8dSLABBE Corentin } 5649f93ac8dSLABBE Corentin 5659f93ac8dSLABBE Corentin static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { 5669f93ac8dSLABBE Corentin .reset = sun8i_dwmac_dma_reset, 5679f93ac8dSLABBE Corentin .init = sun8i_dwmac_dma_init, 56824aaed0cSJose Abreu .init_rx_chan = sun8i_dwmac_dma_init_rx, 56924aaed0cSJose Abreu .init_tx_chan = sun8i_dwmac_dma_init_tx, 5709f93ac8dSLABBE Corentin .dump_regs = sun8i_dwmac_dump_regs, 571ab0204e3SJose Abreu .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx, 572ab0204e3SJose Abreu .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx, 5739f93ac8dSLABBE Corentin .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, 5749f93ac8dSLABBE Corentin .enable_dma_irq = sun8i_dwmac_enable_dma_irq, 5759f93ac8dSLABBE Corentin .disable_dma_irq = sun8i_dwmac_disable_dma_irq, 5769f93ac8dSLABBE Corentin .start_tx = sun8i_dwmac_dma_start_tx, 5779f93ac8dSLABBE Corentin .stop_tx = sun8i_dwmac_dma_stop_tx, 5789f93ac8dSLABBE Corentin .start_rx = sun8i_dwmac_dma_start_rx, 5799f93ac8dSLABBE Corentin .stop_rx = sun8i_dwmac_dma_stop_rx, 5809f93ac8dSLABBE Corentin .dma_interrupt = sun8i_dwmac_dma_interrupt, 5819f93ac8dSLABBE Corentin }; 5829f93ac8dSLABBE Corentin 583b8239638SSamuel Holland static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); 584b8239638SSamuel Holland 5859f93ac8dSLABBE Corentin static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) 5869f93ac8dSLABBE Corentin { 587b8239638SSamuel Holland struct net_device *ndev = platform_get_drvdata(pdev); 5889f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv; 5899f93ac8dSLABBE Corentin int ret; 5909f93ac8dSLABBE Corentin 5919f93ac8dSLABBE Corentin if (gmac->regulator) { 5929f93ac8dSLABBE Corentin ret = regulator_enable(gmac->regulator); 5939f93ac8dSLABBE Corentin if (ret) { 5949f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Fail to enable regulator\n"); 5959f93ac8dSLABBE Corentin return ret; 5969f93ac8dSLABBE Corentin } 5979f93ac8dSLABBE Corentin } 5989f93ac8dSLABBE Corentin 599b8239638SSamuel Holland if (gmac->use_internal_phy) { 600b8239638SSamuel Holland ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); 601b8239638SSamuel Holland if (ret) 602b76bbb34SJisheng Zhang goto err_disable_regulator; 6039f93ac8dSLABBE Corentin } 6049f93ac8dSLABBE Corentin 6059f93ac8dSLABBE Corentin return 0; 606b8239638SSamuel Holland 607b8239638SSamuel Holland err_disable_regulator: 608b8239638SSamuel Holland if (gmac->regulator) 609b8239638SSamuel Holland regulator_disable(gmac->regulator); 610b8239638SSamuel Holland 611b8239638SSamuel Holland return ret; 6129f93ac8dSLABBE Corentin } 6139f93ac8dSLABBE Corentin 6148cad443eSFlorian Fainelli static void sun8i_dwmac_core_init(struct mac_device_info *hw, 6158cad443eSFlorian Fainelli struct net_device *dev) 6169f93ac8dSLABBE Corentin { 6179f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6189f93ac8dSLABBE Corentin u32 v; 6199f93ac8dSLABBE Corentin 6209f93ac8dSLABBE Corentin v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ 6219f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_BASIC_CTL1); 6229f93ac8dSLABBE Corentin } 6239f93ac8dSLABBE Corentin 6249f93ac8dSLABBE Corentin static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) 6259f93ac8dSLABBE Corentin { 6269f93ac8dSLABBE Corentin u32 t, r; 6279f93ac8dSLABBE Corentin 6289f93ac8dSLABBE Corentin t = readl(ioaddr + EMAC_TX_CTL0); 6299f93ac8dSLABBE Corentin r = readl(ioaddr + EMAC_RX_CTL0); 6309f93ac8dSLABBE Corentin if (enable) { 6319f93ac8dSLABBE Corentin t |= EMAC_TX_TRANSMITTER_EN; 6329f93ac8dSLABBE Corentin r |= EMAC_RX_RECEIVER_EN; 6339f93ac8dSLABBE Corentin } else { 6349f93ac8dSLABBE Corentin t &= ~EMAC_TX_TRANSMITTER_EN; 6359f93ac8dSLABBE Corentin r &= ~EMAC_RX_RECEIVER_EN; 6369f93ac8dSLABBE Corentin } 6379f93ac8dSLABBE Corentin writel(t, ioaddr + EMAC_TX_CTL0); 6389f93ac8dSLABBE Corentin writel(r, ioaddr + EMAC_RX_CTL0); 6399f93ac8dSLABBE Corentin } 6409f93ac8dSLABBE Corentin 6419f93ac8dSLABBE Corentin /* Set MAC address at slot reg_n 6429f93ac8dSLABBE Corentin * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST 6439f93ac8dSLABBE Corentin * If addr is NULL, clear the slot 6449f93ac8dSLABBE Corentin */ 6459f93ac8dSLABBE Corentin static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, 64676660757SJakub Kicinski const unsigned char *addr, 6479f93ac8dSLABBE Corentin unsigned int reg_n) 6489f93ac8dSLABBE Corentin { 6499f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6509f93ac8dSLABBE Corentin u32 v; 6519f93ac8dSLABBE Corentin 6529f93ac8dSLABBE Corentin if (!addr) { 6539f93ac8dSLABBE Corentin writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); 6549f93ac8dSLABBE Corentin return; 6559f93ac8dSLABBE Corentin } 6569f93ac8dSLABBE Corentin 6579f93ac8dSLABBE Corentin stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 6589f93ac8dSLABBE Corentin EMAC_MACADDR_LO(reg_n)); 6599f93ac8dSLABBE Corentin if (reg_n > 0) { 6609f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); 6619f93ac8dSLABBE Corentin v |= MAC_ADDR_TYPE_DST; 6629f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); 6639f93ac8dSLABBE Corentin } 6649f93ac8dSLABBE Corentin } 6659f93ac8dSLABBE Corentin 6669f93ac8dSLABBE Corentin static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, 6679f93ac8dSLABBE Corentin unsigned char *addr, 6689f93ac8dSLABBE Corentin unsigned int reg_n) 6699f93ac8dSLABBE Corentin { 6709f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6719f93ac8dSLABBE Corentin 6729f93ac8dSLABBE Corentin stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), 6739f93ac8dSLABBE Corentin EMAC_MACADDR_LO(reg_n)); 6749f93ac8dSLABBE Corentin } 6759f93ac8dSLABBE Corentin 6769f93ac8dSLABBE Corentin /* caution this function must return non 0 to work */ 6779f93ac8dSLABBE Corentin static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) 6789f93ac8dSLABBE Corentin { 6799f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6809f93ac8dSLABBE Corentin u32 v; 6819f93ac8dSLABBE Corentin 6829f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL0); 6839f93ac8dSLABBE Corentin v |= EMAC_RX_DO_CRC; 6849f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL0); 6859f93ac8dSLABBE Corentin 6869f93ac8dSLABBE Corentin return 1; 6879f93ac8dSLABBE Corentin } 6889f93ac8dSLABBE Corentin 6899f93ac8dSLABBE Corentin static void sun8i_dwmac_set_filter(struct mac_device_info *hw, 6909f93ac8dSLABBE Corentin struct net_device *dev) 6919f93ac8dSLABBE Corentin { 6929f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 6939f93ac8dSLABBE Corentin u32 v; 6949f93ac8dSLABBE Corentin int i = 1; 6959f93ac8dSLABBE Corentin struct netdev_hw_addr *ha; 6969f93ac8dSLABBE Corentin int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; 6979f93ac8dSLABBE Corentin 6989f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_CTL; 6999f93ac8dSLABBE Corentin 7009f93ac8dSLABBE Corentin if (dev->flags & IFF_PROMISC) { 7019f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_RXALL; 7029f93ac8dSLABBE Corentin } else if (dev->flags & IFF_ALLMULTI) { 7039f93ac8dSLABBE Corentin v |= EMAC_FRM_FLT_MULTICAST; 7049f93ac8dSLABBE Corentin } else if (macaddrs <= hw->unicast_filter_entries) { 7059f93ac8dSLABBE Corentin if (!netdev_mc_empty(dev)) { 7069f93ac8dSLABBE Corentin netdev_for_each_mc_addr(ha, dev) { 7079f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 7089f93ac8dSLABBE Corentin i++; 7099f93ac8dSLABBE Corentin } 7109f93ac8dSLABBE Corentin } 7119f93ac8dSLABBE Corentin if (!netdev_uc_empty(dev)) { 7129f93ac8dSLABBE Corentin netdev_for_each_uc_addr(ha, dev) { 7139f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, ha->addr, i); 7149f93ac8dSLABBE Corentin i++; 7159f93ac8dSLABBE Corentin } 7169f93ac8dSLABBE Corentin } 7179f93ac8dSLABBE Corentin } else { 71805908d72SMans Rullgard if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL)) 7199f93ac8dSLABBE Corentin netdev_info(dev, "Too many address, switching to promiscuous\n"); 7209f93ac8dSLABBE Corentin v = EMAC_FRM_FLT_RXALL; 7219f93ac8dSLABBE Corentin } 7229f93ac8dSLABBE Corentin 7239f93ac8dSLABBE Corentin /* Disable unused address filter slots */ 7249f93ac8dSLABBE Corentin while (i < hw->unicast_filter_entries) 7259f93ac8dSLABBE Corentin sun8i_dwmac_set_umac_addr(hw, NULL, i++); 7269f93ac8dSLABBE Corentin 7279f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_FRM_FLT); 7289f93ac8dSLABBE Corentin } 7299f93ac8dSLABBE Corentin 7309f93ac8dSLABBE Corentin static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, 7319f93ac8dSLABBE Corentin unsigned int duplex, unsigned int fc, 7329f93ac8dSLABBE Corentin unsigned int pause_time, u32 tx_cnt) 7339f93ac8dSLABBE Corentin { 7349f93ac8dSLABBE Corentin void __iomem *ioaddr = hw->pcsr; 7359f93ac8dSLABBE Corentin u32 v; 7369f93ac8dSLABBE Corentin 7379f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_RX_CTL0); 7389f93ac8dSLABBE Corentin if (fc == FLOW_AUTO) 7399f93ac8dSLABBE Corentin v |= EMAC_RX_FLOW_CTL_EN; 7409f93ac8dSLABBE Corentin else 7419f93ac8dSLABBE Corentin v &= ~EMAC_RX_FLOW_CTL_EN; 7429f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_RX_CTL0); 7439f93ac8dSLABBE Corentin 7449f93ac8dSLABBE Corentin v = readl(ioaddr + EMAC_TX_FLOW_CTL); 7459f93ac8dSLABBE Corentin if (fc == FLOW_AUTO) 7469f93ac8dSLABBE Corentin v |= EMAC_TX_FLOW_CTL_EN; 7479f93ac8dSLABBE Corentin else 7489f93ac8dSLABBE Corentin v &= ~EMAC_TX_FLOW_CTL_EN; 7499f93ac8dSLABBE Corentin writel(v, ioaddr + EMAC_TX_FLOW_CTL); 7509f93ac8dSLABBE Corentin } 7519f93ac8dSLABBE Corentin 7529f93ac8dSLABBE Corentin static int sun8i_dwmac_reset(struct stmmac_priv *priv) 7539f93ac8dSLABBE Corentin { 7549f93ac8dSLABBE Corentin u32 v; 7559f93ac8dSLABBE Corentin int err; 7569f93ac8dSLABBE Corentin 7579f93ac8dSLABBE Corentin v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 7589f93ac8dSLABBE Corentin writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 7599f93ac8dSLABBE Corentin 7609f93ac8dSLABBE Corentin /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 7619f93ac8dSLABBE Corentin * need more if no cable plugged. 100ms seems OK 7629f93ac8dSLABBE Corentin */ 7639f93ac8dSLABBE Corentin err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, 7649f93ac8dSLABBE Corentin !(v & 0x01), 100, 100000); 7659f93ac8dSLABBE Corentin 7669f93ac8dSLABBE Corentin if (err) { 7679f93ac8dSLABBE Corentin dev_err(priv->device, "EMAC reset timeout\n"); 7689e0db41eSJisheng Zhang return err; 7699f93ac8dSLABBE Corentin } 7709f93ac8dSLABBE Corentin return 0; 7719f93ac8dSLABBE Corentin } 7729f93ac8dSLABBE Corentin 773634db83bSCorentin Labbe /* Search in mdio-mux node for internal PHY node and get its clk/reset */ 774634db83bSCorentin Labbe static int get_ephy_nodes(struct stmmac_priv *priv) 775634db83bSCorentin Labbe { 776634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 777634db83bSCorentin Labbe struct device_node *mdio_mux, *iphynode; 778634db83bSCorentin Labbe struct device_node *mdio_internal; 779634db83bSCorentin Labbe int ret; 780634db83bSCorentin Labbe 781634db83bSCorentin Labbe mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 782634db83bSCorentin Labbe if (!mdio_mux) { 783634db83bSCorentin Labbe dev_err(priv->device, "Cannot get mdio-mux node\n"); 784634db83bSCorentin Labbe return -ENODEV; 785634db83bSCorentin Labbe } 786634db83bSCorentin Labbe 787ac63043dSJohan Hovold mdio_internal = of_get_compatible_child(mdio_mux, 788634db83bSCorentin Labbe "allwinner,sun8i-h3-mdio-internal"); 789ac63043dSJohan Hovold of_node_put(mdio_mux); 790634db83bSCorentin Labbe if (!mdio_internal) { 791634db83bSCorentin Labbe dev_err(priv->device, "Cannot get internal_mdio node\n"); 792634db83bSCorentin Labbe return -ENODEV; 793634db83bSCorentin Labbe } 794634db83bSCorentin Labbe 795634db83bSCorentin Labbe /* Seek for internal PHY */ 796634db83bSCorentin Labbe for_each_child_of_node(mdio_internal, iphynode) { 797634db83bSCorentin Labbe gmac->ephy_clk = of_clk_get(iphynode, 0); 798634db83bSCorentin Labbe if (IS_ERR(gmac->ephy_clk)) 799634db83bSCorentin Labbe continue; 800634db83bSCorentin Labbe gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); 801634db83bSCorentin Labbe if (IS_ERR(gmac->rst_ephy)) { 802634db83bSCorentin Labbe ret = PTR_ERR(gmac->rst_ephy); 803ac63043dSJohan Hovold if (ret == -EPROBE_DEFER) { 804ac63043dSJohan Hovold of_node_put(iphynode); 805ac63043dSJohan Hovold of_node_put(mdio_internal); 806634db83bSCorentin Labbe return ret; 807ac63043dSJohan Hovold } 808634db83bSCorentin Labbe continue; 809634db83bSCorentin Labbe } 810634db83bSCorentin Labbe dev_info(priv->device, "Found internal PHY node\n"); 811ac63043dSJohan Hovold of_node_put(iphynode); 812ac63043dSJohan Hovold of_node_put(mdio_internal); 813634db83bSCorentin Labbe return 0; 814634db83bSCorentin Labbe } 815ac63043dSJohan Hovold 816ac63043dSJohan Hovold of_node_put(mdio_internal); 817634db83bSCorentin Labbe return -ENODEV; 818634db83bSCorentin Labbe } 819634db83bSCorentin Labbe 820634db83bSCorentin Labbe static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) 821634db83bSCorentin Labbe { 822634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 823634db83bSCorentin Labbe int ret; 824634db83bSCorentin Labbe 825634db83bSCorentin Labbe if (gmac->internal_phy_powered) { 826634db83bSCorentin Labbe dev_warn(priv->device, "Internal PHY already powered\n"); 827634db83bSCorentin Labbe return 0; 828634db83bSCorentin Labbe } 829634db83bSCorentin Labbe 830634db83bSCorentin Labbe dev_info(priv->device, "Powering internal PHY\n"); 831634db83bSCorentin Labbe ret = clk_prepare_enable(gmac->ephy_clk); 832634db83bSCorentin Labbe if (ret) { 833634db83bSCorentin Labbe dev_err(priv->device, "Cannot enable internal PHY\n"); 834634db83bSCorentin Labbe return ret; 835634db83bSCorentin Labbe } 836634db83bSCorentin Labbe 837634db83bSCorentin Labbe /* Make sure the EPHY is properly reseted, as U-Boot may leave 838634db83bSCorentin Labbe * it at deasserted state, and thus it may fail to reset EMAC. 8391c22f546SSamuel Holland * 8401c22f546SSamuel Holland * This assumes the driver has exclusive access to the EPHY reset. 841634db83bSCorentin Labbe */ 8421c22f546SSamuel Holland ret = reset_control_reset(gmac->rst_ephy); 843634db83bSCorentin Labbe if (ret) { 8441c22f546SSamuel Holland dev_err(priv->device, "Cannot reset internal PHY\n"); 845634db83bSCorentin Labbe clk_disable_unprepare(gmac->ephy_clk); 846634db83bSCorentin Labbe return ret; 847634db83bSCorentin Labbe } 848634db83bSCorentin Labbe 849634db83bSCorentin Labbe gmac->internal_phy_powered = true; 850634db83bSCorentin Labbe 851634db83bSCorentin Labbe return 0; 852634db83bSCorentin Labbe } 853634db83bSCorentin Labbe 854557ef2dfSSamuel Holland static void sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) 855634db83bSCorentin Labbe { 856634db83bSCorentin Labbe if (!gmac->internal_phy_powered) 857557ef2dfSSamuel Holland return; 858634db83bSCorentin Labbe 859634db83bSCorentin Labbe clk_disable_unprepare(gmac->ephy_clk); 860634db83bSCorentin Labbe reset_control_assert(gmac->rst_ephy); 861634db83bSCorentin Labbe gmac->internal_phy_powered = false; 862634db83bSCorentin Labbe } 863634db83bSCorentin Labbe 864634db83bSCorentin Labbe /* MDIO multiplexing switch function 865634db83bSCorentin Labbe * This function is called by the mdio-mux layer when it thinks the mdio bus 866634db83bSCorentin Labbe * multiplexer needs to switch. 867634db83bSCorentin Labbe * 'current_child' is the current value of the mux register 868634db83bSCorentin Labbe * 'desired_child' is the value of the 'reg' property of the target child MDIO 869634db83bSCorentin Labbe * node. 870634db83bSCorentin Labbe * The first time this function is called, current_child == -1. 871634db83bSCorentin Labbe * If current_child == desired_child, then the mux is already set to the 872634db83bSCorentin Labbe * correct bus. 873634db83bSCorentin Labbe */ 874634db83bSCorentin Labbe static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, 875634db83bSCorentin Labbe void *data) 876634db83bSCorentin Labbe { 877634db83bSCorentin Labbe struct stmmac_priv *priv = data; 878634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 879634db83bSCorentin Labbe u32 reg, val; 880634db83bSCorentin Labbe int ret = 0; 881634db83bSCorentin Labbe 882634db83bSCorentin Labbe if (current_child ^ desired_child) { 88325ae15fbSChen-Yu Tsai regmap_field_read(gmac->regmap_field, ®); 884634db83bSCorentin Labbe switch (desired_child) { 885634db83bSCorentin Labbe case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: 886634db83bSCorentin Labbe dev_info(priv->device, "Switch mux to internal PHY"); 887634db83bSCorentin Labbe val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; 888b8239638SSamuel Holland gmac->use_internal_phy = true; 889634db83bSCorentin Labbe break; 890634db83bSCorentin Labbe case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: 891634db83bSCorentin Labbe dev_info(priv->device, "Switch mux to external PHY"); 892634db83bSCorentin Labbe val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; 893b8239638SSamuel Holland gmac->use_internal_phy = false; 894634db83bSCorentin Labbe break; 895634db83bSCorentin Labbe default: 896634db83bSCorentin Labbe dev_err(priv->device, "Invalid child ID %x\n", 897634db83bSCorentin Labbe desired_child); 898634db83bSCorentin Labbe return -EINVAL; 899634db83bSCorentin Labbe } 90025ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, val); 901b8239638SSamuel Holland if (gmac->use_internal_phy) { 902634db83bSCorentin Labbe ret = sun8i_dwmac_power_internal_phy(priv); 903634db83bSCorentin Labbe if (ret) 904634db83bSCorentin Labbe return ret; 905634db83bSCorentin Labbe } else { 906634db83bSCorentin Labbe sun8i_dwmac_unpower_internal_phy(gmac); 907634db83bSCorentin Labbe } 908634db83bSCorentin Labbe /* After changing syscon value, the MAC need reset or it will 909634db83bSCorentin Labbe * use the last value (and so the last PHY set). 910634db83bSCorentin Labbe */ 911634db83bSCorentin Labbe ret = sun8i_dwmac_reset(priv); 912634db83bSCorentin Labbe } 913634db83bSCorentin Labbe return ret; 914634db83bSCorentin Labbe } 915634db83bSCorentin Labbe 916634db83bSCorentin Labbe static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) 917634db83bSCorentin Labbe { 918634db83bSCorentin Labbe int ret; 919634db83bSCorentin Labbe struct device_node *mdio_mux; 920634db83bSCorentin Labbe struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 921634db83bSCorentin Labbe 922634db83bSCorentin Labbe mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); 923634db83bSCorentin Labbe if (!mdio_mux) 924634db83bSCorentin Labbe return -ENODEV; 925634db83bSCorentin Labbe 926634db83bSCorentin Labbe ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, 927634db83bSCorentin Labbe &gmac->mux_handle, priv, priv->mii); 9281a15267bSYang Yingliang of_node_put(mdio_mux); 929634db83bSCorentin Labbe return ret; 930634db83bSCorentin Labbe } 931634db83bSCorentin Labbe 9329b1e39cfSSamuel Holland static int sun8i_dwmac_set_syscon(struct device *dev, 9339b1e39cfSSamuel Holland struct plat_stmmacenet_data *plat) 9349f93ac8dSLABBE Corentin { 9359b1e39cfSSamuel Holland struct sunxi_priv_data *gmac = plat->bsp_priv; 9369b1e39cfSSamuel Holland struct device_node *node = dev->of_node; 937d93b07f8SLABBE Corentin int ret; 9389f93ac8dSLABBE Corentin u32 reg, val; 9399f93ac8dSLABBE Corentin 940e33b4325SYizhuo ret = regmap_field_read(gmac->regmap_field, &val); 941e33b4325SYizhuo if (ret) { 9429b1e39cfSSamuel Holland dev_err(dev, "Fail to read from regmap field.\n"); 943e33b4325SYizhuo return ret; 944e33b4325SYizhuo } 945e33b4325SYizhuo 9469f93ac8dSLABBE Corentin reg = gmac->variant->default_syscon_value; 9479f93ac8dSLABBE Corentin if (reg != val) 9489b1e39cfSSamuel Holland dev_warn(dev, 9499f93ac8dSLABBE Corentin "Current syscon value is not the default %x (expect %x)\n", 9509f93ac8dSLABBE Corentin val, reg); 9519f93ac8dSLABBE Corentin 952634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 9531c08ac0cSCorentin Labbe if (of_property_read_bool(node, "allwinner,leds-active-low")) 9549f93ac8dSLABBE Corentin reg |= H3_EPHY_LED_POL; 9559f93ac8dSLABBE Corentin else 9569f93ac8dSLABBE Corentin reg &= ~H3_EPHY_LED_POL; 9579f93ac8dSLABBE Corentin 9581450ba8aSIcenowy Zheng /* Force EPHY xtal frequency to 24MHz. */ 9591450ba8aSIcenowy Zheng reg |= H3_EPHY_CLK_SEL; 9601450ba8aSIcenowy Zheng 9619b1e39cfSSamuel Holland ret = of_mdio_parse_addr(dev, plat->phy_node); 9629f93ac8dSLABBE Corentin if (ret < 0) { 9639b1e39cfSSamuel Holland dev_err(dev, "Could not parse MDIO addr\n"); 9649f93ac8dSLABBE Corentin return ret; 9659f93ac8dSLABBE Corentin } 9669f93ac8dSLABBE Corentin /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY 9679f93ac8dSLABBE Corentin * address. No need to mask it again. 9689f93ac8dSLABBE Corentin */ 969634db83bSCorentin Labbe reg |= 1 << H3_EPHY_ADDR_SHIFT; 9700fec7e72SIcenowy Zheng } else { 9710fec7e72SIcenowy Zheng /* For SoCs without internal PHY the PHY selection bit should be 9720fec7e72SIcenowy Zheng * set to 0 (external PHY). 9730fec7e72SIcenowy Zheng */ 9740fec7e72SIcenowy Zheng reg &= ~H3_EPHY_SELECT; 9759f93ac8dSLABBE Corentin } 9769f93ac8dSLABBE Corentin 9779f93ac8dSLABBE Corentin if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { 9789f93ac8dSLABBE Corentin if (val % 100) { 9799b1e39cfSSamuel Holland dev_err(dev, "tx-delay must be a multiple of 100\n"); 9809f93ac8dSLABBE Corentin return -EINVAL; 9819f93ac8dSLABBE Corentin } 9829f93ac8dSLABBE Corentin val /= 100; 9839b1e39cfSSamuel Holland dev_dbg(dev, "set tx-delay to %x\n", val); 9847b270b72SChen-Yu Tsai if (val <= gmac->variant->tx_delay_max) { 9857b270b72SChen-Yu Tsai reg &= ~(gmac->variant->tx_delay_max << 9867b270b72SChen-Yu Tsai SYSCON_ETXDC_SHIFT); 9879f93ac8dSLABBE Corentin reg |= (val << SYSCON_ETXDC_SHIFT); 9889f93ac8dSLABBE Corentin } else { 9899b1e39cfSSamuel Holland dev_err(dev, "Invalid TX clock delay: %d\n", 9909f93ac8dSLABBE Corentin val); 9919f93ac8dSLABBE Corentin return -EINVAL; 9929f93ac8dSLABBE Corentin } 9939f93ac8dSLABBE Corentin } 9949f93ac8dSLABBE Corentin 9959f93ac8dSLABBE Corentin if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { 9969f93ac8dSLABBE Corentin if (val % 100) { 9979b1e39cfSSamuel Holland dev_err(dev, "rx-delay must be a multiple of 100\n"); 9989f93ac8dSLABBE Corentin return -EINVAL; 9999f93ac8dSLABBE Corentin } 10009f93ac8dSLABBE Corentin val /= 100; 10019b1e39cfSSamuel Holland dev_dbg(dev, "set rx-delay to %x\n", val); 10027b270b72SChen-Yu Tsai if (val <= gmac->variant->rx_delay_max) { 10037b270b72SChen-Yu Tsai reg &= ~(gmac->variant->rx_delay_max << 10047b270b72SChen-Yu Tsai SYSCON_ERXDC_SHIFT); 10059f93ac8dSLABBE Corentin reg |= (val << SYSCON_ERXDC_SHIFT); 10069f93ac8dSLABBE Corentin } else { 10079b1e39cfSSamuel Holland dev_err(dev, "Invalid RX clock delay: %d\n", 10089f93ac8dSLABBE Corentin val); 10099f93ac8dSLABBE Corentin return -EINVAL; 10109f93ac8dSLABBE Corentin } 10119f93ac8dSLABBE Corentin } 10129f93ac8dSLABBE Corentin 10139f93ac8dSLABBE Corentin /* Clear interface mode bits */ 10149f93ac8dSLABBE Corentin reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); 10159f93ac8dSLABBE Corentin if (gmac->variant->support_rmii) 10169f93ac8dSLABBE Corentin reg &= ~SYSCON_RMII_EN; 10179f93ac8dSLABBE Corentin 10189b1e39cfSSamuel Holland switch (plat->interface) { 10199f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_MII: 10209f93ac8dSLABBE Corentin /* default */ 10219f93ac8dSLABBE Corentin break; 10229f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_RGMII: 1023f1239d8aSChen-Yu Tsai case PHY_INTERFACE_MODE_RGMII_ID: 1024f1239d8aSChen-Yu Tsai case PHY_INTERFACE_MODE_RGMII_RXID: 1025f1239d8aSChen-Yu Tsai case PHY_INTERFACE_MODE_RGMII_TXID: 10269f93ac8dSLABBE Corentin reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; 10279f93ac8dSLABBE Corentin break; 10289f93ac8dSLABBE Corentin case PHY_INTERFACE_MODE_RMII: 10299f93ac8dSLABBE Corentin reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; 10309f93ac8dSLABBE Corentin break; 10319f93ac8dSLABBE Corentin default: 10329b1e39cfSSamuel Holland dev_err(dev, "Unsupported interface mode: %s", 10339b1e39cfSSamuel Holland phy_modes(plat->interface)); 10349f93ac8dSLABBE Corentin return -EINVAL; 10359f93ac8dSLABBE Corentin } 10369f93ac8dSLABBE Corentin 103725ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, reg); 10389f93ac8dSLABBE Corentin 10399f93ac8dSLABBE Corentin return 0; 10409f93ac8dSLABBE Corentin } 10419f93ac8dSLABBE Corentin 10429f93ac8dSLABBE Corentin static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) 10439f93ac8dSLABBE Corentin { 10449f93ac8dSLABBE Corentin u32 reg = gmac->variant->default_syscon_value; 10459f93ac8dSLABBE Corentin 104625ae15fbSChen-Yu Tsai regmap_field_write(gmac->regmap_field, reg); 10479f93ac8dSLABBE Corentin } 10489f93ac8dSLABBE Corentin 10499f93ac8dSLABBE Corentin static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) 10509f93ac8dSLABBE Corentin { 10519f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac = priv; 10529f93ac8dSLABBE Corentin 1053afac1d34SSamuel Holland if (gmac->variant->soc_has_internal_phy) 1054634db83bSCorentin Labbe sun8i_dwmac_unpower_internal_phy(gmac); 1055634db83bSCorentin Labbe 10569f93ac8dSLABBE Corentin if (gmac->regulator) 10579f93ac8dSLABBE Corentin regulator_disable(gmac->regulator); 10589f93ac8dSLABBE Corentin } 10599f93ac8dSLABBE Corentin 10608edb1271SCorentin Labbe static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) 10618edb1271SCorentin Labbe { 10628edb1271SCorentin Labbe u32 value = readl(ioaddr + EMAC_BASIC_CTL0); 10638edb1271SCorentin Labbe 10648edb1271SCorentin Labbe if (enable) 10658edb1271SCorentin Labbe value |= EMAC_LOOPBACK; 10668edb1271SCorentin Labbe else 10678edb1271SCorentin Labbe value &= ~EMAC_LOOPBACK; 10688edb1271SCorentin Labbe 10698edb1271SCorentin Labbe writel(value, ioaddr + EMAC_BASIC_CTL0); 10708edb1271SCorentin Labbe } 10718edb1271SCorentin Labbe 10729f93ac8dSLABBE Corentin static const struct stmmac_ops sun8i_dwmac_ops = { 10739f93ac8dSLABBE Corentin .core_init = sun8i_dwmac_core_init, 10749f93ac8dSLABBE Corentin .set_mac = sun8i_dwmac_set_mac, 10759f93ac8dSLABBE Corentin .dump_regs = sun8i_dwmac_dump_mac_regs, 10769f93ac8dSLABBE Corentin .rx_ipc = sun8i_dwmac_rx_ipc_enable, 10779f93ac8dSLABBE Corentin .set_filter = sun8i_dwmac_set_filter, 10789f93ac8dSLABBE Corentin .flow_ctrl = sun8i_dwmac_flow_ctrl, 10799f93ac8dSLABBE Corentin .set_umac_addr = sun8i_dwmac_set_umac_addr, 10809f93ac8dSLABBE Corentin .get_umac_addr = sun8i_dwmac_get_umac_addr, 10818edb1271SCorentin Labbe .set_mac_loopback = sun8i_dwmac_set_mac_loopback, 10829f93ac8dSLABBE Corentin }; 10839f93ac8dSLABBE Corentin 10849f93ac8dSLABBE Corentin static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) 10859f93ac8dSLABBE Corentin { 10869f93ac8dSLABBE Corentin struct mac_device_info *mac; 10879f93ac8dSLABBE Corentin struct stmmac_priv *priv = ppriv; 10889f93ac8dSLABBE Corentin 10899f93ac8dSLABBE Corentin mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); 10909f93ac8dSLABBE Corentin if (!mac) 10919f93ac8dSLABBE Corentin return NULL; 10929f93ac8dSLABBE Corentin 10939f93ac8dSLABBE Corentin mac->pcsr = priv->ioaddr; 10949f93ac8dSLABBE Corentin mac->mac = &sun8i_dwmac_ops; 10959f93ac8dSLABBE Corentin mac->dma = &sun8i_dwmac_dma_ops; 10969f93ac8dSLABBE Corentin 1097d4c26eb6SCorentin Labbe priv->dev->priv_flags |= IFF_UNICAST_FLT; 1098d4c26eb6SCorentin Labbe 10999f93ac8dSLABBE Corentin /* The loopback bit seems to be re-set when link change 11009f93ac8dSLABBE Corentin * Simply mask it each time 11019f93ac8dSLABBE Corentin * Speed 10/100/1000 are set in BIT(2)/BIT(3) 11029f93ac8dSLABBE Corentin */ 11039f93ac8dSLABBE Corentin mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; 11049f93ac8dSLABBE Corentin mac->link.speed10 = EMAC_SPEED_10; 11059f93ac8dSLABBE Corentin mac->link.speed100 = EMAC_SPEED_100; 11069f93ac8dSLABBE Corentin mac->link.speed1000 = EMAC_SPEED_1000; 11079f93ac8dSLABBE Corentin mac->link.duplex = EMAC_DUPLEX_FULL; 11089f93ac8dSLABBE Corentin mac->mii.addr = EMAC_MDIO_CMD; 11099f93ac8dSLABBE Corentin mac->mii.data = EMAC_MDIO_DATA; 11109f93ac8dSLABBE Corentin mac->mii.reg_shift = 4; 11119f93ac8dSLABBE Corentin mac->mii.reg_mask = GENMASK(8, 4); 11129f93ac8dSLABBE Corentin mac->mii.addr_shift = 12; 11139f93ac8dSLABBE Corentin mac->mii.addr_mask = GENMASK(16, 12); 11149f93ac8dSLABBE Corentin mac->mii.clk_csr_shift = 20; 11159f93ac8dSLABBE Corentin mac->mii.clk_csr_mask = GENMASK(22, 20); 11169f93ac8dSLABBE Corentin mac->unicast_filter_entries = 8; 11179f93ac8dSLABBE Corentin 11189f93ac8dSLABBE Corentin /* Synopsys Id is not available */ 11199f93ac8dSLABBE Corentin priv->synopsys_id = 0; 11209f93ac8dSLABBE Corentin 11219f93ac8dSLABBE Corentin return mac; 11229f93ac8dSLABBE Corentin } 11239f93ac8dSLABBE Corentin 112449a06caeSChen-Yu Tsai static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node) 112549a06caeSChen-Yu Tsai { 112649a06caeSChen-Yu Tsai struct device_node *syscon_node; 112749a06caeSChen-Yu Tsai struct platform_device *syscon_pdev; 112849a06caeSChen-Yu Tsai struct regmap *regmap = NULL; 112949a06caeSChen-Yu Tsai 113049a06caeSChen-Yu Tsai syscon_node = of_parse_phandle(node, "syscon", 0); 113149a06caeSChen-Yu Tsai if (!syscon_node) 113249a06caeSChen-Yu Tsai return ERR_PTR(-ENODEV); 113349a06caeSChen-Yu Tsai 113449a06caeSChen-Yu Tsai syscon_pdev = of_find_device_by_node(syscon_node); 113549a06caeSChen-Yu Tsai if (!syscon_pdev) { 113649a06caeSChen-Yu Tsai /* platform device might not be probed yet */ 113749a06caeSChen-Yu Tsai regmap = ERR_PTR(-EPROBE_DEFER); 113849a06caeSChen-Yu Tsai goto out_put_node; 113949a06caeSChen-Yu Tsai } 114049a06caeSChen-Yu Tsai 114149a06caeSChen-Yu Tsai /* If no regmap is found then the other device driver is at fault */ 114249a06caeSChen-Yu Tsai regmap = dev_get_regmap(&syscon_pdev->dev, NULL); 114349a06caeSChen-Yu Tsai if (!regmap) 114449a06caeSChen-Yu Tsai regmap = ERR_PTR(-EINVAL); 114549a06caeSChen-Yu Tsai 114649a06caeSChen-Yu Tsai platform_device_put(syscon_pdev); 114749a06caeSChen-Yu Tsai out_put_node: 114849a06caeSChen-Yu Tsai of_node_put(syscon_node); 114949a06caeSChen-Yu Tsai return regmap; 115049a06caeSChen-Yu Tsai } 115149a06caeSChen-Yu Tsai 11529f93ac8dSLABBE Corentin static int sun8i_dwmac_probe(struct platform_device *pdev) 11539f93ac8dSLABBE Corentin { 11549f93ac8dSLABBE Corentin struct plat_stmmacenet_data *plat_dat; 11559f93ac8dSLABBE Corentin struct stmmac_resources stmmac_res; 11569f93ac8dSLABBE Corentin struct sunxi_priv_data *gmac; 11579f93ac8dSLABBE Corentin struct device *dev = &pdev->dev; 11580c65b2b9SAndrew Lunn phy_interface_t interface; 11599f93ac8dSLABBE Corentin int ret; 1160634db83bSCorentin Labbe struct stmmac_priv *priv; 1161634db83bSCorentin Labbe struct net_device *ndev; 116225ae15fbSChen-Yu Tsai struct regmap *regmap; 11639f93ac8dSLABBE Corentin 11649f93ac8dSLABBE Corentin ret = stmmac_get_platform_resources(pdev, &stmmac_res); 11659f93ac8dSLABBE Corentin if (ret) 11669f93ac8dSLABBE Corentin return ret; 11679f93ac8dSLABBE Corentin 11689f93ac8dSLABBE Corentin gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); 11699f93ac8dSLABBE Corentin if (!gmac) 11709f93ac8dSLABBE Corentin return -ENOMEM; 11719f93ac8dSLABBE Corentin 11729f93ac8dSLABBE Corentin gmac->variant = of_device_get_match_data(&pdev->dev); 11739f93ac8dSLABBE Corentin if (!gmac->variant) { 11749f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); 11759f93ac8dSLABBE Corentin return -EINVAL; 11769f93ac8dSLABBE Corentin } 11779f93ac8dSLABBE Corentin 11789f93ac8dSLABBE Corentin /* Optional regulator for PHY */ 11799f93ac8dSLABBE Corentin gmac->regulator = devm_regulator_get_optional(dev, "phy"); 11809f93ac8dSLABBE Corentin if (IS_ERR(gmac->regulator)) { 11819f93ac8dSLABBE Corentin if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) 11829f93ac8dSLABBE Corentin return -EPROBE_DEFER; 11839f93ac8dSLABBE Corentin dev_info(dev, "No regulator found\n"); 11849f93ac8dSLABBE Corentin gmac->regulator = NULL; 11859f93ac8dSLABBE Corentin } 11869f93ac8dSLABBE Corentin 118749a06caeSChen-Yu Tsai /* The "GMAC clock control" register might be located in the 118849a06caeSChen-Yu Tsai * CCU address range (on the R40), or the system control address 118949a06caeSChen-Yu Tsai * range (on most other sun8i and later SoCs). 119049a06caeSChen-Yu Tsai * 119149a06caeSChen-Yu Tsai * The former controls most if not all clocks in the SoC. The 119249a06caeSChen-Yu Tsai * latter has an SoC identification register, and on some SoCs, 119349a06caeSChen-Yu Tsai * controls to map device specific SRAM to either the intended 119449a06caeSChen-Yu Tsai * peripheral, or the CPU address space. 119549a06caeSChen-Yu Tsai * 119649a06caeSChen-Yu Tsai * In either case, there should be a coordinated and restricted 119749a06caeSChen-Yu Tsai * method of accessing the register needed here. This is done by 119849a06caeSChen-Yu Tsai * having the device export a custom regmap, instead of a generic 119949a06caeSChen-Yu Tsai * syscon, which grants all access to all registers. 120049a06caeSChen-Yu Tsai * 120149a06caeSChen-Yu Tsai * To support old device trees, we fall back to using the syscon 120249a06caeSChen-Yu Tsai * interface if possible. 120349a06caeSChen-Yu Tsai */ 120449a06caeSChen-Yu Tsai regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); 120549a06caeSChen-Yu Tsai if (IS_ERR(regmap)) 120649a06caeSChen-Yu Tsai regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 120749a06caeSChen-Yu Tsai "syscon"); 120825ae15fbSChen-Yu Tsai if (IS_ERR(regmap)) { 120925ae15fbSChen-Yu Tsai ret = PTR_ERR(regmap); 12109f93ac8dSLABBE Corentin dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); 12119f93ac8dSLABBE Corentin return ret; 12129f93ac8dSLABBE Corentin } 12139f93ac8dSLABBE Corentin 121425ae15fbSChen-Yu Tsai gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, 121525ae15fbSChen-Yu Tsai *gmac->variant->syscon_field); 121625ae15fbSChen-Yu Tsai if (IS_ERR(gmac->regmap_field)) { 121725ae15fbSChen-Yu Tsai ret = PTR_ERR(gmac->regmap_field); 121825ae15fbSChen-Yu Tsai dev_err(dev, "Unable to map syscon register: %d\n", ret); 121925ae15fbSChen-Yu Tsai return ret; 122025ae15fbSChen-Yu Tsai } 122125ae15fbSChen-Yu Tsai 12220c65b2b9SAndrew Lunn ret = of_get_phy_mode(dev->of_node, &interface); 12230c65b2b9SAndrew Lunn if (ret) 12244ec850e5SKangjie Lu return -EINVAL; 12257eeecc4bSSamuel Holland 122683216e39SMichael Walle plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 12277eeecc4bSSamuel Holland if (IS_ERR(plat_dat)) 12287eeecc4bSSamuel Holland return PTR_ERR(plat_dat); 12299f93ac8dSLABBE Corentin 12309f93ac8dSLABBE Corentin /* platform data specifying hardware features and callbacks. 12319f93ac8dSLABBE Corentin * hardware features were copied from Allwinner drivers. 12329f93ac8dSLABBE Corentin */ 12337eeecc4bSSamuel Holland plat_dat->interface = interface; 12349f93ac8dSLABBE Corentin plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; 12359f93ac8dSLABBE Corentin plat_dat->tx_coe = 1; 1236d8daff28SBartosz Golaszewski plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I; 12379f93ac8dSLABBE Corentin plat_dat->bsp_priv = gmac; 12389f93ac8dSLABBE Corentin plat_dat->init = sun8i_dwmac_init; 12399f93ac8dSLABBE Corentin plat_dat->exit = sun8i_dwmac_exit; 12409f93ac8dSLABBE Corentin plat_dat->setup = sun8i_dwmac_setup; 1241014dfa26SCorentin Labbe plat_dat->tx_fifo_size = 4096; 1242014dfa26SCorentin Labbe plat_dat->rx_fifo_size = 16384; 12439f93ac8dSLABBE Corentin 12449b1e39cfSSamuel Holland ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); 12459f93ac8dSLABBE Corentin if (ret) 12467eeecc4bSSamuel Holland goto dwmac_deconfig; 12479f93ac8dSLABBE Corentin 12489b1e39cfSSamuel Holland ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); 12499b1e39cfSSamuel Holland if (ret) 12509b1e39cfSSamuel Holland goto dwmac_syscon; 12519b1e39cfSSamuel Holland 12529f93ac8dSLABBE Corentin ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 12539f93ac8dSLABBE Corentin if (ret) 1254634db83bSCorentin Labbe goto dwmac_exit; 12559f93ac8dSLABBE Corentin 1256634db83bSCorentin Labbe ndev = dev_get_drvdata(&pdev->dev); 1257634db83bSCorentin Labbe priv = netdev_priv(ndev); 12582743aa24SSamuel Holland 1259b76bbb34SJisheng Zhang /* the MAC is runtime suspended after stmmac_dvr_probe(), so we 1260b76bbb34SJisheng Zhang * need to ensure the MAC resume back before other operations such 1261b76bbb34SJisheng Zhang * as reset. 1262b76bbb34SJisheng Zhang */ 1263b76bbb34SJisheng Zhang pm_runtime_get_sync(&pdev->dev); 1264b76bbb34SJisheng Zhang 1265634db83bSCorentin Labbe /* The mux must be registered after parent MDIO 1266634db83bSCorentin Labbe * so after stmmac_dvr_probe() 1267634db83bSCorentin Labbe */ 1268634db83bSCorentin Labbe if (gmac->variant->soc_has_internal_phy) { 1269634db83bSCorentin Labbe ret = get_ephy_nodes(priv); 1270634db83bSCorentin Labbe if (ret) 12717eeecc4bSSamuel Holland goto dwmac_remove; 1272634db83bSCorentin Labbe ret = sun8i_dwmac_register_mdio_mux(priv); 1273634db83bSCorentin Labbe if (ret) { 1274634db83bSCorentin Labbe dev_err(&pdev->dev, "Failed to register mux\n"); 1275634db83bSCorentin Labbe goto dwmac_mux; 1276634db83bSCorentin Labbe } 1277634db83bSCorentin Labbe } else { 1278634db83bSCorentin Labbe ret = sun8i_dwmac_reset(priv); 1279634db83bSCorentin Labbe if (ret) 12807eeecc4bSSamuel Holland goto dwmac_remove; 1281634db83bSCorentin Labbe } 1282634db83bSCorentin Labbe 1283b76bbb34SJisheng Zhang pm_runtime_put(&pdev->dev); 1284b76bbb34SJisheng Zhang 12852743aa24SSamuel Holland return 0; 12862743aa24SSamuel Holland 1287634db83bSCorentin Labbe dwmac_mux: 128852925421SSamuel Holland reset_control_put(gmac->rst_ephy); 128952925421SSamuel Holland clk_put(gmac->ephy_clk); 12907eeecc4bSSamuel Holland dwmac_remove: 1291b76bbb34SJisheng Zhang pm_runtime_put_noidle(&pdev->dev); 12927eeecc4bSSamuel Holland stmmac_dvr_remove(&pdev->dev); 1293634db83bSCorentin Labbe dwmac_exit: 12947eeecc4bSSamuel Holland sun8i_dwmac_exit(pdev, gmac); 12959b1e39cfSSamuel Holland dwmac_syscon: 12969b1e39cfSSamuel Holland sun8i_dwmac_unset_syscon(gmac); 12977eeecc4bSSamuel Holland dwmac_deconfig: 12987eeecc4bSSamuel Holland stmmac_remove_config_dt(pdev, plat_dat); 12997eeecc4bSSamuel Holland 13009f93ac8dSLABBE Corentin return ret; 13019f93ac8dSLABBE Corentin } 13029f93ac8dSLABBE Corentin 1303cc708d4eSUwe Kleine-König static void sun8i_dwmac_remove(struct platform_device *pdev) 130452925421SSamuel Holland { 130552925421SSamuel Holland struct net_device *ndev = platform_get_drvdata(pdev); 130652925421SSamuel Holland struct stmmac_priv *priv = netdev_priv(ndev); 130752925421SSamuel Holland struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 130852925421SSamuel Holland 130952925421SSamuel Holland if (gmac->variant->soc_has_internal_phy) { 131052925421SSamuel Holland mdio_mux_uninit(gmac->mux_handle); 131152925421SSamuel Holland sun8i_dwmac_unpower_internal_phy(gmac); 131252925421SSamuel Holland reset_control_put(gmac->rst_ephy); 131352925421SSamuel Holland clk_put(gmac->ephy_clk); 131452925421SSamuel Holland } 131552925421SSamuel Holland 131652925421SSamuel Holland stmmac_pltfr_remove(pdev); 13179b1e39cfSSamuel Holland sun8i_dwmac_unset_syscon(gmac); 131852925421SSamuel Holland } 131952925421SSamuel Holland 132096be41d7SSamuel Holland static void sun8i_dwmac_shutdown(struct platform_device *pdev) 132196be41d7SSamuel Holland { 132296be41d7SSamuel Holland struct net_device *ndev = platform_get_drvdata(pdev); 132396be41d7SSamuel Holland struct stmmac_priv *priv = netdev_priv(ndev); 132496be41d7SSamuel Holland struct sunxi_priv_data *gmac = priv->plat->bsp_priv; 132596be41d7SSamuel Holland 132696be41d7SSamuel Holland sun8i_dwmac_exit(pdev, gmac); 132796be41d7SSamuel Holland } 132896be41d7SSamuel Holland 13299f93ac8dSLABBE Corentin static const struct of_device_id sun8i_dwmac_match[] = { 1330a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-h3-emac", 1331a8ff8ccbSCorentin Labbe .data = &emac_variant_h3 }, 1332a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-v3s-emac", 1333a8ff8ccbSCorentin Labbe .data = &emac_variant_v3s }, 1334a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun8i-a83t-emac", 1335a8ff8ccbSCorentin Labbe .data = &emac_variant_a83t }, 13369bf5085aSChen-Yu Tsai { .compatible = "allwinner,sun8i-r40-gmac", 13379bf5085aSChen-Yu Tsai .data = &emac_variant_r40 }, 1338a8ff8ccbSCorentin Labbe { .compatible = "allwinner,sun50i-a64-emac", 1339a8ff8ccbSCorentin Labbe .data = &emac_variant_a64 }, 1340adadd38cSIcenowy Zheng { .compatible = "allwinner,sun50i-h6-emac", 1341adadd38cSIcenowy Zheng .data = &emac_variant_h6 }, 13429f93ac8dSLABBE Corentin { } 13439f93ac8dSLABBE Corentin }; 13449f93ac8dSLABBE Corentin MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); 13459f93ac8dSLABBE Corentin 13469f93ac8dSLABBE Corentin static struct platform_driver sun8i_dwmac_driver = { 13479f93ac8dSLABBE Corentin .probe = sun8i_dwmac_probe, 1348cc708d4eSUwe Kleine-König .remove_new = sun8i_dwmac_remove, 134996be41d7SSamuel Holland .shutdown = sun8i_dwmac_shutdown, 13509f93ac8dSLABBE Corentin .driver = { 13519f93ac8dSLABBE Corentin .name = "dwmac-sun8i", 13529f93ac8dSLABBE Corentin .pm = &stmmac_pltfr_pm_ops, 13539f93ac8dSLABBE Corentin .of_match_table = sun8i_dwmac_match, 13549f93ac8dSLABBE Corentin }, 13559f93ac8dSLABBE Corentin }; 13569f93ac8dSLABBE Corentin module_platform_driver(sun8i_dwmac_driver); 13579f93ac8dSLABBE Corentin 13589f93ac8dSLABBE Corentin MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); 13599f93ac8dSLABBE Corentin MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); 13609f93ac8dSLABBE Corentin MODULE_LICENSE("GPL"); 1361