1 /** 2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 3 * 4 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 5 * 6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/stmmac.h> 20 #include <linux/bitops.h> 21 #include <linux/clk.h> 22 #include <linux/phy.h> 23 #include <linux/of_net.h> 24 #include <linux/gpio.h> 25 #include <linux/module.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/delay.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/regmap.h> 33 #include <linux/pm_runtime.h> 34 35 #include "stmmac_platform.h" 36 37 struct rk_priv_data; 38 struct rk_gmac_ops { 39 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 40 int tx_delay, int rx_delay); 41 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 42 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 43 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 44 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 }; 46 47 struct rk_priv_data { 48 struct platform_device *pdev; 49 int phy_iface; 50 struct regulator *regulator; 51 bool suspended; 52 const struct rk_gmac_ops *ops; 53 54 bool clk_enabled; 55 bool clock_input; 56 bool integrated_phy; 57 58 struct clk *clk_mac; 59 struct clk *gmac_clkin; 60 struct clk *mac_clk_rx; 61 struct clk *mac_clk_tx; 62 struct clk *clk_mac_ref; 63 struct clk *clk_mac_refout; 64 struct clk *aclk_mac; 65 struct clk *pclk_mac; 66 struct clk *clk_phy; 67 68 struct reset_control *phy_reset; 69 70 int tx_delay; 71 int rx_delay; 72 73 struct regmap *grf; 74 }; 75 76 #define HIWORD_UPDATE(val, mask, shift) \ 77 ((val) << (shift) | (mask) << ((shift) + 16)) 78 79 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 80 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 81 82 #define DELAY_ENABLE(soc, tx, rx) \ 83 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 84 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 85 86 #define RK3228_GRF_MAC_CON0 0x0900 87 #define RK3228_GRF_MAC_CON1 0x0904 88 89 #define RK3228_GRF_CON_MUX 0x50 90 91 /* RK3228_GRF_MAC_CON0 */ 92 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 93 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 94 95 /* RK3228_GRF_MAC_CON1 */ 96 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 97 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 98 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 99 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 100 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 101 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 102 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 103 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 104 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 105 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 106 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 107 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 108 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 109 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 110 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 111 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 112 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 113 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 114 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 115 116 /* RK3228_GRF_COM_MUX */ 117 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 118 119 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 120 int tx_delay, int rx_delay) 121 { 122 struct device *dev = &bsp_priv->pdev->dev; 123 124 if (IS_ERR(bsp_priv->grf)) { 125 dev_err(dev, "Missing rockchip,grf property\n"); 126 return; 127 } 128 129 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 130 RK3228_GMAC_PHY_INTF_SEL_RGMII | 131 RK3228_GMAC_RMII_MODE_CLR | 132 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 133 134 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 135 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 136 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 137 } 138 139 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 140 { 141 struct device *dev = &bsp_priv->pdev->dev; 142 143 if (IS_ERR(bsp_priv->grf)) { 144 dev_err(dev, "Missing rockchip,grf property\n"); 145 return; 146 } 147 148 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 149 RK3228_GMAC_PHY_INTF_SEL_RMII | 150 RK3228_GMAC_RMII_MODE); 151 152 /* set MAC to RMII mode */ 153 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 154 } 155 156 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 157 { 158 struct device *dev = &bsp_priv->pdev->dev; 159 160 if (IS_ERR(bsp_priv->grf)) { 161 dev_err(dev, "Missing rockchip,grf property\n"); 162 return; 163 } 164 165 if (speed == 10) 166 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 167 RK3228_GMAC_CLK_2_5M); 168 else if (speed == 100) 169 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 170 RK3228_GMAC_CLK_25M); 171 else if (speed == 1000) 172 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 173 RK3228_GMAC_CLK_125M); 174 else 175 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 176 } 177 178 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 179 { 180 struct device *dev = &bsp_priv->pdev->dev; 181 182 if (IS_ERR(bsp_priv->grf)) { 183 dev_err(dev, "Missing rockchip,grf property\n"); 184 return; 185 } 186 187 if (speed == 10) 188 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 189 RK3228_GMAC_RMII_CLK_2_5M | 190 RK3228_GMAC_SPEED_10M); 191 else if (speed == 100) 192 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 193 RK3228_GMAC_RMII_CLK_25M | 194 RK3228_GMAC_SPEED_100M); 195 else 196 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 197 } 198 199 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 200 { 201 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 202 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 203 } 204 205 static const struct rk_gmac_ops rk3228_ops = { 206 .set_to_rgmii = rk3228_set_to_rgmii, 207 .set_to_rmii = rk3228_set_to_rmii, 208 .set_rgmii_speed = rk3228_set_rgmii_speed, 209 .set_rmii_speed = rk3228_set_rmii_speed, 210 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 211 }; 212 213 #define RK3288_GRF_SOC_CON1 0x0248 214 #define RK3288_GRF_SOC_CON3 0x0250 215 216 /*RK3288_GRF_SOC_CON1*/ 217 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 218 GRF_CLR_BIT(8)) 219 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 220 GRF_BIT(8)) 221 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 222 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 223 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 224 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 225 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 226 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 227 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 228 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 229 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 230 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 231 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 232 233 /*RK3288_GRF_SOC_CON3*/ 234 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 235 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 236 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 237 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 238 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 239 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 240 241 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 242 int tx_delay, int rx_delay) 243 { 244 struct device *dev = &bsp_priv->pdev->dev; 245 246 if (IS_ERR(bsp_priv->grf)) { 247 dev_err(dev, "Missing rockchip,grf property\n"); 248 return; 249 } 250 251 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 252 RK3288_GMAC_PHY_INTF_SEL_RGMII | 253 RK3288_GMAC_RMII_MODE_CLR); 254 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 255 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 256 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 257 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 258 } 259 260 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 261 { 262 struct device *dev = &bsp_priv->pdev->dev; 263 264 if (IS_ERR(bsp_priv->grf)) { 265 dev_err(dev, "Missing rockchip,grf property\n"); 266 return; 267 } 268 269 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 270 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 271 } 272 273 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 274 { 275 struct device *dev = &bsp_priv->pdev->dev; 276 277 if (IS_ERR(bsp_priv->grf)) { 278 dev_err(dev, "Missing rockchip,grf property\n"); 279 return; 280 } 281 282 if (speed == 10) 283 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 284 RK3288_GMAC_CLK_2_5M); 285 else if (speed == 100) 286 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 287 RK3288_GMAC_CLK_25M); 288 else if (speed == 1000) 289 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 290 RK3288_GMAC_CLK_125M); 291 else 292 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 293 } 294 295 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 296 { 297 struct device *dev = &bsp_priv->pdev->dev; 298 299 if (IS_ERR(bsp_priv->grf)) { 300 dev_err(dev, "Missing rockchip,grf property\n"); 301 return; 302 } 303 304 if (speed == 10) { 305 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 306 RK3288_GMAC_RMII_CLK_2_5M | 307 RK3288_GMAC_SPEED_10M); 308 } else if (speed == 100) { 309 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 310 RK3288_GMAC_RMII_CLK_25M | 311 RK3288_GMAC_SPEED_100M); 312 } else { 313 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 314 } 315 } 316 317 static const struct rk_gmac_ops rk3288_ops = { 318 .set_to_rgmii = rk3288_set_to_rgmii, 319 .set_to_rmii = rk3288_set_to_rmii, 320 .set_rgmii_speed = rk3288_set_rgmii_speed, 321 .set_rmii_speed = rk3288_set_rmii_speed, 322 }; 323 324 #define RK3328_GRF_MAC_CON0 0x0900 325 #define RK3328_GRF_MAC_CON1 0x0904 326 #define RK3328_GRF_MAC_CON2 0x0908 327 #define RK3328_GRF_MACPHY_CON1 0xb04 328 329 /* RK3328_GRF_MAC_CON0 */ 330 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 331 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 332 333 /* RK3328_GRF_MAC_CON1 */ 334 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 335 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 336 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 337 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 338 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 339 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 340 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 341 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 342 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 343 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 344 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 345 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 346 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 347 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 348 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 349 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 350 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 351 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 352 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 353 354 /* RK3328_GRF_MACPHY_CON1 */ 355 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 356 357 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 358 int tx_delay, int rx_delay) 359 { 360 struct device *dev = &bsp_priv->pdev->dev; 361 362 if (IS_ERR(bsp_priv->grf)) { 363 dev_err(dev, "Missing rockchip,grf property\n"); 364 return; 365 } 366 367 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 368 RK3328_GMAC_PHY_INTF_SEL_RGMII | 369 RK3328_GMAC_RMII_MODE_CLR | 370 RK3328_GMAC_RXCLK_DLY_ENABLE | 371 RK3328_GMAC_TXCLK_DLY_ENABLE); 372 373 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 374 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 375 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 376 } 377 378 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 379 { 380 struct device *dev = &bsp_priv->pdev->dev; 381 unsigned int reg; 382 383 if (IS_ERR(bsp_priv->grf)) { 384 dev_err(dev, "Missing rockchip,grf property\n"); 385 return; 386 } 387 388 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 389 RK3328_GRF_MAC_CON1; 390 391 regmap_write(bsp_priv->grf, reg, 392 RK3328_GMAC_PHY_INTF_SEL_RMII | 393 RK3328_GMAC_RMII_MODE); 394 } 395 396 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 397 { 398 struct device *dev = &bsp_priv->pdev->dev; 399 400 if (IS_ERR(bsp_priv->grf)) { 401 dev_err(dev, "Missing rockchip,grf property\n"); 402 return; 403 } 404 405 if (speed == 10) 406 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 407 RK3328_GMAC_CLK_2_5M); 408 else if (speed == 100) 409 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 410 RK3328_GMAC_CLK_25M); 411 else if (speed == 1000) 412 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 413 RK3328_GMAC_CLK_125M); 414 else 415 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 416 } 417 418 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 419 { 420 struct device *dev = &bsp_priv->pdev->dev; 421 unsigned int reg; 422 423 if (IS_ERR(bsp_priv->grf)) { 424 dev_err(dev, "Missing rockchip,grf property\n"); 425 return; 426 } 427 428 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 429 RK3328_GRF_MAC_CON1; 430 431 if (speed == 10) 432 regmap_write(bsp_priv->grf, reg, 433 RK3328_GMAC_RMII_CLK_2_5M | 434 RK3328_GMAC_SPEED_10M); 435 else if (speed == 100) 436 regmap_write(bsp_priv->grf, reg, 437 RK3328_GMAC_RMII_CLK_25M | 438 RK3328_GMAC_SPEED_100M); 439 else 440 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 441 } 442 443 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 444 { 445 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 446 RK3328_MACPHY_RMII_MODE); 447 } 448 449 static const struct rk_gmac_ops rk3328_ops = { 450 .set_to_rgmii = rk3328_set_to_rgmii, 451 .set_to_rmii = rk3328_set_to_rmii, 452 .set_rgmii_speed = rk3328_set_rgmii_speed, 453 .set_rmii_speed = rk3328_set_rmii_speed, 454 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 455 }; 456 457 #define RK3366_GRF_SOC_CON6 0x0418 458 #define RK3366_GRF_SOC_CON7 0x041c 459 460 /* RK3366_GRF_SOC_CON6 */ 461 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 462 GRF_CLR_BIT(11)) 463 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 464 GRF_BIT(11)) 465 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 466 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 467 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 468 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 469 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 470 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 471 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 472 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 473 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 474 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 475 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 476 477 /* RK3366_GRF_SOC_CON7 */ 478 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 479 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 480 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 481 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 482 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 483 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 484 485 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 486 int tx_delay, int rx_delay) 487 { 488 struct device *dev = &bsp_priv->pdev->dev; 489 490 if (IS_ERR(bsp_priv->grf)) { 491 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 492 return; 493 } 494 495 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 496 RK3366_GMAC_PHY_INTF_SEL_RGMII | 497 RK3366_GMAC_RMII_MODE_CLR); 498 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 499 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 500 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 501 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 502 } 503 504 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 505 { 506 struct device *dev = &bsp_priv->pdev->dev; 507 508 if (IS_ERR(bsp_priv->grf)) { 509 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 510 return; 511 } 512 513 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 514 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 515 } 516 517 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 518 { 519 struct device *dev = &bsp_priv->pdev->dev; 520 521 if (IS_ERR(bsp_priv->grf)) { 522 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 523 return; 524 } 525 526 if (speed == 10) 527 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 528 RK3366_GMAC_CLK_2_5M); 529 else if (speed == 100) 530 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 531 RK3366_GMAC_CLK_25M); 532 else if (speed == 1000) 533 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 534 RK3366_GMAC_CLK_125M); 535 else 536 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 537 } 538 539 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 540 { 541 struct device *dev = &bsp_priv->pdev->dev; 542 543 if (IS_ERR(bsp_priv->grf)) { 544 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 545 return; 546 } 547 548 if (speed == 10) { 549 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 550 RK3366_GMAC_RMII_CLK_2_5M | 551 RK3366_GMAC_SPEED_10M); 552 } else if (speed == 100) { 553 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 554 RK3366_GMAC_RMII_CLK_25M | 555 RK3366_GMAC_SPEED_100M); 556 } else { 557 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 558 } 559 } 560 561 static const struct rk_gmac_ops rk3366_ops = { 562 .set_to_rgmii = rk3366_set_to_rgmii, 563 .set_to_rmii = rk3366_set_to_rmii, 564 .set_rgmii_speed = rk3366_set_rgmii_speed, 565 .set_rmii_speed = rk3366_set_rmii_speed, 566 }; 567 568 #define RK3368_GRF_SOC_CON15 0x043c 569 #define RK3368_GRF_SOC_CON16 0x0440 570 571 /* RK3368_GRF_SOC_CON15 */ 572 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 573 GRF_CLR_BIT(11)) 574 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 575 GRF_BIT(11)) 576 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 577 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 578 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 579 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 580 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 581 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 582 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 583 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 584 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 585 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 586 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 587 588 /* RK3368_GRF_SOC_CON16 */ 589 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 590 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 591 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 592 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 593 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 594 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 595 596 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 597 int tx_delay, int rx_delay) 598 { 599 struct device *dev = &bsp_priv->pdev->dev; 600 601 if (IS_ERR(bsp_priv->grf)) { 602 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 603 return; 604 } 605 606 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 607 RK3368_GMAC_PHY_INTF_SEL_RGMII | 608 RK3368_GMAC_RMII_MODE_CLR); 609 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 610 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 611 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 612 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 613 } 614 615 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 616 { 617 struct device *dev = &bsp_priv->pdev->dev; 618 619 if (IS_ERR(bsp_priv->grf)) { 620 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 621 return; 622 } 623 624 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 625 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 626 } 627 628 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 629 { 630 struct device *dev = &bsp_priv->pdev->dev; 631 632 if (IS_ERR(bsp_priv->grf)) { 633 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 634 return; 635 } 636 637 if (speed == 10) 638 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 639 RK3368_GMAC_CLK_2_5M); 640 else if (speed == 100) 641 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 642 RK3368_GMAC_CLK_25M); 643 else if (speed == 1000) 644 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 645 RK3368_GMAC_CLK_125M); 646 else 647 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 648 } 649 650 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 651 { 652 struct device *dev = &bsp_priv->pdev->dev; 653 654 if (IS_ERR(bsp_priv->grf)) { 655 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 656 return; 657 } 658 659 if (speed == 10) { 660 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 661 RK3368_GMAC_RMII_CLK_2_5M | 662 RK3368_GMAC_SPEED_10M); 663 } else if (speed == 100) { 664 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 665 RK3368_GMAC_RMII_CLK_25M | 666 RK3368_GMAC_SPEED_100M); 667 } else { 668 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 669 } 670 } 671 672 static const struct rk_gmac_ops rk3368_ops = { 673 .set_to_rgmii = rk3368_set_to_rgmii, 674 .set_to_rmii = rk3368_set_to_rmii, 675 .set_rgmii_speed = rk3368_set_rgmii_speed, 676 .set_rmii_speed = rk3368_set_rmii_speed, 677 }; 678 679 #define RK3399_GRF_SOC_CON5 0xc214 680 #define RK3399_GRF_SOC_CON6 0xc218 681 682 /* RK3399_GRF_SOC_CON5 */ 683 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 684 GRF_CLR_BIT(11)) 685 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 686 GRF_BIT(11)) 687 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 688 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 689 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 690 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 691 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 692 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 693 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 694 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 695 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 696 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 697 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 698 699 /* RK3399_GRF_SOC_CON6 */ 700 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 701 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 702 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 703 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 704 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 705 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 706 707 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 708 int tx_delay, int rx_delay) 709 { 710 struct device *dev = &bsp_priv->pdev->dev; 711 712 if (IS_ERR(bsp_priv->grf)) { 713 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 714 return; 715 } 716 717 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 718 RK3399_GMAC_PHY_INTF_SEL_RGMII | 719 RK3399_GMAC_RMII_MODE_CLR); 720 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 721 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 722 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 723 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 724 } 725 726 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 727 { 728 struct device *dev = &bsp_priv->pdev->dev; 729 730 if (IS_ERR(bsp_priv->grf)) { 731 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 732 return; 733 } 734 735 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 736 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 737 } 738 739 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 740 { 741 struct device *dev = &bsp_priv->pdev->dev; 742 743 if (IS_ERR(bsp_priv->grf)) { 744 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 745 return; 746 } 747 748 if (speed == 10) 749 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 750 RK3399_GMAC_CLK_2_5M); 751 else if (speed == 100) 752 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 753 RK3399_GMAC_CLK_25M); 754 else if (speed == 1000) 755 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 756 RK3399_GMAC_CLK_125M); 757 else 758 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 759 } 760 761 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 762 { 763 struct device *dev = &bsp_priv->pdev->dev; 764 765 if (IS_ERR(bsp_priv->grf)) { 766 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 767 return; 768 } 769 770 if (speed == 10) { 771 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 772 RK3399_GMAC_RMII_CLK_2_5M | 773 RK3399_GMAC_SPEED_10M); 774 } else if (speed == 100) { 775 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 776 RK3399_GMAC_RMII_CLK_25M | 777 RK3399_GMAC_SPEED_100M); 778 } else { 779 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 780 } 781 } 782 783 static const struct rk_gmac_ops rk3399_ops = { 784 .set_to_rgmii = rk3399_set_to_rgmii, 785 .set_to_rmii = rk3399_set_to_rmii, 786 .set_rgmii_speed = rk3399_set_rgmii_speed, 787 .set_rmii_speed = rk3399_set_rmii_speed, 788 }; 789 790 #define RV1108_GRF_GMAC_CON0 0X0900 791 792 /* RV1108_GRF_GMAC_CON0 */ 793 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 794 GRF_BIT(6)) 795 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 796 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 797 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 798 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 799 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 800 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 801 802 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 803 { 804 struct device *dev = &bsp_priv->pdev->dev; 805 806 if (IS_ERR(bsp_priv->grf)) { 807 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 808 return; 809 } 810 811 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 812 RV1108_GMAC_PHY_INTF_SEL_RMII); 813 } 814 815 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 816 { 817 struct device *dev = &bsp_priv->pdev->dev; 818 819 if (IS_ERR(bsp_priv->grf)) { 820 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 821 return; 822 } 823 824 if (speed == 10) { 825 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 826 RV1108_GMAC_RMII_CLK_2_5M | 827 RV1108_GMAC_SPEED_10M); 828 } else if (speed == 100) { 829 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 830 RV1108_GMAC_RMII_CLK_25M | 831 RV1108_GMAC_SPEED_100M); 832 } else { 833 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 834 } 835 } 836 837 static const struct rk_gmac_ops rv1108_ops = { 838 .set_to_rmii = rv1108_set_to_rmii, 839 .set_rmii_speed = rv1108_set_rmii_speed, 840 }; 841 842 #define RK_GRF_MACPHY_CON0 0xb00 843 #define RK_GRF_MACPHY_CON1 0xb04 844 #define RK_GRF_MACPHY_CON2 0xb08 845 #define RK_GRF_MACPHY_CON3 0xb0c 846 847 #define RK_MACPHY_ENABLE GRF_BIT(0) 848 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 849 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 850 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 851 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 852 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 853 854 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) 855 { 856 if (priv->ops->integrated_phy_powerup) 857 priv->ops->integrated_phy_powerup(priv); 858 859 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 860 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 861 862 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 863 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 864 865 if (priv->phy_reset) { 866 /* PHY needs to be disabled before trying to reset it */ 867 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 868 if (priv->phy_reset) 869 reset_control_assert(priv->phy_reset); 870 usleep_range(10, 20); 871 if (priv->phy_reset) 872 reset_control_deassert(priv->phy_reset); 873 usleep_range(10, 20); 874 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 875 msleep(30); 876 } 877 } 878 879 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) 880 { 881 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 882 if (priv->phy_reset) 883 reset_control_assert(priv->phy_reset); 884 } 885 886 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 887 { 888 struct rk_priv_data *bsp_priv = plat->bsp_priv; 889 struct device *dev = &bsp_priv->pdev->dev; 890 int ret; 891 892 bsp_priv->clk_enabled = false; 893 894 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); 895 if (IS_ERR(bsp_priv->mac_clk_rx)) 896 dev_err(dev, "cannot get clock %s\n", 897 "mac_clk_rx"); 898 899 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); 900 if (IS_ERR(bsp_priv->mac_clk_tx)) 901 dev_err(dev, "cannot get clock %s\n", 902 "mac_clk_tx"); 903 904 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); 905 if (IS_ERR(bsp_priv->aclk_mac)) 906 dev_err(dev, "cannot get clock %s\n", 907 "aclk_mac"); 908 909 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); 910 if (IS_ERR(bsp_priv->pclk_mac)) 911 dev_err(dev, "cannot get clock %s\n", 912 "pclk_mac"); 913 914 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 915 if (IS_ERR(bsp_priv->clk_mac)) 916 dev_err(dev, "cannot get clock %s\n", 917 "stmmaceth"); 918 919 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 920 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); 921 if (IS_ERR(bsp_priv->clk_mac_ref)) 922 dev_err(dev, "cannot get clock %s\n", 923 "clk_mac_ref"); 924 925 if (!bsp_priv->clock_input) { 926 bsp_priv->clk_mac_refout = 927 devm_clk_get(dev, "clk_mac_refout"); 928 if (IS_ERR(bsp_priv->clk_mac_refout)) 929 dev_err(dev, "cannot get clock %s\n", 930 "clk_mac_refout"); 931 } 932 } 933 934 if (bsp_priv->clock_input) { 935 dev_info(dev, "clock input from PHY\n"); 936 } else { 937 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 938 clk_set_rate(bsp_priv->clk_mac, 50000000); 939 } 940 941 if (plat->phy_node && bsp_priv->integrated_phy) { 942 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 943 if (IS_ERR(bsp_priv->clk_phy)) { 944 ret = PTR_ERR(bsp_priv->clk_phy); 945 dev_err(dev, "Cannot get PHY clock: %d\n", ret); 946 return -EINVAL; 947 } 948 clk_set_rate(bsp_priv->clk_phy, 50000000); 949 } 950 951 return 0; 952 } 953 954 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 955 { 956 int phy_iface = bsp_priv->phy_iface; 957 958 if (enable) { 959 if (!bsp_priv->clk_enabled) { 960 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 961 if (!IS_ERR(bsp_priv->mac_clk_rx)) 962 clk_prepare_enable( 963 bsp_priv->mac_clk_rx); 964 965 if (!IS_ERR(bsp_priv->clk_mac_ref)) 966 clk_prepare_enable( 967 bsp_priv->clk_mac_ref); 968 969 if (!IS_ERR(bsp_priv->clk_mac_refout)) 970 clk_prepare_enable( 971 bsp_priv->clk_mac_refout); 972 } 973 974 if (!IS_ERR(bsp_priv->clk_phy)) 975 clk_prepare_enable(bsp_priv->clk_phy); 976 977 if (!IS_ERR(bsp_priv->aclk_mac)) 978 clk_prepare_enable(bsp_priv->aclk_mac); 979 980 if (!IS_ERR(bsp_priv->pclk_mac)) 981 clk_prepare_enable(bsp_priv->pclk_mac); 982 983 if (!IS_ERR(bsp_priv->mac_clk_tx)) 984 clk_prepare_enable(bsp_priv->mac_clk_tx); 985 986 /** 987 * if (!IS_ERR(bsp_priv->clk_mac)) 988 * clk_prepare_enable(bsp_priv->clk_mac); 989 */ 990 mdelay(5); 991 bsp_priv->clk_enabled = true; 992 } 993 } else { 994 if (bsp_priv->clk_enabled) { 995 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 996 if (!IS_ERR(bsp_priv->mac_clk_rx)) 997 clk_disable_unprepare( 998 bsp_priv->mac_clk_rx); 999 1000 if (!IS_ERR(bsp_priv->clk_mac_ref)) 1001 clk_disable_unprepare( 1002 bsp_priv->clk_mac_ref); 1003 1004 if (!IS_ERR(bsp_priv->clk_mac_refout)) 1005 clk_disable_unprepare( 1006 bsp_priv->clk_mac_refout); 1007 } 1008 1009 if (!IS_ERR(bsp_priv->clk_phy)) 1010 clk_disable_unprepare(bsp_priv->clk_phy); 1011 1012 if (!IS_ERR(bsp_priv->aclk_mac)) 1013 clk_disable_unprepare(bsp_priv->aclk_mac); 1014 1015 if (!IS_ERR(bsp_priv->pclk_mac)) 1016 clk_disable_unprepare(bsp_priv->pclk_mac); 1017 1018 if (!IS_ERR(bsp_priv->mac_clk_tx)) 1019 clk_disable_unprepare(bsp_priv->mac_clk_tx); 1020 /** 1021 * if (!IS_ERR(bsp_priv->clk_mac)) 1022 * clk_disable_unprepare(bsp_priv->clk_mac); 1023 */ 1024 bsp_priv->clk_enabled = false; 1025 } 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1032 { 1033 struct regulator *ldo = bsp_priv->regulator; 1034 int ret; 1035 struct device *dev = &bsp_priv->pdev->dev; 1036 1037 if (!ldo) { 1038 dev_err(dev, "no regulator found\n"); 1039 return -1; 1040 } 1041 1042 if (enable) { 1043 ret = regulator_enable(ldo); 1044 if (ret) 1045 dev_err(dev, "fail to enable phy-supply\n"); 1046 } else { 1047 ret = regulator_disable(ldo); 1048 if (ret) 1049 dev_err(dev, "fail to disable phy-supply\n"); 1050 } 1051 1052 return 0; 1053 } 1054 1055 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1056 struct plat_stmmacenet_data *plat, 1057 const struct rk_gmac_ops *ops) 1058 { 1059 struct rk_priv_data *bsp_priv; 1060 struct device *dev = &pdev->dev; 1061 int ret; 1062 const char *strings = NULL; 1063 int value; 1064 1065 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1066 if (!bsp_priv) 1067 return ERR_PTR(-ENOMEM); 1068 1069 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); 1070 bsp_priv->ops = ops; 1071 1072 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); 1073 if (IS_ERR(bsp_priv->regulator)) { 1074 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { 1075 dev_err(dev, "phy regulator is not available yet, deferred probing\n"); 1076 return ERR_PTR(-EPROBE_DEFER); 1077 } 1078 dev_err(dev, "no regulator found\n"); 1079 bsp_priv->regulator = NULL; 1080 } 1081 1082 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1083 if (ret) { 1084 dev_err(dev, "Can not read property: clock_in_out.\n"); 1085 bsp_priv->clock_input = true; 1086 } else { 1087 dev_info(dev, "clock input or output? (%s).\n", 1088 strings); 1089 if (!strcmp(strings, "input")) 1090 bsp_priv->clock_input = true; 1091 else 1092 bsp_priv->clock_input = false; 1093 } 1094 1095 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1096 if (ret) { 1097 bsp_priv->tx_delay = 0x30; 1098 dev_err(dev, "Can not read property: tx_delay."); 1099 dev_err(dev, "set tx_delay to 0x%x\n", 1100 bsp_priv->tx_delay); 1101 } else { 1102 dev_info(dev, "TX delay(0x%x).\n", value); 1103 bsp_priv->tx_delay = value; 1104 } 1105 1106 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1107 if (ret) { 1108 bsp_priv->rx_delay = 0x10; 1109 dev_err(dev, "Can not read property: rx_delay."); 1110 dev_err(dev, "set rx_delay to 0x%x\n", 1111 bsp_priv->rx_delay); 1112 } else { 1113 dev_info(dev, "RX delay(0x%x).\n", value); 1114 bsp_priv->rx_delay = value; 1115 } 1116 1117 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1118 "rockchip,grf"); 1119 1120 if (plat->phy_node) { 1121 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1122 "phy-is-integrated"); 1123 if (bsp_priv->integrated_phy) { 1124 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1125 if (IS_ERR(bsp_priv->phy_reset)) { 1126 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1127 bsp_priv->phy_reset = NULL; 1128 } 1129 } 1130 } 1131 dev_info(dev, "integrated PHY? (%s).\n", 1132 bsp_priv->integrated_phy ? "yes" : "no"); 1133 1134 bsp_priv->pdev = pdev; 1135 1136 return bsp_priv; 1137 } 1138 1139 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1140 { 1141 int ret; 1142 struct device *dev = &bsp_priv->pdev->dev; 1143 1144 ret = gmac_clk_enable(bsp_priv, true); 1145 if (ret) 1146 return ret; 1147 1148 /*rmii or rgmii*/ 1149 switch (bsp_priv->phy_iface) { 1150 case PHY_INTERFACE_MODE_RGMII: 1151 dev_info(dev, "init for RGMII\n"); 1152 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1153 bsp_priv->rx_delay); 1154 break; 1155 case PHY_INTERFACE_MODE_RGMII_ID: 1156 dev_info(dev, "init for RGMII_ID\n"); 1157 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1158 break; 1159 case PHY_INTERFACE_MODE_RGMII_RXID: 1160 dev_info(dev, "init for RGMII_RXID\n"); 1161 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1162 break; 1163 case PHY_INTERFACE_MODE_RGMII_TXID: 1164 dev_info(dev, "init for RGMII_TXID\n"); 1165 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1166 break; 1167 case PHY_INTERFACE_MODE_RMII: 1168 dev_info(dev, "init for RMII\n"); 1169 bsp_priv->ops->set_to_rmii(bsp_priv); 1170 break; 1171 default: 1172 dev_err(dev, "NO interface defined!\n"); 1173 } 1174 1175 ret = phy_power_on(bsp_priv, true); 1176 if (ret) 1177 return ret; 1178 1179 pm_runtime_enable(dev); 1180 pm_runtime_get_sync(dev); 1181 1182 if (bsp_priv->integrated_phy) 1183 rk_gmac_integrated_phy_powerup(bsp_priv); 1184 1185 return 0; 1186 } 1187 1188 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1189 { 1190 struct device *dev = &gmac->pdev->dev; 1191 1192 if (gmac->integrated_phy) 1193 rk_gmac_integrated_phy_powerdown(gmac); 1194 1195 pm_runtime_put_sync(dev); 1196 pm_runtime_disable(dev); 1197 1198 phy_power_on(gmac, false); 1199 gmac_clk_enable(gmac, false); 1200 } 1201 1202 static void rk_fix_speed(void *priv, unsigned int speed) 1203 { 1204 struct rk_priv_data *bsp_priv = priv; 1205 struct device *dev = &bsp_priv->pdev->dev; 1206 1207 switch (bsp_priv->phy_iface) { 1208 case PHY_INTERFACE_MODE_RGMII: 1209 case PHY_INTERFACE_MODE_RGMII_ID: 1210 case PHY_INTERFACE_MODE_RGMII_RXID: 1211 case PHY_INTERFACE_MODE_RGMII_TXID: 1212 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 1213 break; 1214 case PHY_INTERFACE_MODE_RMII: 1215 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 1216 break; 1217 default: 1218 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 1219 } 1220 } 1221 1222 static int rk_gmac_probe(struct platform_device *pdev) 1223 { 1224 struct plat_stmmacenet_data *plat_dat; 1225 struct stmmac_resources stmmac_res; 1226 const struct rk_gmac_ops *data; 1227 int ret; 1228 1229 data = of_device_get_match_data(&pdev->dev); 1230 if (!data) { 1231 dev_err(&pdev->dev, "no of match data provided\n"); 1232 return -EINVAL; 1233 } 1234 1235 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1236 if (ret) 1237 return ret; 1238 1239 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1240 if (IS_ERR(plat_dat)) 1241 return PTR_ERR(plat_dat); 1242 1243 plat_dat->has_gmac = true; 1244 plat_dat->fix_mac_speed = rk_fix_speed; 1245 1246 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1247 if (IS_ERR(plat_dat->bsp_priv)) { 1248 ret = PTR_ERR(plat_dat->bsp_priv); 1249 goto err_remove_config_dt; 1250 } 1251 1252 ret = rk_gmac_clk_init(plat_dat); 1253 if (ret) 1254 return ret; 1255 1256 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1257 if (ret) 1258 goto err_remove_config_dt; 1259 1260 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1261 if (ret) 1262 goto err_gmac_powerdown; 1263 1264 return 0; 1265 1266 err_gmac_powerdown: 1267 rk_gmac_powerdown(plat_dat->bsp_priv); 1268 err_remove_config_dt: 1269 stmmac_remove_config_dt(pdev, plat_dat); 1270 1271 return ret; 1272 } 1273 1274 static int rk_gmac_remove(struct platform_device *pdev) 1275 { 1276 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 1277 int ret = stmmac_dvr_remove(&pdev->dev); 1278 1279 rk_gmac_powerdown(bsp_priv); 1280 1281 return ret; 1282 } 1283 1284 #ifdef CONFIG_PM_SLEEP 1285 static int rk_gmac_suspend(struct device *dev) 1286 { 1287 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1288 int ret = stmmac_suspend(dev); 1289 1290 /* Keep the PHY up if we use Wake-on-Lan. */ 1291 if (!device_may_wakeup(dev)) { 1292 rk_gmac_powerdown(bsp_priv); 1293 bsp_priv->suspended = true; 1294 } 1295 1296 return ret; 1297 } 1298 1299 static int rk_gmac_resume(struct device *dev) 1300 { 1301 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1302 1303 /* The PHY was up for Wake-on-Lan. */ 1304 if (bsp_priv->suspended) { 1305 rk_gmac_powerup(bsp_priv); 1306 bsp_priv->suspended = false; 1307 } 1308 1309 return stmmac_resume(dev); 1310 } 1311 #endif /* CONFIG_PM_SLEEP */ 1312 1313 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1314 1315 static const struct of_device_id rk_gmac_dwmac_match[] = { 1316 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1317 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1318 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1319 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1320 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1321 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1322 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1323 { } 1324 }; 1325 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1326 1327 static struct platform_driver rk_gmac_dwmac_driver = { 1328 .probe = rk_gmac_probe, 1329 .remove = rk_gmac_remove, 1330 .driver = { 1331 .name = "rk_gmac-dwmac", 1332 .pm = &rk_gmac_pm_ops, 1333 .of_match_table = rk_gmac_dwmac_match, 1334 }, 1335 }; 1336 module_platform_driver(rk_gmac_dwmac_driver); 1337 1338 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1339 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1340 MODULE_LICENSE("GPL"); 1341