1 /** 2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 3 * 4 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 5 * 6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/stmmac.h> 20 #include <linux/bitops.h> 21 #include <linux/clk.h> 22 #include <linux/phy.h> 23 #include <linux/of_net.h> 24 #include <linux/gpio.h> 25 #include <linux/module.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/delay.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/regmap.h> 33 #include <linux/pm_runtime.h> 34 35 #include "stmmac_platform.h" 36 37 struct rk_priv_data; 38 struct rk_gmac_ops { 39 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 40 int tx_delay, int rx_delay); 41 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 42 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 43 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 44 }; 45 46 struct rk_priv_data { 47 struct platform_device *pdev; 48 int phy_iface; 49 struct regulator *regulator; 50 bool suspended; 51 const struct rk_gmac_ops *ops; 52 53 bool clk_enabled; 54 bool clock_input; 55 56 struct clk *clk_mac; 57 struct clk *gmac_clkin; 58 struct clk *mac_clk_rx; 59 struct clk *mac_clk_tx; 60 struct clk *clk_mac_ref; 61 struct clk *clk_mac_refout; 62 struct clk *aclk_mac; 63 struct clk *pclk_mac; 64 65 int tx_delay; 66 int rx_delay; 67 68 struct regmap *grf; 69 }; 70 71 #define HIWORD_UPDATE(val, mask, shift) \ 72 ((val) << (shift) | (mask) << ((shift) + 16)) 73 74 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 75 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 76 77 #define RK3228_GRF_MAC_CON0 0x0900 78 #define RK3228_GRF_MAC_CON1 0x0904 79 80 /* RK3228_GRF_MAC_CON0 */ 81 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 82 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 83 84 /* RK3228_GRF_MAC_CON1 */ 85 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 86 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 87 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 88 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 89 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 90 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 91 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 92 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 93 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 94 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 95 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 96 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 97 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 98 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 99 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 100 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 101 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 102 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 103 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 104 105 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 106 int tx_delay, int rx_delay) 107 { 108 struct device *dev = &bsp_priv->pdev->dev; 109 110 if (IS_ERR(bsp_priv->grf)) { 111 dev_err(dev, "Missing rockchip,grf property\n"); 112 return; 113 } 114 115 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 116 RK3228_GMAC_PHY_INTF_SEL_RGMII | 117 RK3228_GMAC_RMII_MODE_CLR | 118 RK3228_GMAC_RXCLK_DLY_ENABLE | 119 RK3228_GMAC_TXCLK_DLY_ENABLE); 120 121 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 122 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 123 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 124 } 125 126 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 127 { 128 struct device *dev = &bsp_priv->pdev->dev; 129 130 if (IS_ERR(bsp_priv->grf)) { 131 dev_err(dev, "Missing rockchip,grf property\n"); 132 return; 133 } 134 135 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 136 RK3228_GMAC_PHY_INTF_SEL_RMII | 137 RK3228_GMAC_RMII_MODE); 138 139 /* set MAC to RMII mode */ 140 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 141 } 142 143 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 144 { 145 struct device *dev = &bsp_priv->pdev->dev; 146 147 if (IS_ERR(bsp_priv->grf)) { 148 dev_err(dev, "Missing rockchip,grf property\n"); 149 return; 150 } 151 152 if (speed == 10) 153 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 154 RK3228_GMAC_CLK_2_5M); 155 else if (speed == 100) 156 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 157 RK3228_GMAC_CLK_25M); 158 else if (speed == 1000) 159 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 160 RK3228_GMAC_CLK_125M); 161 else 162 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 163 } 164 165 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 166 { 167 struct device *dev = &bsp_priv->pdev->dev; 168 169 if (IS_ERR(bsp_priv->grf)) { 170 dev_err(dev, "Missing rockchip,grf property\n"); 171 return; 172 } 173 174 if (speed == 10) 175 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 176 RK3228_GMAC_RMII_CLK_2_5M | 177 RK3228_GMAC_SPEED_10M); 178 else if (speed == 100) 179 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 180 RK3228_GMAC_RMII_CLK_25M | 181 RK3228_GMAC_SPEED_100M); 182 else 183 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 184 } 185 186 static const struct rk_gmac_ops rk3228_ops = { 187 .set_to_rgmii = rk3228_set_to_rgmii, 188 .set_to_rmii = rk3228_set_to_rmii, 189 .set_rgmii_speed = rk3228_set_rgmii_speed, 190 .set_rmii_speed = rk3228_set_rmii_speed, 191 }; 192 193 #define RK3288_GRF_SOC_CON1 0x0248 194 #define RK3288_GRF_SOC_CON3 0x0250 195 196 /*RK3288_GRF_SOC_CON1*/ 197 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 198 GRF_CLR_BIT(8)) 199 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 200 GRF_BIT(8)) 201 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 202 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 203 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 204 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 205 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 206 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 207 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 208 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 209 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 210 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 211 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 212 213 /*RK3288_GRF_SOC_CON3*/ 214 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 215 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 216 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 217 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 218 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 219 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 220 221 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 222 int tx_delay, int rx_delay) 223 { 224 struct device *dev = &bsp_priv->pdev->dev; 225 226 if (IS_ERR(bsp_priv->grf)) { 227 dev_err(dev, "Missing rockchip,grf property\n"); 228 return; 229 } 230 231 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 232 RK3288_GMAC_PHY_INTF_SEL_RGMII | 233 RK3288_GMAC_RMII_MODE_CLR); 234 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 235 RK3288_GMAC_RXCLK_DLY_ENABLE | 236 RK3288_GMAC_TXCLK_DLY_ENABLE | 237 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 238 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 239 } 240 241 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 242 { 243 struct device *dev = &bsp_priv->pdev->dev; 244 245 if (IS_ERR(bsp_priv->grf)) { 246 dev_err(dev, "Missing rockchip,grf property\n"); 247 return; 248 } 249 250 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 251 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 252 } 253 254 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 255 { 256 struct device *dev = &bsp_priv->pdev->dev; 257 258 if (IS_ERR(bsp_priv->grf)) { 259 dev_err(dev, "Missing rockchip,grf property\n"); 260 return; 261 } 262 263 if (speed == 10) 264 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 265 RK3288_GMAC_CLK_2_5M); 266 else if (speed == 100) 267 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 268 RK3288_GMAC_CLK_25M); 269 else if (speed == 1000) 270 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 271 RK3288_GMAC_CLK_125M); 272 else 273 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 274 } 275 276 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 277 { 278 struct device *dev = &bsp_priv->pdev->dev; 279 280 if (IS_ERR(bsp_priv->grf)) { 281 dev_err(dev, "Missing rockchip,grf property\n"); 282 return; 283 } 284 285 if (speed == 10) { 286 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 287 RK3288_GMAC_RMII_CLK_2_5M | 288 RK3288_GMAC_SPEED_10M); 289 } else if (speed == 100) { 290 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 291 RK3288_GMAC_RMII_CLK_25M | 292 RK3288_GMAC_SPEED_100M); 293 } else { 294 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 295 } 296 } 297 298 static const struct rk_gmac_ops rk3288_ops = { 299 .set_to_rgmii = rk3288_set_to_rgmii, 300 .set_to_rmii = rk3288_set_to_rmii, 301 .set_rgmii_speed = rk3288_set_rgmii_speed, 302 .set_rmii_speed = rk3288_set_rmii_speed, 303 }; 304 305 #define RK3366_GRF_SOC_CON6 0x0418 306 #define RK3366_GRF_SOC_CON7 0x041c 307 308 /* RK3366_GRF_SOC_CON6 */ 309 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 310 GRF_CLR_BIT(11)) 311 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 312 GRF_BIT(11)) 313 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 314 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 315 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 316 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 317 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 318 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 319 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 320 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 321 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 322 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 323 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 324 325 /* RK3366_GRF_SOC_CON7 */ 326 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 327 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 328 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 329 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 330 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 331 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 332 333 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 334 int tx_delay, int rx_delay) 335 { 336 struct device *dev = &bsp_priv->pdev->dev; 337 338 if (IS_ERR(bsp_priv->grf)) { 339 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 340 return; 341 } 342 343 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 344 RK3366_GMAC_PHY_INTF_SEL_RGMII | 345 RK3366_GMAC_RMII_MODE_CLR); 346 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 347 RK3366_GMAC_RXCLK_DLY_ENABLE | 348 RK3366_GMAC_TXCLK_DLY_ENABLE | 349 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 350 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 351 } 352 353 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 354 { 355 struct device *dev = &bsp_priv->pdev->dev; 356 357 if (IS_ERR(bsp_priv->grf)) { 358 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 359 return; 360 } 361 362 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 363 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 364 } 365 366 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 367 { 368 struct device *dev = &bsp_priv->pdev->dev; 369 370 if (IS_ERR(bsp_priv->grf)) { 371 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 372 return; 373 } 374 375 if (speed == 10) 376 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 377 RK3366_GMAC_CLK_2_5M); 378 else if (speed == 100) 379 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 380 RK3366_GMAC_CLK_25M); 381 else if (speed == 1000) 382 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 383 RK3366_GMAC_CLK_125M); 384 else 385 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 386 } 387 388 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 389 { 390 struct device *dev = &bsp_priv->pdev->dev; 391 392 if (IS_ERR(bsp_priv->grf)) { 393 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 394 return; 395 } 396 397 if (speed == 10) { 398 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 399 RK3366_GMAC_RMII_CLK_2_5M | 400 RK3366_GMAC_SPEED_10M); 401 } else if (speed == 100) { 402 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 403 RK3366_GMAC_RMII_CLK_25M | 404 RK3366_GMAC_SPEED_100M); 405 } else { 406 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 407 } 408 } 409 410 static const struct rk_gmac_ops rk3366_ops = { 411 .set_to_rgmii = rk3366_set_to_rgmii, 412 .set_to_rmii = rk3366_set_to_rmii, 413 .set_rgmii_speed = rk3366_set_rgmii_speed, 414 .set_rmii_speed = rk3366_set_rmii_speed, 415 }; 416 417 #define RK3368_GRF_SOC_CON15 0x043c 418 #define RK3368_GRF_SOC_CON16 0x0440 419 420 /* RK3368_GRF_SOC_CON15 */ 421 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 422 GRF_CLR_BIT(11)) 423 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 424 GRF_BIT(11)) 425 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 426 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 427 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 428 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 429 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 430 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 431 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 432 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 433 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 434 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 435 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 436 437 /* RK3368_GRF_SOC_CON16 */ 438 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 439 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 440 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 441 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 442 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 443 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 444 445 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 446 int tx_delay, int rx_delay) 447 { 448 struct device *dev = &bsp_priv->pdev->dev; 449 450 if (IS_ERR(bsp_priv->grf)) { 451 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 452 return; 453 } 454 455 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 456 RK3368_GMAC_PHY_INTF_SEL_RGMII | 457 RK3368_GMAC_RMII_MODE_CLR); 458 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 459 RK3368_GMAC_RXCLK_DLY_ENABLE | 460 RK3368_GMAC_TXCLK_DLY_ENABLE | 461 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 462 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 463 } 464 465 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 466 { 467 struct device *dev = &bsp_priv->pdev->dev; 468 469 if (IS_ERR(bsp_priv->grf)) { 470 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 471 return; 472 } 473 474 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 475 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 476 } 477 478 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 479 { 480 struct device *dev = &bsp_priv->pdev->dev; 481 482 if (IS_ERR(bsp_priv->grf)) { 483 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 484 return; 485 } 486 487 if (speed == 10) 488 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 489 RK3368_GMAC_CLK_2_5M); 490 else if (speed == 100) 491 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 492 RK3368_GMAC_CLK_25M); 493 else if (speed == 1000) 494 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 495 RK3368_GMAC_CLK_125M); 496 else 497 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 498 } 499 500 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 501 { 502 struct device *dev = &bsp_priv->pdev->dev; 503 504 if (IS_ERR(bsp_priv->grf)) { 505 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 506 return; 507 } 508 509 if (speed == 10) { 510 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 511 RK3368_GMAC_RMII_CLK_2_5M | 512 RK3368_GMAC_SPEED_10M); 513 } else if (speed == 100) { 514 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 515 RK3368_GMAC_RMII_CLK_25M | 516 RK3368_GMAC_SPEED_100M); 517 } else { 518 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 519 } 520 } 521 522 static const struct rk_gmac_ops rk3368_ops = { 523 .set_to_rgmii = rk3368_set_to_rgmii, 524 .set_to_rmii = rk3368_set_to_rmii, 525 .set_rgmii_speed = rk3368_set_rgmii_speed, 526 .set_rmii_speed = rk3368_set_rmii_speed, 527 }; 528 529 #define RK3399_GRF_SOC_CON5 0xc214 530 #define RK3399_GRF_SOC_CON6 0xc218 531 532 /* RK3399_GRF_SOC_CON5 */ 533 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 534 GRF_CLR_BIT(11)) 535 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 536 GRF_BIT(11)) 537 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 538 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 539 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 540 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 541 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 542 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 543 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 544 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 545 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 546 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 547 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 548 549 /* RK3399_GRF_SOC_CON6 */ 550 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 551 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 552 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 553 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 554 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 555 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 556 557 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 558 int tx_delay, int rx_delay) 559 { 560 struct device *dev = &bsp_priv->pdev->dev; 561 562 if (IS_ERR(bsp_priv->grf)) { 563 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 564 return; 565 } 566 567 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 568 RK3399_GMAC_PHY_INTF_SEL_RGMII | 569 RK3399_GMAC_RMII_MODE_CLR); 570 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 571 RK3399_GMAC_RXCLK_DLY_ENABLE | 572 RK3399_GMAC_TXCLK_DLY_ENABLE | 573 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 574 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 575 } 576 577 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 578 { 579 struct device *dev = &bsp_priv->pdev->dev; 580 581 if (IS_ERR(bsp_priv->grf)) { 582 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 583 return; 584 } 585 586 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 587 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 588 } 589 590 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 591 { 592 struct device *dev = &bsp_priv->pdev->dev; 593 594 if (IS_ERR(bsp_priv->grf)) { 595 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 596 return; 597 } 598 599 if (speed == 10) 600 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 601 RK3399_GMAC_CLK_2_5M); 602 else if (speed == 100) 603 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 604 RK3399_GMAC_CLK_25M); 605 else if (speed == 1000) 606 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 607 RK3399_GMAC_CLK_125M); 608 else 609 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 610 } 611 612 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 613 { 614 struct device *dev = &bsp_priv->pdev->dev; 615 616 if (IS_ERR(bsp_priv->grf)) { 617 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 618 return; 619 } 620 621 if (speed == 10) { 622 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 623 RK3399_GMAC_RMII_CLK_2_5M | 624 RK3399_GMAC_SPEED_10M); 625 } else if (speed == 100) { 626 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 627 RK3399_GMAC_RMII_CLK_25M | 628 RK3399_GMAC_SPEED_100M); 629 } else { 630 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 631 } 632 } 633 634 static const struct rk_gmac_ops rk3399_ops = { 635 .set_to_rgmii = rk3399_set_to_rgmii, 636 .set_to_rmii = rk3399_set_to_rmii, 637 .set_rgmii_speed = rk3399_set_rgmii_speed, 638 .set_rmii_speed = rk3399_set_rmii_speed, 639 }; 640 641 static int gmac_clk_init(struct rk_priv_data *bsp_priv) 642 { 643 struct device *dev = &bsp_priv->pdev->dev; 644 645 bsp_priv->clk_enabled = false; 646 647 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); 648 if (IS_ERR(bsp_priv->mac_clk_rx)) 649 dev_err(dev, "cannot get clock %s\n", 650 "mac_clk_rx"); 651 652 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); 653 if (IS_ERR(bsp_priv->mac_clk_tx)) 654 dev_err(dev, "cannot get clock %s\n", 655 "mac_clk_tx"); 656 657 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); 658 if (IS_ERR(bsp_priv->aclk_mac)) 659 dev_err(dev, "cannot get clock %s\n", 660 "aclk_mac"); 661 662 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); 663 if (IS_ERR(bsp_priv->pclk_mac)) 664 dev_err(dev, "cannot get clock %s\n", 665 "pclk_mac"); 666 667 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 668 if (IS_ERR(bsp_priv->clk_mac)) 669 dev_err(dev, "cannot get clock %s\n", 670 "stmmaceth"); 671 672 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 673 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); 674 if (IS_ERR(bsp_priv->clk_mac_ref)) 675 dev_err(dev, "cannot get clock %s\n", 676 "clk_mac_ref"); 677 678 if (!bsp_priv->clock_input) { 679 bsp_priv->clk_mac_refout = 680 devm_clk_get(dev, "clk_mac_refout"); 681 if (IS_ERR(bsp_priv->clk_mac_refout)) 682 dev_err(dev, "cannot get clock %s\n", 683 "clk_mac_refout"); 684 } 685 } 686 687 if (bsp_priv->clock_input) { 688 dev_info(dev, "clock input from PHY\n"); 689 } else { 690 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 691 clk_set_rate(bsp_priv->clk_mac, 50000000); 692 } 693 694 return 0; 695 } 696 697 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 698 { 699 int phy_iface = bsp_priv->phy_iface; 700 701 if (enable) { 702 if (!bsp_priv->clk_enabled) { 703 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 704 if (!IS_ERR(bsp_priv->mac_clk_rx)) 705 clk_prepare_enable( 706 bsp_priv->mac_clk_rx); 707 708 if (!IS_ERR(bsp_priv->clk_mac_ref)) 709 clk_prepare_enable( 710 bsp_priv->clk_mac_ref); 711 712 if (!IS_ERR(bsp_priv->clk_mac_refout)) 713 clk_prepare_enable( 714 bsp_priv->clk_mac_refout); 715 } 716 717 if (!IS_ERR(bsp_priv->aclk_mac)) 718 clk_prepare_enable(bsp_priv->aclk_mac); 719 720 if (!IS_ERR(bsp_priv->pclk_mac)) 721 clk_prepare_enable(bsp_priv->pclk_mac); 722 723 if (!IS_ERR(bsp_priv->mac_clk_tx)) 724 clk_prepare_enable(bsp_priv->mac_clk_tx); 725 726 /** 727 * if (!IS_ERR(bsp_priv->clk_mac)) 728 * clk_prepare_enable(bsp_priv->clk_mac); 729 */ 730 mdelay(5); 731 bsp_priv->clk_enabled = true; 732 } 733 } else { 734 if (bsp_priv->clk_enabled) { 735 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 736 if (!IS_ERR(bsp_priv->mac_clk_rx)) 737 clk_disable_unprepare( 738 bsp_priv->mac_clk_rx); 739 740 if (!IS_ERR(bsp_priv->clk_mac_ref)) 741 clk_disable_unprepare( 742 bsp_priv->clk_mac_ref); 743 744 if (!IS_ERR(bsp_priv->clk_mac_refout)) 745 clk_disable_unprepare( 746 bsp_priv->clk_mac_refout); 747 } 748 749 if (!IS_ERR(bsp_priv->aclk_mac)) 750 clk_disable_unprepare(bsp_priv->aclk_mac); 751 752 if (!IS_ERR(bsp_priv->pclk_mac)) 753 clk_disable_unprepare(bsp_priv->pclk_mac); 754 755 if (!IS_ERR(bsp_priv->mac_clk_tx)) 756 clk_disable_unprepare(bsp_priv->mac_clk_tx); 757 /** 758 * if (!IS_ERR(bsp_priv->clk_mac)) 759 * clk_disable_unprepare(bsp_priv->clk_mac); 760 */ 761 bsp_priv->clk_enabled = false; 762 } 763 } 764 765 return 0; 766 } 767 768 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 769 { 770 struct regulator *ldo = bsp_priv->regulator; 771 int ret; 772 struct device *dev = &bsp_priv->pdev->dev; 773 774 if (!ldo) { 775 dev_err(dev, "no regulator found\n"); 776 return -1; 777 } 778 779 if (enable) { 780 ret = regulator_enable(ldo); 781 if (ret) 782 dev_err(dev, "fail to enable phy-supply\n"); 783 } else { 784 ret = regulator_disable(ldo); 785 if (ret) 786 dev_err(dev, "fail to disable phy-supply\n"); 787 } 788 789 return 0; 790 } 791 792 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 793 const struct rk_gmac_ops *ops) 794 { 795 struct rk_priv_data *bsp_priv; 796 struct device *dev = &pdev->dev; 797 int ret; 798 const char *strings = NULL; 799 int value; 800 801 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 802 if (!bsp_priv) 803 return ERR_PTR(-ENOMEM); 804 805 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); 806 bsp_priv->ops = ops; 807 808 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); 809 if (IS_ERR(bsp_priv->regulator)) { 810 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { 811 dev_err(dev, "phy regulator is not available yet, deferred probing\n"); 812 return ERR_PTR(-EPROBE_DEFER); 813 } 814 dev_err(dev, "no regulator found\n"); 815 bsp_priv->regulator = NULL; 816 } 817 818 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 819 if (ret) { 820 dev_err(dev, "Can not read property: clock_in_out.\n"); 821 bsp_priv->clock_input = true; 822 } else { 823 dev_info(dev, "clock input or output? (%s).\n", 824 strings); 825 if (!strcmp(strings, "input")) 826 bsp_priv->clock_input = true; 827 else 828 bsp_priv->clock_input = false; 829 } 830 831 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 832 if (ret) { 833 bsp_priv->tx_delay = 0x30; 834 dev_err(dev, "Can not read property: tx_delay."); 835 dev_err(dev, "set tx_delay to 0x%x\n", 836 bsp_priv->tx_delay); 837 } else { 838 dev_info(dev, "TX delay(0x%x).\n", value); 839 bsp_priv->tx_delay = value; 840 } 841 842 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 843 if (ret) { 844 bsp_priv->rx_delay = 0x10; 845 dev_err(dev, "Can not read property: rx_delay."); 846 dev_err(dev, "set rx_delay to 0x%x\n", 847 bsp_priv->rx_delay); 848 } else { 849 dev_info(dev, "RX delay(0x%x).\n", value); 850 bsp_priv->rx_delay = value; 851 } 852 853 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 854 "rockchip,grf"); 855 bsp_priv->pdev = pdev; 856 857 gmac_clk_init(bsp_priv); 858 859 return bsp_priv; 860 } 861 862 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 863 { 864 int ret; 865 struct device *dev = &bsp_priv->pdev->dev; 866 867 ret = gmac_clk_enable(bsp_priv, true); 868 if (ret) 869 return ret; 870 871 /*rmii or rgmii*/ 872 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) { 873 dev_info(dev, "init for RGMII\n"); 874 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 875 bsp_priv->rx_delay); 876 } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 877 dev_info(dev, "init for RMII\n"); 878 bsp_priv->ops->set_to_rmii(bsp_priv); 879 } else { 880 dev_err(dev, "NO interface defined!\n"); 881 } 882 883 ret = phy_power_on(bsp_priv, true); 884 if (ret) 885 return ret; 886 887 pm_runtime_enable(dev); 888 pm_runtime_get_sync(dev); 889 890 return 0; 891 } 892 893 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 894 { 895 struct device *dev = &gmac->pdev->dev; 896 897 pm_runtime_put_sync(dev); 898 pm_runtime_disable(dev); 899 900 phy_power_on(gmac, false); 901 gmac_clk_enable(gmac, false); 902 } 903 904 static void rk_fix_speed(void *priv, unsigned int speed) 905 { 906 struct rk_priv_data *bsp_priv = priv; 907 struct device *dev = &bsp_priv->pdev->dev; 908 909 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) 910 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 911 else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 912 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 913 else 914 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 915 } 916 917 static int rk_gmac_probe(struct platform_device *pdev) 918 { 919 struct plat_stmmacenet_data *plat_dat; 920 struct stmmac_resources stmmac_res; 921 const struct rk_gmac_ops *data; 922 int ret; 923 924 data = of_device_get_match_data(&pdev->dev); 925 if (!data) { 926 dev_err(&pdev->dev, "no of match data provided\n"); 927 return -EINVAL; 928 } 929 930 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 931 if (ret) 932 return ret; 933 934 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 935 if (IS_ERR(plat_dat)) 936 return PTR_ERR(plat_dat); 937 938 plat_dat->has_gmac = true; 939 plat_dat->fix_mac_speed = rk_fix_speed; 940 941 plat_dat->bsp_priv = rk_gmac_setup(pdev, data); 942 if (IS_ERR(plat_dat->bsp_priv)) { 943 ret = PTR_ERR(plat_dat->bsp_priv); 944 goto err_remove_config_dt; 945 } 946 947 ret = rk_gmac_powerup(plat_dat->bsp_priv); 948 if (ret) 949 goto err_remove_config_dt; 950 951 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 952 if (ret) 953 goto err_gmac_powerdown; 954 955 return 0; 956 957 err_gmac_powerdown: 958 rk_gmac_powerdown(plat_dat->bsp_priv); 959 err_remove_config_dt: 960 stmmac_remove_config_dt(pdev, plat_dat); 961 962 return ret; 963 } 964 965 static int rk_gmac_remove(struct platform_device *pdev) 966 { 967 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 968 int ret = stmmac_dvr_remove(&pdev->dev); 969 970 rk_gmac_powerdown(bsp_priv); 971 972 return ret; 973 } 974 975 #ifdef CONFIG_PM_SLEEP 976 static int rk_gmac_suspend(struct device *dev) 977 { 978 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 979 int ret = stmmac_suspend(dev); 980 981 /* Keep the PHY up if we use Wake-on-Lan. */ 982 if (!device_may_wakeup(dev)) { 983 rk_gmac_powerdown(bsp_priv); 984 bsp_priv->suspended = true; 985 } 986 987 return ret; 988 } 989 990 static int rk_gmac_resume(struct device *dev) 991 { 992 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 993 994 /* The PHY was up for Wake-on-Lan. */ 995 if (bsp_priv->suspended) { 996 rk_gmac_powerup(bsp_priv); 997 bsp_priv->suspended = false; 998 } 999 1000 return stmmac_resume(dev); 1001 } 1002 #endif /* CONFIG_PM_SLEEP */ 1003 1004 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1005 1006 static const struct of_device_id rk_gmac_dwmac_match[] = { 1007 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1008 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1009 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1010 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1011 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1012 { } 1013 }; 1014 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1015 1016 static struct platform_driver rk_gmac_dwmac_driver = { 1017 .probe = rk_gmac_probe, 1018 .remove = rk_gmac_remove, 1019 .driver = { 1020 .name = "rk_gmac-dwmac", 1021 .pm = &rk_gmac_pm_ops, 1022 .of_match_table = rk_gmac_dwmac_match, 1023 }, 1024 }; 1025 module_platform_driver(rk_gmac_dwmac_driver); 1026 1027 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1028 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1029 MODULE_LICENSE("GPL"); 1030