1 /** 2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 3 * 4 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 5 * 6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/stmmac.h> 20 #include <linux/bitops.h> 21 #include <linux/clk.h> 22 #include <linux/phy.h> 23 #include <linux/of_net.h> 24 #include <linux/gpio.h> 25 #include <linux/module.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/delay.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/regmap.h> 33 #include <linux/pm_runtime.h> 34 35 #include "stmmac_platform.h" 36 37 struct rk_priv_data; 38 struct rk_gmac_ops { 39 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 40 int tx_delay, int rx_delay); 41 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 42 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 43 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 44 }; 45 46 struct rk_priv_data { 47 struct platform_device *pdev; 48 int phy_iface; 49 struct regulator *regulator; 50 bool suspended; 51 const struct rk_gmac_ops *ops; 52 53 bool clk_enabled; 54 bool clock_input; 55 56 struct clk *clk_mac; 57 struct clk *gmac_clkin; 58 struct clk *mac_clk_rx; 59 struct clk *mac_clk_tx; 60 struct clk *clk_mac_ref; 61 struct clk *clk_mac_refout; 62 struct clk *aclk_mac; 63 struct clk *pclk_mac; 64 65 int tx_delay; 66 int rx_delay; 67 68 struct regmap *grf; 69 }; 70 71 #define HIWORD_UPDATE(val, mask, shift) \ 72 ((val) << (shift) | (mask) << ((shift) + 16)) 73 74 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 75 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 76 77 #define RK3228_GRF_MAC_CON0 0x0900 78 #define RK3228_GRF_MAC_CON1 0x0904 79 80 /* RK3228_GRF_MAC_CON0 */ 81 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 82 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 83 84 /* RK3228_GRF_MAC_CON1 */ 85 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 86 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 87 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 88 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 89 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 90 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 91 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 92 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 93 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 94 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 95 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 96 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 97 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 98 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 99 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 100 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 101 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 102 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 103 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 104 105 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 106 int tx_delay, int rx_delay) 107 { 108 struct device *dev = &bsp_priv->pdev->dev; 109 110 if (IS_ERR(bsp_priv->grf)) { 111 dev_err(dev, "Missing rockchip,grf property\n"); 112 return; 113 } 114 115 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 116 RK3228_GMAC_PHY_INTF_SEL_RGMII | 117 RK3228_GMAC_RMII_MODE_CLR | 118 RK3228_GMAC_RXCLK_DLY_ENABLE | 119 RK3228_GMAC_TXCLK_DLY_ENABLE); 120 121 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 122 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 123 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 124 } 125 126 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 127 { 128 struct device *dev = &bsp_priv->pdev->dev; 129 130 if (IS_ERR(bsp_priv->grf)) { 131 dev_err(dev, "Missing rockchip,grf property\n"); 132 return; 133 } 134 135 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 136 RK3228_GMAC_PHY_INTF_SEL_RMII | 137 RK3228_GMAC_RMII_MODE); 138 139 /* set MAC to RMII mode */ 140 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 141 } 142 143 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 144 { 145 struct device *dev = &bsp_priv->pdev->dev; 146 147 if (IS_ERR(bsp_priv->grf)) { 148 dev_err(dev, "Missing rockchip,grf property\n"); 149 return; 150 } 151 152 if (speed == 10) 153 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 154 RK3228_GMAC_CLK_2_5M); 155 else if (speed == 100) 156 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 157 RK3228_GMAC_CLK_25M); 158 else if (speed == 1000) 159 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 160 RK3228_GMAC_CLK_125M); 161 else 162 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 163 } 164 165 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 166 { 167 struct device *dev = &bsp_priv->pdev->dev; 168 169 if (IS_ERR(bsp_priv->grf)) { 170 dev_err(dev, "Missing rockchip,grf property\n"); 171 return; 172 } 173 174 if (speed == 10) 175 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 176 RK3228_GMAC_RMII_CLK_2_5M | 177 RK3228_GMAC_SPEED_10M); 178 else if (speed == 100) 179 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 180 RK3228_GMAC_RMII_CLK_25M | 181 RK3228_GMAC_SPEED_100M); 182 else 183 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 184 } 185 186 static const struct rk_gmac_ops rk3228_ops = { 187 .set_to_rgmii = rk3228_set_to_rgmii, 188 .set_to_rmii = rk3228_set_to_rmii, 189 .set_rgmii_speed = rk3228_set_rgmii_speed, 190 .set_rmii_speed = rk3228_set_rmii_speed, 191 }; 192 193 #define RK3288_GRF_SOC_CON1 0x0248 194 #define RK3288_GRF_SOC_CON3 0x0250 195 196 /*RK3288_GRF_SOC_CON1*/ 197 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 198 GRF_CLR_BIT(8)) 199 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 200 GRF_BIT(8)) 201 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 202 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 203 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 204 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 205 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 206 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 207 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 208 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 209 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 210 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 211 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 212 213 /*RK3288_GRF_SOC_CON3*/ 214 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 215 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 216 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 217 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 218 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 219 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 220 221 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 222 int tx_delay, int rx_delay) 223 { 224 struct device *dev = &bsp_priv->pdev->dev; 225 226 if (IS_ERR(bsp_priv->grf)) { 227 dev_err(dev, "Missing rockchip,grf property\n"); 228 return; 229 } 230 231 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 232 RK3288_GMAC_PHY_INTF_SEL_RGMII | 233 RK3288_GMAC_RMII_MODE_CLR); 234 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 235 RK3288_GMAC_RXCLK_DLY_ENABLE | 236 RK3288_GMAC_TXCLK_DLY_ENABLE | 237 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 238 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 239 } 240 241 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 242 { 243 struct device *dev = &bsp_priv->pdev->dev; 244 245 if (IS_ERR(bsp_priv->grf)) { 246 dev_err(dev, "Missing rockchip,grf property\n"); 247 return; 248 } 249 250 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 251 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 252 } 253 254 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 255 { 256 struct device *dev = &bsp_priv->pdev->dev; 257 258 if (IS_ERR(bsp_priv->grf)) { 259 dev_err(dev, "Missing rockchip,grf property\n"); 260 return; 261 } 262 263 if (speed == 10) 264 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 265 RK3288_GMAC_CLK_2_5M); 266 else if (speed == 100) 267 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 268 RK3288_GMAC_CLK_25M); 269 else if (speed == 1000) 270 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 271 RK3288_GMAC_CLK_125M); 272 else 273 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 274 } 275 276 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 277 { 278 struct device *dev = &bsp_priv->pdev->dev; 279 280 if (IS_ERR(bsp_priv->grf)) { 281 dev_err(dev, "Missing rockchip,grf property\n"); 282 return; 283 } 284 285 if (speed == 10) { 286 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 287 RK3288_GMAC_RMII_CLK_2_5M | 288 RK3288_GMAC_SPEED_10M); 289 } else if (speed == 100) { 290 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 291 RK3288_GMAC_RMII_CLK_25M | 292 RK3288_GMAC_SPEED_100M); 293 } else { 294 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 295 } 296 } 297 298 static const struct rk_gmac_ops rk3288_ops = { 299 .set_to_rgmii = rk3288_set_to_rgmii, 300 .set_to_rmii = rk3288_set_to_rmii, 301 .set_rgmii_speed = rk3288_set_rgmii_speed, 302 .set_rmii_speed = rk3288_set_rmii_speed, 303 }; 304 305 #define RK3328_GRF_MAC_CON0 0x0900 306 #define RK3328_GRF_MAC_CON1 0x0904 307 308 /* RK3328_GRF_MAC_CON0 */ 309 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 310 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 311 312 /* RK3328_GRF_MAC_CON1 */ 313 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 314 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 315 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 316 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 317 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 318 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 319 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 320 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 321 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 322 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 323 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 324 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 325 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 326 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 327 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 328 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 329 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 330 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 331 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 332 333 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 334 int tx_delay, int rx_delay) 335 { 336 struct device *dev = &bsp_priv->pdev->dev; 337 338 if (IS_ERR(bsp_priv->grf)) { 339 dev_err(dev, "Missing rockchip,grf property\n"); 340 return; 341 } 342 343 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 344 RK3328_GMAC_PHY_INTF_SEL_RGMII | 345 RK3328_GMAC_RMII_MODE_CLR | 346 RK3328_GMAC_RXCLK_DLY_ENABLE | 347 RK3328_GMAC_TXCLK_DLY_ENABLE); 348 349 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 350 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 351 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 352 } 353 354 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 355 { 356 struct device *dev = &bsp_priv->pdev->dev; 357 358 if (IS_ERR(bsp_priv->grf)) { 359 dev_err(dev, "Missing rockchip,grf property\n"); 360 return; 361 } 362 363 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 364 RK3328_GMAC_PHY_INTF_SEL_RMII | 365 RK3328_GMAC_RMII_MODE); 366 367 /* set MAC to RMII mode */ 368 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11)); 369 } 370 371 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 372 { 373 struct device *dev = &bsp_priv->pdev->dev; 374 375 if (IS_ERR(bsp_priv->grf)) { 376 dev_err(dev, "Missing rockchip,grf property\n"); 377 return; 378 } 379 380 if (speed == 10) 381 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 382 RK3328_GMAC_CLK_2_5M); 383 else if (speed == 100) 384 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 385 RK3328_GMAC_CLK_25M); 386 else if (speed == 1000) 387 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 388 RK3328_GMAC_CLK_125M); 389 else 390 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 391 } 392 393 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 394 { 395 struct device *dev = &bsp_priv->pdev->dev; 396 397 if (IS_ERR(bsp_priv->grf)) { 398 dev_err(dev, "Missing rockchip,grf property\n"); 399 return; 400 } 401 402 if (speed == 10) 403 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 404 RK3328_GMAC_RMII_CLK_2_5M | 405 RK3328_GMAC_SPEED_10M); 406 else if (speed == 100) 407 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 408 RK3328_GMAC_RMII_CLK_25M | 409 RK3328_GMAC_SPEED_100M); 410 else 411 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 412 } 413 414 static const struct rk_gmac_ops rk3328_ops = { 415 .set_to_rgmii = rk3328_set_to_rgmii, 416 .set_to_rmii = rk3328_set_to_rmii, 417 .set_rgmii_speed = rk3328_set_rgmii_speed, 418 .set_rmii_speed = rk3328_set_rmii_speed, 419 }; 420 421 #define RK3366_GRF_SOC_CON6 0x0418 422 #define RK3366_GRF_SOC_CON7 0x041c 423 424 /* RK3366_GRF_SOC_CON6 */ 425 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 426 GRF_CLR_BIT(11)) 427 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 428 GRF_BIT(11)) 429 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 430 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 431 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 432 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 433 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 434 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 435 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 436 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 437 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 438 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 439 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 440 441 /* RK3366_GRF_SOC_CON7 */ 442 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 443 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 444 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 445 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 446 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 447 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 448 449 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 450 int tx_delay, int rx_delay) 451 { 452 struct device *dev = &bsp_priv->pdev->dev; 453 454 if (IS_ERR(bsp_priv->grf)) { 455 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 456 return; 457 } 458 459 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 460 RK3366_GMAC_PHY_INTF_SEL_RGMII | 461 RK3366_GMAC_RMII_MODE_CLR); 462 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 463 RK3366_GMAC_RXCLK_DLY_ENABLE | 464 RK3366_GMAC_TXCLK_DLY_ENABLE | 465 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 466 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 467 } 468 469 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 470 { 471 struct device *dev = &bsp_priv->pdev->dev; 472 473 if (IS_ERR(bsp_priv->grf)) { 474 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 475 return; 476 } 477 478 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 479 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 480 } 481 482 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 483 { 484 struct device *dev = &bsp_priv->pdev->dev; 485 486 if (IS_ERR(bsp_priv->grf)) { 487 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 488 return; 489 } 490 491 if (speed == 10) 492 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 493 RK3366_GMAC_CLK_2_5M); 494 else if (speed == 100) 495 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 496 RK3366_GMAC_CLK_25M); 497 else if (speed == 1000) 498 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 499 RK3366_GMAC_CLK_125M); 500 else 501 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 502 } 503 504 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 505 { 506 struct device *dev = &bsp_priv->pdev->dev; 507 508 if (IS_ERR(bsp_priv->grf)) { 509 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 510 return; 511 } 512 513 if (speed == 10) { 514 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 515 RK3366_GMAC_RMII_CLK_2_5M | 516 RK3366_GMAC_SPEED_10M); 517 } else if (speed == 100) { 518 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 519 RK3366_GMAC_RMII_CLK_25M | 520 RK3366_GMAC_SPEED_100M); 521 } else { 522 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 523 } 524 } 525 526 static const struct rk_gmac_ops rk3366_ops = { 527 .set_to_rgmii = rk3366_set_to_rgmii, 528 .set_to_rmii = rk3366_set_to_rmii, 529 .set_rgmii_speed = rk3366_set_rgmii_speed, 530 .set_rmii_speed = rk3366_set_rmii_speed, 531 }; 532 533 #define RK3368_GRF_SOC_CON15 0x043c 534 #define RK3368_GRF_SOC_CON16 0x0440 535 536 /* RK3368_GRF_SOC_CON15 */ 537 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 538 GRF_CLR_BIT(11)) 539 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 540 GRF_BIT(11)) 541 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 542 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 543 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 544 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 545 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 546 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 547 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 548 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 549 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 550 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 551 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 552 553 /* RK3368_GRF_SOC_CON16 */ 554 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 555 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 556 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 557 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 558 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 559 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 560 561 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 562 int tx_delay, int rx_delay) 563 { 564 struct device *dev = &bsp_priv->pdev->dev; 565 566 if (IS_ERR(bsp_priv->grf)) { 567 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 568 return; 569 } 570 571 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 572 RK3368_GMAC_PHY_INTF_SEL_RGMII | 573 RK3368_GMAC_RMII_MODE_CLR); 574 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 575 RK3368_GMAC_RXCLK_DLY_ENABLE | 576 RK3368_GMAC_TXCLK_DLY_ENABLE | 577 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 578 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 579 } 580 581 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 582 { 583 struct device *dev = &bsp_priv->pdev->dev; 584 585 if (IS_ERR(bsp_priv->grf)) { 586 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 587 return; 588 } 589 590 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 591 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 592 } 593 594 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 595 { 596 struct device *dev = &bsp_priv->pdev->dev; 597 598 if (IS_ERR(bsp_priv->grf)) { 599 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 600 return; 601 } 602 603 if (speed == 10) 604 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 605 RK3368_GMAC_CLK_2_5M); 606 else if (speed == 100) 607 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 608 RK3368_GMAC_CLK_25M); 609 else if (speed == 1000) 610 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 611 RK3368_GMAC_CLK_125M); 612 else 613 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 614 } 615 616 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 617 { 618 struct device *dev = &bsp_priv->pdev->dev; 619 620 if (IS_ERR(bsp_priv->grf)) { 621 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 622 return; 623 } 624 625 if (speed == 10) { 626 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 627 RK3368_GMAC_RMII_CLK_2_5M | 628 RK3368_GMAC_SPEED_10M); 629 } else if (speed == 100) { 630 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 631 RK3368_GMAC_RMII_CLK_25M | 632 RK3368_GMAC_SPEED_100M); 633 } else { 634 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 635 } 636 } 637 638 static const struct rk_gmac_ops rk3368_ops = { 639 .set_to_rgmii = rk3368_set_to_rgmii, 640 .set_to_rmii = rk3368_set_to_rmii, 641 .set_rgmii_speed = rk3368_set_rgmii_speed, 642 .set_rmii_speed = rk3368_set_rmii_speed, 643 }; 644 645 #define RK3399_GRF_SOC_CON5 0xc214 646 #define RK3399_GRF_SOC_CON6 0xc218 647 648 /* RK3399_GRF_SOC_CON5 */ 649 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 650 GRF_CLR_BIT(11)) 651 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 652 GRF_BIT(11)) 653 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 654 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 655 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 656 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 657 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 658 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 659 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 660 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 661 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 662 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 663 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 664 665 /* RK3399_GRF_SOC_CON6 */ 666 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 667 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 668 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 669 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 670 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 671 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 672 673 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 674 int tx_delay, int rx_delay) 675 { 676 struct device *dev = &bsp_priv->pdev->dev; 677 678 if (IS_ERR(bsp_priv->grf)) { 679 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 680 return; 681 } 682 683 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 684 RK3399_GMAC_PHY_INTF_SEL_RGMII | 685 RK3399_GMAC_RMII_MODE_CLR); 686 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 687 RK3399_GMAC_RXCLK_DLY_ENABLE | 688 RK3399_GMAC_TXCLK_DLY_ENABLE | 689 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 690 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 691 } 692 693 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 694 { 695 struct device *dev = &bsp_priv->pdev->dev; 696 697 if (IS_ERR(bsp_priv->grf)) { 698 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 699 return; 700 } 701 702 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 703 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 704 } 705 706 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 707 { 708 struct device *dev = &bsp_priv->pdev->dev; 709 710 if (IS_ERR(bsp_priv->grf)) { 711 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 712 return; 713 } 714 715 if (speed == 10) 716 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 717 RK3399_GMAC_CLK_2_5M); 718 else if (speed == 100) 719 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 720 RK3399_GMAC_CLK_25M); 721 else if (speed == 1000) 722 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 723 RK3399_GMAC_CLK_125M); 724 else 725 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 726 } 727 728 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 729 { 730 struct device *dev = &bsp_priv->pdev->dev; 731 732 if (IS_ERR(bsp_priv->grf)) { 733 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 734 return; 735 } 736 737 if (speed == 10) { 738 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 739 RK3399_GMAC_RMII_CLK_2_5M | 740 RK3399_GMAC_SPEED_10M); 741 } else if (speed == 100) { 742 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 743 RK3399_GMAC_RMII_CLK_25M | 744 RK3399_GMAC_SPEED_100M); 745 } else { 746 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 747 } 748 } 749 750 static const struct rk_gmac_ops rk3399_ops = { 751 .set_to_rgmii = rk3399_set_to_rgmii, 752 .set_to_rmii = rk3399_set_to_rmii, 753 .set_rgmii_speed = rk3399_set_rgmii_speed, 754 .set_rmii_speed = rk3399_set_rmii_speed, 755 }; 756 757 static int gmac_clk_init(struct rk_priv_data *bsp_priv) 758 { 759 struct device *dev = &bsp_priv->pdev->dev; 760 761 bsp_priv->clk_enabled = false; 762 763 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); 764 if (IS_ERR(bsp_priv->mac_clk_rx)) 765 dev_err(dev, "cannot get clock %s\n", 766 "mac_clk_rx"); 767 768 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); 769 if (IS_ERR(bsp_priv->mac_clk_tx)) 770 dev_err(dev, "cannot get clock %s\n", 771 "mac_clk_tx"); 772 773 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); 774 if (IS_ERR(bsp_priv->aclk_mac)) 775 dev_err(dev, "cannot get clock %s\n", 776 "aclk_mac"); 777 778 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); 779 if (IS_ERR(bsp_priv->pclk_mac)) 780 dev_err(dev, "cannot get clock %s\n", 781 "pclk_mac"); 782 783 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 784 if (IS_ERR(bsp_priv->clk_mac)) 785 dev_err(dev, "cannot get clock %s\n", 786 "stmmaceth"); 787 788 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 789 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); 790 if (IS_ERR(bsp_priv->clk_mac_ref)) 791 dev_err(dev, "cannot get clock %s\n", 792 "clk_mac_ref"); 793 794 if (!bsp_priv->clock_input) { 795 bsp_priv->clk_mac_refout = 796 devm_clk_get(dev, "clk_mac_refout"); 797 if (IS_ERR(bsp_priv->clk_mac_refout)) 798 dev_err(dev, "cannot get clock %s\n", 799 "clk_mac_refout"); 800 } 801 } 802 803 if (bsp_priv->clock_input) { 804 dev_info(dev, "clock input from PHY\n"); 805 } else { 806 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 807 clk_set_rate(bsp_priv->clk_mac, 50000000); 808 } 809 810 return 0; 811 } 812 813 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 814 { 815 int phy_iface = bsp_priv->phy_iface; 816 817 if (enable) { 818 if (!bsp_priv->clk_enabled) { 819 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 820 if (!IS_ERR(bsp_priv->mac_clk_rx)) 821 clk_prepare_enable( 822 bsp_priv->mac_clk_rx); 823 824 if (!IS_ERR(bsp_priv->clk_mac_ref)) 825 clk_prepare_enable( 826 bsp_priv->clk_mac_ref); 827 828 if (!IS_ERR(bsp_priv->clk_mac_refout)) 829 clk_prepare_enable( 830 bsp_priv->clk_mac_refout); 831 } 832 833 if (!IS_ERR(bsp_priv->aclk_mac)) 834 clk_prepare_enable(bsp_priv->aclk_mac); 835 836 if (!IS_ERR(bsp_priv->pclk_mac)) 837 clk_prepare_enable(bsp_priv->pclk_mac); 838 839 if (!IS_ERR(bsp_priv->mac_clk_tx)) 840 clk_prepare_enable(bsp_priv->mac_clk_tx); 841 842 /** 843 * if (!IS_ERR(bsp_priv->clk_mac)) 844 * clk_prepare_enable(bsp_priv->clk_mac); 845 */ 846 mdelay(5); 847 bsp_priv->clk_enabled = true; 848 } 849 } else { 850 if (bsp_priv->clk_enabled) { 851 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 852 if (!IS_ERR(bsp_priv->mac_clk_rx)) 853 clk_disable_unprepare( 854 bsp_priv->mac_clk_rx); 855 856 if (!IS_ERR(bsp_priv->clk_mac_ref)) 857 clk_disable_unprepare( 858 bsp_priv->clk_mac_ref); 859 860 if (!IS_ERR(bsp_priv->clk_mac_refout)) 861 clk_disable_unprepare( 862 bsp_priv->clk_mac_refout); 863 } 864 865 if (!IS_ERR(bsp_priv->aclk_mac)) 866 clk_disable_unprepare(bsp_priv->aclk_mac); 867 868 if (!IS_ERR(bsp_priv->pclk_mac)) 869 clk_disable_unprepare(bsp_priv->pclk_mac); 870 871 if (!IS_ERR(bsp_priv->mac_clk_tx)) 872 clk_disable_unprepare(bsp_priv->mac_clk_tx); 873 /** 874 * if (!IS_ERR(bsp_priv->clk_mac)) 875 * clk_disable_unprepare(bsp_priv->clk_mac); 876 */ 877 bsp_priv->clk_enabled = false; 878 } 879 } 880 881 return 0; 882 } 883 884 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 885 { 886 struct regulator *ldo = bsp_priv->regulator; 887 int ret; 888 struct device *dev = &bsp_priv->pdev->dev; 889 890 if (!ldo) { 891 dev_err(dev, "no regulator found\n"); 892 return -1; 893 } 894 895 if (enable) { 896 ret = regulator_enable(ldo); 897 if (ret) 898 dev_err(dev, "fail to enable phy-supply\n"); 899 } else { 900 ret = regulator_disable(ldo); 901 if (ret) 902 dev_err(dev, "fail to disable phy-supply\n"); 903 } 904 905 return 0; 906 } 907 908 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 909 const struct rk_gmac_ops *ops) 910 { 911 struct rk_priv_data *bsp_priv; 912 struct device *dev = &pdev->dev; 913 int ret; 914 const char *strings = NULL; 915 int value; 916 917 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 918 if (!bsp_priv) 919 return ERR_PTR(-ENOMEM); 920 921 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); 922 bsp_priv->ops = ops; 923 924 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); 925 if (IS_ERR(bsp_priv->regulator)) { 926 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { 927 dev_err(dev, "phy regulator is not available yet, deferred probing\n"); 928 return ERR_PTR(-EPROBE_DEFER); 929 } 930 dev_err(dev, "no regulator found\n"); 931 bsp_priv->regulator = NULL; 932 } 933 934 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 935 if (ret) { 936 dev_err(dev, "Can not read property: clock_in_out.\n"); 937 bsp_priv->clock_input = true; 938 } else { 939 dev_info(dev, "clock input or output? (%s).\n", 940 strings); 941 if (!strcmp(strings, "input")) 942 bsp_priv->clock_input = true; 943 else 944 bsp_priv->clock_input = false; 945 } 946 947 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 948 if (ret) { 949 bsp_priv->tx_delay = 0x30; 950 dev_err(dev, "Can not read property: tx_delay."); 951 dev_err(dev, "set tx_delay to 0x%x\n", 952 bsp_priv->tx_delay); 953 } else { 954 dev_info(dev, "TX delay(0x%x).\n", value); 955 bsp_priv->tx_delay = value; 956 } 957 958 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 959 if (ret) { 960 bsp_priv->rx_delay = 0x10; 961 dev_err(dev, "Can not read property: rx_delay."); 962 dev_err(dev, "set rx_delay to 0x%x\n", 963 bsp_priv->rx_delay); 964 } else { 965 dev_info(dev, "RX delay(0x%x).\n", value); 966 bsp_priv->rx_delay = value; 967 } 968 969 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 970 "rockchip,grf"); 971 bsp_priv->pdev = pdev; 972 973 gmac_clk_init(bsp_priv); 974 975 return bsp_priv; 976 } 977 978 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 979 { 980 int ret; 981 struct device *dev = &bsp_priv->pdev->dev; 982 983 ret = gmac_clk_enable(bsp_priv, true); 984 if (ret) 985 return ret; 986 987 /*rmii or rgmii*/ 988 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) { 989 dev_info(dev, "init for RGMII\n"); 990 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 991 bsp_priv->rx_delay); 992 } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 993 dev_info(dev, "init for RMII\n"); 994 bsp_priv->ops->set_to_rmii(bsp_priv); 995 } else { 996 dev_err(dev, "NO interface defined!\n"); 997 } 998 999 ret = phy_power_on(bsp_priv, true); 1000 if (ret) 1001 return ret; 1002 1003 pm_runtime_enable(dev); 1004 pm_runtime_get_sync(dev); 1005 1006 return 0; 1007 } 1008 1009 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1010 { 1011 struct device *dev = &gmac->pdev->dev; 1012 1013 pm_runtime_put_sync(dev); 1014 pm_runtime_disable(dev); 1015 1016 phy_power_on(gmac, false); 1017 gmac_clk_enable(gmac, false); 1018 } 1019 1020 static void rk_fix_speed(void *priv, unsigned int speed) 1021 { 1022 struct rk_priv_data *bsp_priv = priv; 1023 struct device *dev = &bsp_priv->pdev->dev; 1024 1025 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) 1026 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 1027 else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1028 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 1029 else 1030 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 1031 } 1032 1033 static int rk_gmac_probe(struct platform_device *pdev) 1034 { 1035 struct plat_stmmacenet_data *plat_dat; 1036 struct stmmac_resources stmmac_res; 1037 const struct rk_gmac_ops *data; 1038 int ret; 1039 1040 data = of_device_get_match_data(&pdev->dev); 1041 if (!data) { 1042 dev_err(&pdev->dev, "no of match data provided\n"); 1043 return -EINVAL; 1044 } 1045 1046 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1047 if (ret) 1048 return ret; 1049 1050 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1051 if (IS_ERR(plat_dat)) 1052 return PTR_ERR(plat_dat); 1053 1054 plat_dat->has_gmac = true; 1055 plat_dat->fix_mac_speed = rk_fix_speed; 1056 1057 plat_dat->bsp_priv = rk_gmac_setup(pdev, data); 1058 if (IS_ERR(plat_dat->bsp_priv)) { 1059 ret = PTR_ERR(plat_dat->bsp_priv); 1060 goto err_remove_config_dt; 1061 } 1062 1063 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1064 if (ret) 1065 goto err_remove_config_dt; 1066 1067 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1068 if (ret) 1069 goto err_gmac_powerdown; 1070 1071 return 0; 1072 1073 err_gmac_powerdown: 1074 rk_gmac_powerdown(plat_dat->bsp_priv); 1075 err_remove_config_dt: 1076 stmmac_remove_config_dt(pdev, plat_dat); 1077 1078 return ret; 1079 } 1080 1081 static int rk_gmac_remove(struct platform_device *pdev) 1082 { 1083 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 1084 int ret = stmmac_dvr_remove(&pdev->dev); 1085 1086 rk_gmac_powerdown(bsp_priv); 1087 1088 return ret; 1089 } 1090 1091 #ifdef CONFIG_PM_SLEEP 1092 static int rk_gmac_suspend(struct device *dev) 1093 { 1094 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1095 int ret = stmmac_suspend(dev); 1096 1097 /* Keep the PHY up if we use Wake-on-Lan. */ 1098 if (!device_may_wakeup(dev)) { 1099 rk_gmac_powerdown(bsp_priv); 1100 bsp_priv->suspended = true; 1101 } 1102 1103 return ret; 1104 } 1105 1106 static int rk_gmac_resume(struct device *dev) 1107 { 1108 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1109 1110 /* The PHY was up for Wake-on-Lan. */ 1111 if (bsp_priv->suspended) { 1112 rk_gmac_powerup(bsp_priv); 1113 bsp_priv->suspended = false; 1114 } 1115 1116 return stmmac_resume(dev); 1117 } 1118 #endif /* CONFIG_PM_SLEEP */ 1119 1120 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1121 1122 static const struct of_device_id rk_gmac_dwmac_match[] = { 1123 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1124 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1125 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1126 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1127 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1128 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1129 { } 1130 }; 1131 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1132 1133 static struct platform_driver rk_gmac_dwmac_driver = { 1134 .probe = rk_gmac_probe, 1135 .remove = rk_gmac_remove, 1136 .driver = { 1137 .name = "rk_gmac-dwmac", 1138 .pm = &rk_gmac_pm_ops, 1139 .of_match_table = rk_gmac_dwmac_match, 1140 }, 1141 }; 1142 module_platform_driver(rk_gmac_dwmac_driver); 1143 1144 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1145 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1146 MODULE_LICENSE("GPL"); 1147