1 /** 2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 3 * 4 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 5 * 6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/stmmac.h> 20 #include <linux/bitops.h> 21 #include <linux/clk.h> 22 #include <linux/phy.h> 23 #include <linux/of_net.h> 24 #include <linux/gpio.h> 25 #include <linux/module.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/delay.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/regmap.h> 33 #include <linux/pm_runtime.h> 34 35 #include "stmmac_platform.h" 36 37 struct rk_priv_data; 38 struct rk_gmac_ops { 39 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 40 int tx_delay, int rx_delay); 41 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); 42 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); 43 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); 44 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 }; 46 47 struct rk_priv_data { 48 struct platform_device *pdev; 49 int phy_iface; 50 struct regulator *regulator; 51 bool suspended; 52 const struct rk_gmac_ops *ops; 53 54 bool clk_enabled; 55 bool clock_input; 56 bool integrated_phy; 57 58 struct clk *clk_mac; 59 struct clk *gmac_clkin; 60 struct clk *mac_clk_rx; 61 struct clk *mac_clk_tx; 62 struct clk *clk_mac_ref; 63 struct clk *clk_mac_refout; 64 struct clk *clk_mac_speed; 65 struct clk *aclk_mac; 66 struct clk *pclk_mac; 67 struct clk *clk_phy; 68 69 struct reset_control *phy_reset; 70 71 int tx_delay; 72 int rx_delay; 73 74 struct regmap *grf; 75 }; 76 77 #define HIWORD_UPDATE(val, mask, shift) \ 78 ((val) << (shift) | (mask) << ((shift) + 16)) 79 80 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 81 #define GRF_CLR_BIT(nr) (BIT(nr+16)) 82 83 #define DELAY_ENABLE(soc, tx, rx) \ 84 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ 85 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) 86 87 #define PX30_GRF_GMAC_CON1 0x0904 88 89 /* PX30_GRF_GMAC_CON1 */ 90 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 91 GRF_BIT(6)) 92 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 93 #define PX30_GMAC_SPEED_100M GRF_BIT(2) 94 95 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 96 { 97 struct device *dev = &bsp_priv->pdev->dev; 98 99 if (IS_ERR(bsp_priv->grf)) { 100 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 101 return; 102 } 103 104 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 105 PX30_GMAC_PHY_INTF_SEL_RMII); 106 } 107 108 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 109 { 110 struct device *dev = &bsp_priv->pdev->dev; 111 int ret; 112 113 if (IS_ERR(bsp_priv->clk_mac_speed)) { 114 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 115 return; 116 } 117 118 if (speed == 10) { 119 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 120 PX30_GMAC_SPEED_10M); 121 122 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000); 123 if (ret) 124 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n", 125 __func__, ret); 126 } else if (speed == 100) { 127 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 128 PX30_GMAC_SPEED_100M); 129 130 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000); 131 if (ret) 132 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n", 133 __func__, ret); 134 135 } else { 136 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 137 } 138 } 139 140 static const struct rk_gmac_ops px30_ops = { 141 .set_to_rmii = px30_set_to_rmii, 142 .set_rmii_speed = px30_set_rmii_speed, 143 }; 144 145 #define RK3128_GRF_MAC_CON0 0x0168 146 #define RK3128_GRF_MAC_CON1 0x016c 147 148 /* RK3128_GRF_MAC_CON0 */ 149 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 150 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 151 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 152 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 153 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 154 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 155 156 /* RK3128_GRF_MAC_CON1 */ 157 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ 158 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 159 #define RK3128_GMAC_PHY_INTF_SEL_RMII \ 160 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 161 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 162 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 163 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 164 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 165 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 166 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 167 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 168 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 169 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 170 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 171 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 172 173 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 174 int tx_delay, int rx_delay) 175 { 176 struct device *dev = &bsp_priv->pdev->dev; 177 178 if (IS_ERR(bsp_priv->grf)) { 179 dev_err(dev, "Missing rockchip,grf property\n"); 180 return; 181 } 182 183 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 184 RK3128_GMAC_PHY_INTF_SEL_RGMII | 185 RK3128_GMAC_RMII_MODE_CLR); 186 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 187 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 188 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | 189 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); 190 } 191 192 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 193 { 194 struct device *dev = &bsp_priv->pdev->dev; 195 196 if (IS_ERR(bsp_priv->grf)) { 197 dev_err(dev, "Missing rockchip,grf property\n"); 198 return; 199 } 200 201 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 202 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); 203 } 204 205 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 206 { 207 struct device *dev = &bsp_priv->pdev->dev; 208 209 if (IS_ERR(bsp_priv->grf)) { 210 dev_err(dev, "Missing rockchip,grf property\n"); 211 return; 212 } 213 214 if (speed == 10) 215 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 216 RK3128_GMAC_CLK_2_5M); 217 else if (speed == 100) 218 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 219 RK3128_GMAC_CLK_25M); 220 else if (speed == 1000) 221 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 222 RK3128_GMAC_CLK_125M); 223 else 224 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 225 } 226 227 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 228 { 229 struct device *dev = &bsp_priv->pdev->dev; 230 231 if (IS_ERR(bsp_priv->grf)) { 232 dev_err(dev, "Missing rockchip,grf property\n"); 233 return; 234 } 235 236 if (speed == 10) { 237 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 238 RK3128_GMAC_RMII_CLK_2_5M | 239 RK3128_GMAC_SPEED_10M); 240 } else if (speed == 100) { 241 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 242 RK3128_GMAC_RMII_CLK_25M | 243 RK3128_GMAC_SPEED_100M); 244 } else { 245 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 246 } 247 } 248 249 static const struct rk_gmac_ops rk3128_ops = { 250 .set_to_rgmii = rk3128_set_to_rgmii, 251 .set_to_rmii = rk3128_set_to_rmii, 252 .set_rgmii_speed = rk3128_set_rgmii_speed, 253 .set_rmii_speed = rk3128_set_rmii_speed, 254 }; 255 256 #define RK3228_GRF_MAC_CON0 0x0900 257 #define RK3228_GRF_MAC_CON1 0x0904 258 259 #define RK3228_GRF_CON_MUX 0x50 260 261 /* RK3228_GRF_MAC_CON0 */ 262 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 263 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 264 265 /* RK3228_GRF_MAC_CON1 */ 266 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ 267 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 268 #define RK3228_GMAC_PHY_INTF_SEL_RMII \ 269 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 270 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 271 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 272 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 273 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 274 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 275 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 276 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) 277 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) 278 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) 279 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 280 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 281 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 282 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 283 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 284 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) 285 286 /* RK3228_GRF_COM_MUX */ 287 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) 288 289 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, 290 int tx_delay, int rx_delay) 291 { 292 struct device *dev = &bsp_priv->pdev->dev; 293 294 if (IS_ERR(bsp_priv->grf)) { 295 dev_err(dev, "Missing rockchip,grf property\n"); 296 return; 297 } 298 299 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 300 RK3228_GMAC_PHY_INTF_SEL_RGMII | 301 RK3228_GMAC_RMII_MODE_CLR | 302 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 303 304 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, 305 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | 306 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); 307 } 308 309 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 310 { 311 struct device *dev = &bsp_priv->pdev->dev; 312 313 if (IS_ERR(bsp_priv->grf)) { 314 dev_err(dev, "Missing rockchip,grf property\n"); 315 return; 316 } 317 318 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 319 RK3228_GMAC_PHY_INTF_SEL_RMII | 320 RK3228_GMAC_RMII_MODE); 321 322 /* set MAC to RMII mode */ 323 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 324 } 325 326 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 327 { 328 struct device *dev = &bsp_priv->pdev->dev; 329 330 if (IS_ERR(bsp_priv->grf)) { 331 dev_err(dev, "Missing rockchip,grf property\n"); 332 return; 333 } 334 335 if (speed == 10) 336 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 337 RK3228_GMAC_CLK_2_5M); 338 else if (speed == 100) 339 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 340 RK3228_GMAC_CLK_25M); 341 else if (speed == 1000) 342 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 343 RK3228_GMAC_CLK_125M); 344 else 345 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 346 } 347 348 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 349 { 350 struct device *dev = &bsp_priv->pdev->dev; 351 352 if (IS_ERR(bsp_priv->grf)) { 353 dev_err(dev, "Missing rockchip,grf property\n"); 354 return; 355 } 356 357 if (speed == 10) 358 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 359 RK3228_GMAC_RMII_CLK_2_5M | 360 RK3228_GMAC_SPEED_10M); 361 else if (speed == 100) 362 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 363 RK3228_GMAC_RMII_CLK_25M | 364 RK3228_GMAC_SPEED_100M); 365 else 366 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 367 } 368 369 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) 370 { 371 regmap_write(priv->grf, RK3228_GRF_CON_MUX, 372 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); 373 } 374 375 static const struct rk_gmac_ops rk3228_ops = { 376 .set_to_rgmii = rk3228_set_to_rgmii, 377 .set_to_rmii = rk3228_set_to_rmii, 378 .set_rgmii_speed = rk3228_set_rgmii_speed, 379 .set_rmii_speed = rk3228_set_rmii_speed, 380 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 381 }; 382 383 #define RK3288_GRF_SOC_CON1 0x0248 384 #define RK3288_GRF_SOC_CON3 0x0250 385 386 /*RK3288_GRF_SOC_CON1*/ 387 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ 388 GRF_CLR_BIT(8)) 389 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ 390 GRF_BIT(8)) 391 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 392 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 393 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 394 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 395 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 396 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 397 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 398 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 399 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 400 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 401 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 402 403 /*RK3288_GRF_SOC_CON3*/ 404 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 405 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 406 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 407 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 408 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 409 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 410 411 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 412 int tx_delay, int rx_delay) 413 { 414 struct device *dev = &bsp_priv->pdev->dev; 415 416 if (IS_ERR(bsp_priv->grf)) { 417 dev_err(dev, "Missing rockchip,grf property\n"); 418 return; 419 } 420 421 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 422 RK3288_GMAC_PHY_INTF_SEL_RGMII | 423 RK3288_GMAC_RMII_MODE_CLR); 424 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 425 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 426 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | 427 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); 428 } 429 430 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 431 { 432 struct device *dev = &bsp_priv->pdev->dev; 433 434 if (IS_ERR(bsp_priv->grf)) { 435 dev_err(dev, "Missing rockchip,grf property\n"); 436 return; 437 } 438 439 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 440 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); 441 } 442 443 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 444 { 445 struct device *dev = &bsp_priv->pdev->dev; 446 447 if (IS_ERR(bsp_priv->grf)) { 448 dev_err(dev, "Missing rockchip,grf property\n"); 449 return; 450 } 451 452 if (speed == 10) 453 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 454 RK3288_GMAC_CLK_2_5M); 455 else if (speed == 100) 456 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 457 RK3288_GMAC_CLK_25M); 458 else if (speed == 1000) 459 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 460 RK3288_GMAC_CLK_125M); 461 else 462 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 463 } 464 465 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 466 { 467 struct device *dev = &bsp_priv->pdev->dev; 468 469 if (IS_ERR(bsp_priv->grf)) { 470 dev_err(dev, "Missing rockchip,grf property\n"); 471 return; 472 } 473 474 if (speed == 10) { 475 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 476 RK3288_GMAC_RMII_CLK_2_5M | 477 RK3288_GMAC_SPEED_10M); 478 } else if (speed == 100) { 479 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 480 RK3288_GMAC_RMII_CLK_25M | 481 RK3288_GMAC_SPEED_100M); 482 } else { 483 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 484 } 485 } 486 487 static const struct rk_gmac_ops rk3288_ops = { 488 .set_to_rgmii = rk3288_set_to_rgmii, 489 .set_to_rmii = rk3288_set_to_rmii, 490 .set_rgmii_speed = rk3288_set_rgmii_speed, 491 .set_rmii_speed = rk3288_set_rmii_speed, 492 }; 493 494 #define RK3328_GRF_MAC_CON0 0x0900 495 #define RK3328_GRF_MAC_CON1 0x0904 496 #define RK3328_GRF_MAC_CON2 0x0908 497 #define RK3328_GRF_MACPHY_CON1 0xb04 498 499 /* RK3328_GRF_MAC_CON0 */ 500 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 501 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 502 503 /* RK3328_GRF_MAC_CON1 */ 504 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ 505 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) 506 #define RK3328_GMAC_PHY_INTF_SEL_RMII \ 507 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) 508 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 509 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 510 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 511 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 512 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 513 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 514 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) 515 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) 516 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) 517 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 518 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 519 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 520 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 521 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 522 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 523 524 /* RK3328_GRF_MACPHY_CON1 */ 525 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 526 527 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 528 int tx_delay, int rx_delay) 529 { 530 struct device *dev = &bsp_priv->pdev->dev; 531 532 if (IS_ERR(bsp_priv->grf)) { 533 dev_err(dev, "Missing rockchip,grf property\n"); 534 return; 535 } 536 537 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 538 RK3328_GMAC_PHY_INTF_SEL_RGMII | 539 RK3328_GMAC_RMII_MODE_CLR | 540 RK3328_GMAC_RXCLK_DLY_ENABLE | 541 RK3328_GMAC_TXCLK_DLY_ENABLE); 542 543 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, 544 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | 545 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); 546 } 547 548 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 549 { 550 struct device *dev = &bsp_priv->pdev->dev; 551 unsigned int reg; 552 553 if (IS_ERR(bsp_priv->grf)) { 554 dev_err(dev, "Missing rockchip,grf property\n"); 555 return; 556 } 557 558 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 559 RK3328_GRF_MAC_CON1; 560 561 regmap_write(bsp_priv->grf, reg, 562 RK3328_GMAC_PHY_INTF_SEL_RMII | 563 RK3328_GMAC_RMII_MODE); 564 } 565 566 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 567 { 568 struct device *dev = &bsp_priv->pdev->dev; 569 570 if (IS_ERR(bsp_priv->grf)) { 571 dev_err(dev, "Missing rockchip,grf property\n"); 572 return; 573 } 574 575 if (speed == 10) 576 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 577 RK3328_GMAC_CLK_2_5M); 578 else if (speed == 100) 579 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 580 RK3328_GMAC_CLK_25M); 581 else if (speed == 1000) 582 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 583 RK3328_GMAC_CLK_125M); 584 else 585 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 586 } 587 588 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 589 { 590 struct device *dev = &bsp_priv->pdev->dev; 591 unsigned int reg; 592 593 if (IS_ERR(bsp_priv->grf)) { 594 dev_err(dev, "Missing rockchip,grf property\n"); 595 return; 596 } 597 598 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : 599 RK3328_GRF_MAC_CON1; 600 601 if (speed == 10) 602 regmap_write(bsp_priv->grf, reg, 603 RK3328_GMAC_RMII_CLK_2_5M | 604 RK3328_GMAC_SPEED_10M); 605 else if (speed == 100) 606 regmap_write(bsp_priv->grf, reg, 607 RK3328_GMAC_RMII_CLK_25M | 608 RK3328_GMAC_SPEED_100M); 609 else 610 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 611 } 612 613 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) 614 { 615 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, 616 RK3328_MACPHY_RMII_MODE); 617 } 618 619 static const struct rk_gmac_ops rk3328_ops = { 620 .set_to_rgmii = rk3328_set_to_rgmii, 621 .set_to_rmii = rk3328_set_to_rmii, 622 .set_rgmii_speed = rk3328_set_rgmii_speed, 623 .set_rmii_speed = rk3328_set_rmii_speed, 624 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 625 }; 626 627 #define RK3366_GRF_SOC_CON6 0x0418 628 #define RK3366_GRF_SOC_CON7 0x041c 629 630 /* RK3366_GRF_SOC_CON6 */ 631 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 632 GRF_CLR_BIT(11)) 633 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 634 GRF_BIT(11)) 635 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 636 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 637 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 638 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 639 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 640 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 641 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 642 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 643 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 644 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 645 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 646 647 /* RK3366_GRF_SOC_CON7 */ 648 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 649 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 650 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 651 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 652 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 653 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 654 655 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 656 int tx_delay, int rx_delay) 657 { 658 struct device *dev = &bsp_priv->pdev->dev; 659 660 if (IS_ERR(bsp_priv->grf)) { 661 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 662 return; 663 } 664 665 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 666 RK3366_GMAC_PHY_INTF_SEL_RGMII | 667 RK3366_GMAC_RMII_MODE_CLR); 668 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 669 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 670 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | 671 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); 672 } 673 674 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 675 { 676 struct device *dev = &bsp_priv->pdev->dev; 677 678 if (IS_ERR(bsp_priv->grf)) { 679 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 680 return; 681 } 682 683 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 684 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); 685 } 686 687 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 688 { 689 struct device *dev = &bsp_priv->pdev->dev; 690 691 if (IS_ERR(bsp_priv->grf)) { 692 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 693 return; 694 } 695 696 if (speed == 10) 697 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 698 RK3366_GMAC_CLK_2_5M); 699 else if (speed == 100) 700 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 701 RK3366_GMAC_CLK_25M); 702 else if (speed == 1000) 703 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 704 RK3366_GMAC_CLK_125M); 705 else 706 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 707 } 708 709 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 710 { 711 struct device *dev = &bsp_priv->pdev->dev; 712 713 if (IS_ERR(bsp_priv->grf)) { 714 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 715 return; 716 } 717 718 if (speed == 10) { 719 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 720 RK3366_GMAC_RMII_CLK_2_5M | 721 RK3366_GMAC_SPEED_10M); 722 } else if (speed == 100) { 723 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 724 RK3366_GMAC_RMII_CLK_25M | 725 RK3366_GMAC_SPEED_100M); 726 } else { 727 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 728 } 729 } 730 731 static const struct rk_gmac_ops rk3366_ops = { 732 .set_to_rgmii = rk3366_set_to_rgmii, 733 .set_to_rmii = rk3366_set_to_rmii, 734 .set_rgmii_speed = rk3366_set_rgmii_speed, 735 .set_rmii_speed = rk3366_set_rmii_speed, 736 }; 737 738 #define RK3368_GRF_SOC_CON15 0x043c 739 #define RK3368_GRF_SOC_CON16 0x0440 740 741 /* RK3368_GRF_SOC_CON15 */ 742 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 743 GRF_CLR_BIT(11)) 744 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 745 GRF_BIT(11)) 746 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 747 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 748 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 749 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 750 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 751 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 752 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 753 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 754 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 755 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 756 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 757 758 /* RK3368_GRF_SOC_CON16 */ 759 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 760 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 761 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 762 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 763 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 764 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 765 766 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 767 int tx_delay, int rx_delay) 768 { 769 struct device *dev = &bsp_priv->pdev->dev; 770 771 if (IS_ERR(bsp_priv->grf)) { 772 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 773 return; 774 } 775 776 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 777 RK3368_GMAC_PHY_INTF_SEL_RGMII | 778 RK3368_GMAC_RMII_MODE_CLR); 779 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 780 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 781 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | 782 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); 783 } 784 785 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 786 { 787 struct device *dev = &bsp_priv->pdev->dev; 788 789 if (IS_ERR(bsp_priv->grf)) { 790 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 791 return; 792 } 793 794 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 795 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); 796 } 797 798 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 799 { 800 struct device *dev = &bsp_priv->pdev->dev; 801 802 if (IS_ERR(bsp_priv->grf)) { 803 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 804 return; 805 } 806 807 if (speed == 10) 808 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 809 RK3368_GMAC_CLK_2_5M); 810 else if (speed == 100) 811 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 812 RK3368_GMAC_CLK_25M); 813 else if (speed == 1000) 814 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 815 RK3368_GMAC_CLK_125M); 816 else 817 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 818 } 819 820 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 821 { 822 struct device *dev = &bsp_priv->pdev->dev; 823 824 if (IS_ERR(bsp_priv->grf)) { 825 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 826 return; 827 } 828 829 if (speed == 10) { 830 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 831 RK3368_GMAC_RMII_CLK_2_5M | 832 RK3368_GMAC_SPEED_10M); 833 } else if (speed == 100) { 834 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 835 RK3368_GMAC_RMII_CLK_25M | 836 RK3368_GMAC_SPEED_100M); 837 } else { 838 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 839 } 840 } 841 842 static const struct rk_gmac_ops rk3368_ops = { 843 .set_to_rgmii = rk3368_set_to_rgmii, 844 .set_to_rmii = rk3368_set_to_rmii, 845 .set_rgmii_speed = rk3368_set_rgmii_speed, 846 .set_rmii_speed = rk3368_set_rmii_speed, 847 }; 848 849 #define RK3399_GRF_SOC_CON5 0xc214 850 #define RK3399_GRF_SOC_CON6 0xc218 851 852 /* RK3399_GRF_SOC_CON5 */ 853 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ 854 GRF_CLR_BIT(11)) 855 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ 856 GRF_BIT(11)) 857 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 858 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 859 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 860 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 861 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 862 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 863 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) 864 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) 865 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) 866 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 867 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 868 869 /* RK3399_GRF_SOC_CON6 */ 870 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) 871 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) 872 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 873 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 874 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) 875 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 876 877 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 878 int tx_delay, int rx_delay) 879 { 880 struct device *dev = &bsp_priv->pdev->dev; 881 882 if (IS_ERR(bsp_priv->grf)) { 883 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 884 return; 885 } 886 887 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 888 RK3399_GMAC_PHY_INTF_SEL_RGMII | 889 RK3399_GMAC_RMII_MODE_CLR); 890 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 891 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 892 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | 893 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); 894 } 895 896 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 897 { 898 struct device *dev = &bsp_priv->pdev->dev; 899 900 if (IS_ERR(bsp_priv->grf)) { 901 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 902 return; 903 } 904 905 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 906 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); 907 } 908 909 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 910 { 911 struct device *dev = &bsp_priv->pdev->dev; 912 913 if (IS_ERR(bsp_priv->grf)) { 914 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 915 return; 916 } 917 918 if (speed == 10) 919 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 920 RK3399_GMAC_CLK_2_5M); 921 else if (speed == 100) 922 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 923 RK3399_GMAC_CLK_25M); 924 else if (speed == 1000) 925 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 926 RK3399_GMAC_CLK_125M); 927 else 928 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 929 } 930 931 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 932 { 933 struct device *dev = &bsp_priv->pdev->dev; 934 935 if (IS_ERR(bsp_priv->grf)) { 936 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 937 return; 938 } 939 940 if (speed == 10) { 941 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 942 RK3399_GMAC_RMII_CLK_2_5M | 943 RK3399_GMAC_SPEED_10M); 944 } else if (speed == 100) { 945 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 946 RK3399_GMAC_RMII_CLK_25M | 947 RK3399_GMAC_SPEED_100M); 948 } else { 949 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 950 } 951 } 952 953 static const struct rk_gmac_ops rk3399_ops = { 954 .set_to_rgmii = rk3399_set_to_rgmii, 955 .set_to_rmii = rk3399_set_to_rmii, 956 .set_rgmii_speed = rk3399_set_rgmii_speed, 957 .set_rmii_speed = rk3399_set_rmii_speed, 958 }; 959 960 #define RV1108_GRF_GMAC_CON0 0X0900 961 962 /* RV1108_GRF_GMAC_CON0 */ 963 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ 964 GRF_BIT(6)) 965 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 966 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 967 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 968 #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 969 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 970 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 971 972 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 973 { 974 struct device *dev = &bsp_priv->pdev->dev; 975 976 if (IS_ERR(bsp_priv->grf)) { 977 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 978 return; 979 } 980 981 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 982 RV1108_GMAC_PHY_INTF_SEL_RMII); 983 } 984 985 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 986 { 987 struct device *dev = &bsp_priv->pdev->dev; 988 989 if (IS_ERR(bsp_priv->grf)) { 990 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 991 return; 992 } 993 994 if (speed == 10) { 995 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 996 RV1108_GMAC_RMII_CLK_2_5M | 997 RV1108_GMAC_SPEED_10M); 998 } else if (speed == 100) { 999 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1000 RV1108_GMAC_RMII_CLK_25M | 1001 RV1108_GMAC_SPEED_100M); 1002 } else { 1003 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 1004 } 1005 } 1006 1007 static const struct rk_gmac_ops rv1108_ops = { 1008 .set_to_rmii = rv1108_set_to_rmii, 1009 .set_rmii_speed = rv1108_set_rmii_speed, 1010 }; 1011 1012 #define RK_GRF_MACPHY_CON0 0xb00 1013 #define RK_GRF_MACPHY_CON1 0xb04 1014 #define RK_GRF_MACPHY_CON2 0xb08 1015 #define RK_GRF_MACPHY_CON3 0xb0c 1016 1017 #define RK_MACPHY_ENABLE GRF_BIT(0) 1018 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) 1019 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) 1020 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) 1021 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) 1022 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) 1023 1024 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) 1025 { 1026 if (priv->ops->integrated_phy_powerup) 1027 priv->ops->integrated_phy_powerup(priv); 1028 1029 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); 1030 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); 1031 1032 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); 1033 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); 1034 1035 if (priv->phy_reset) { 1036 /* PHY needs to be disabled before trying to reset it */ 1037 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1038 if (priv->phy_reset) 1039 reset_control_assert(priv->phy_reset); 1040 usleep_range(10, 20); 1041 if (priv->phy_reset) 1042 reset_control_deassert(priv->phy_reset); 1043 usleep_range(10, 20); 1044 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); 1045 msleep(30); 1046 } 1047 } 1048 1049 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) 1050 { 1051 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); 1052 if (priv->phy_reset) 1053 reset_control_assert(priv->phy_reset); 1054 } 1055 1056 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) 1057 { 1058 struct rk_priv_data *bsp_priv = plat->bsp_priv; 1059 struct device *dev = &bsp_priv->pdev->dev; 1060 int ret; 1061 1062 bsp_priv->clk_enabled = false; 1063 1064 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); 1065 if (IS_ERR(bsp_priv->mac_clk_rx)) 1066 dev_err(dev, "cannot get clock %s\n", 1067 "mac_clk_rx"); 1068 1069 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); 1070 if (IS_ERR(bsp_priv->mac_clk_tx)) 1071 dev_err(dev, "cannot get clock %s\n", 1072 "mac_clk_tx"); 1073 1074 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); 1075 if (IS_ERR(bsp_priv->aclk_mac)) 1076 dev_err(dev, "cannot get clock %s\n", 1077 "aclk_mac"); 1078 1079 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); 1080 if (IS_ERR(bsp_priv->pclk_mac)) 1081 dev_err(dev, "cannot get clock %s\n", 1082 "pclk_mac"); 1083 1084 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 1085 if (IS_ERR(bsp_priv->clk_mac)) 1086 dev_err(dev, "cannot get clock %s\n", 1087 "stmmaceth"); 1088 1089 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 1090 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); 1091 if (IS_ERR(bsp_priv->clk_mac_ref)) 1092 dev_err(dev, "cannot get clock %s\n", 1093 "clk_mac_ref"); 1094 1095 if (!bsp_priv->clock_input) { 1096 bsp_priv->clk_mac_refout = 1097 devm_clk_get(dev, "clk_mac_refout"); 1098 if (IS_ERR(bsp_priv->clk_mac_refout)) 1099 dev_err(dev, "cannot get clock %s\n", 1100 "clk_mac_refout"); 1101 } 1102 } 1103 1104 bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed"); 1105 if (IS_ERR(bsp_priv->clk_mac_speed)) 1106 dev_err(dev, "cannot get clock %s\n", "clk_mac_speed"); 1107 1108 if (bsp_priv->clock_input) { 1109 dev_info(dev, "clock input from PHY\n"); 1110 } else { 1111 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 1112 clk_set_rate(bsp_priv->clk_mac, 50000000); 1113 } 1114 1115 if (plat->phy_node && bsp_priv->integrated_phy) { 1116 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); 1117 if (IS_ERR(bsp_priv->clk_phy)) { 1118 ret = PTR_ERR(bsp_priv->clk_phy); 1119 dev_err(dev, "Cannot get PHY clock: %d\n", ret); 1120 return -EINVAL; 1121 } 1122 clk_set_rate(bsp_priv->clk_phy, 50000000); 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 1129 { 1130 int phy_iface = bsp_priv->phy_iface; 1131 1132 if (enable) { 1133 if (!bsp_priv->clk_enabled) { 1134 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1135 if (!IS_ERR(bsp_priv->mac_clk_rx)) 1136 clk_prepare_enable( 1137 bsp_priv->mac_clk_rx); 1138 1139 if (!IS_ERR(bsp_priv->clk_mac_ref)) 1140 clk_prepare_enable( 1141 bsp_priv->clk_mac_ref); 1142 1143 if (!IS_ERR(bsp_priv->clk_mac_refout)) 1144 clk_prepare_enable( 1145 bsp_priv->clk_mac_refout); 1146 } 1147 1148 if (!IS_ERR(bsp_priv->clk_phy)) 1149 clk_prepare_enable(bsp_priv->clk_phy); 1150 1151 if (!IS_ERR(bsp_priv->aclk_mac)) 1152 clk_prepare_enable(bsp_priv->aclk_mac); 1153 1154 if (!IS_ERR(bsp_priv->pclk_mac)) 1155 clk_prepare_enable(bsp_priv->pclk_mac); 1156 1157 if (!IS_ERR(bsp_priv->mac_clk_tx)) 1158 clk_prepare_enable(bsp_priv->mac_clk_tx); 1159 1160 if (!IS_ERR(bsp_priv->clk_mac_speed)) 1161 clk_prepare_enable(bsp_priv->clk_mac_speed); 1162 1163 /** 1164 * if (!IS_ERR(bsp_priv->clk_mac)) 1165 * clk_prepare_enable(bsp_priv->clk_mac); 1166 */ 1167 mdelay(5); 1168 bsp_priv->clk_enabled = true; 1169 } 1170 } else { 1171 if (bsp_priv->clk_enabled) { 1172 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 1173 clk_disable_unprepare(bsp_priv->mac_clk_rx); 1174 1175 clk_disable_unprepare(bsp_priv->clk_mac_ref); 1176 1177 clk_disable_unprepare(bsp_priv->clk_mac_refout); 1178 } 1179 1180 clk_disable_unprepare(bsp_priv->clk_phy); 1181 1182 clk_disable_unprepare(bsp_priv->aclk_mac); 1183 1184 clk_disable_unprepare(bsp_priv->pclk_mac); 1185 1186 clk_disable_unprepare(bsp_priv->mac_clk_tx); 1187 1188 clk_disable_unprepare(bsp_priv->clk_mac_speed); 1189 /** 1190 * if (!IS_ERR(bsp_priv->clk_mac)) 1191 * clk_disable_unprepare(bsp_priv->clk_mac); 1192 */ 1193 bsp_priv->clk_enabled = false; 1194 } 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 1201 { 1202 struct regulator *ldo = bsp_priv->regulator; 1203 int ret; 1204 struct device *dev = &bsp_priv->pdev->dev; 1205 1206 if (!ldo) { 1207 dev_err(dev, "no regulator found\n"); 1208 return -1; 1209 } 1210 1211 if (enable) { 1212 ret = regulator_enable(ldo); 1213 if (ret) 1214 dev_err(dev, "fail to enable phy-supply\n"); 1215 } else { 1216 ret = regulator_disable(ldo); 1217 if (ret) 1218 dev_err(dev, "fail to disable phy-supply\n"); 1219 } 1220 1221 return 0; 1222 } 1223 1224 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, 1225 struct plat_stmmacenet_data *plat, 1226 const struct rk_gmac_ops *ops) 1227 { 1228 struct rk_priv_data *bsp_priv; 1229 struct device *dev = &pdev->dev; 1230 int ret; 1231 const char *strings = NULL; 1232 int value; 1233 1234 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 1235 if (!bsp_priv) 1236 return ERR_PTR(-ENOMEM); 1237 1238 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); 1239 bsp_priv->ops = ops; 1240 1241 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); 1242 if (IS_ERR(bsp_priv->regulator)) { 1243 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { 1244 dev_err(dev, "phy regulator is not available yet, deferred probing\n"); 1245 return ERR_PTR(-EPROBE_DEFER); 1246 } 1247 dev_err(dev, "no regulator found\n"); 1248 bsp_priv->regulator = NULL; 1249 } 1250 1251 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 1252 if (ret) { 1253 dev_err(dev, "Can not read property: clock_in_out.\n"); 1254 bsp_priv->clock_input = true; 1255 } else { 1256 dev_info(dev, "clock input or output? (%s).\n", 1257 strings); 1258 if (!strcmp(strings, "input")) 1259 bsp_priv->clock_input = true; 1260 else 1261 bsp_priv->clock_input = false; 1262 } 1263 1264 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 1265 if (ret) { 1266 bsp_priv->tx_delay = 0x30; 1267 dev_err(dev, "Can not read property: tx_delay."); 1268 dev_err(dev, "set tx_delay to 0x%x\n", 1269 bsp_priv->tx_delay); 1270 } else { 1271 dev_info(dev, "TX delay(0x%x).\n", value); 1272 bsp_priv->tx_delay = value; 1273 } 1274 1275 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 1276 if (ret) { 1277 bsp_priv->rx_delay = 0x10; 1278 dev_err(dev, "Can not read property: rx_delay."); 1279 dev_err(dev, "set rx_delay to 0x%x\n", 1280 bsp_priv->rx_delay); 1281 } else { 1282 dev_info(dev, "RX delay(0x%x).\n", value); 1283 bsp_priv->rx_delay = value; 1284 } 1285 1286 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 1287 "rockchip,grf"); 1288 1289 if (plat->phy_node) { 1290 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, 1291 "phy-is-integrated"); 1292 if (bsp_priv->integrated_phy) { 1293 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); 1294 if (IS_ERR(bsp_priv->phy_reset)) { 1295 dev_err(&pdev->dev, "No PHY reset control found.\n"); 1296 bsp_priv->phy_reset = NULL; 1297 } 1298 } 1299 } 1300 dev_info(dev, "integrated PHY? (%s).\n", 1301 bsp_priv->integrated_phy ? "yes" : "no"); 1302 1303 bsp_priv->pdev = pdev; 1304 1305 return bsp_priv; 1306 } 1307 1308 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1309 { 1310 int ret; 1311 struct device *dev = &bsp_priv->pdev->dev; 1312 1313 ret = gmac_clk_enable(bsp_priv, true); 1314 if (ret) 1315 return ret; 1316 1317 /*rmii or rgmii*/ 1318 switch (bsp_priv->phy_iface) { 1319 case PHY_INTERFACE_MODE_RGMII: 1320 dev_info(dev, "init for RGMII\n"); 1321 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 1322 bsp_priv->rx_delay); 1323 break; 1324 case PHY_INTERFACE_MODE_RGMII_ID: 1325 dev_info(dev, "init for RGMII_ID\n"); 1326 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); 1327 break; 1328 case PHY_INTERFACE_MODE_RGMII_RXID: 1329 dev_info(dev, "init for RGMII_RXID\n"); 1330 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); 1331 break; 1332 case PHY_INTERFACE_MODE_RGMII_TXID: 1333 dev_info(dev, "init for RGMII_TXID\n"); 1334 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); 1335 break; 1336 case PHY_INTERFACE_MODE_RMII: 1337 dev_info(dev, "init for RMII\n"); 1338 bsp_priv->ops->set_to_rmii(bsp_priv); 1339 break; 1340 default: 1341 dev_err(dev, "NO interface defined!\n"); 1342 } 1343 1344 ret = phy_power_on(bsp_priv, true); 1345 if (ret) { 1346 gmac_clk_enable(bsp_priv, false); 1347 return ret; 1348 } 1349 1350 pm_runtime_enable(dev); 1351 pm_runtime_get_sync(dev); 1352 1353 if (bsp_priv->integrated_phy) 1354 rk_gmac_integrated_phy_powerup(bsp_priv); 1355 1356 return 0; 1357 } 1358 1359 static void rk_gmac_powerdown(struct rk_priv_data *gmac) 1360 { 1361 struct device *dev = &gmac->pdev->dev; 1362 1363 if (gmac->integrated_phy) 1364 rk_gmac_integrated_phy_powerdown(gmac); 1365 1366 pm_runtime_put_sync(dev); 1367 pm_runtime_disable(dev); 1368 1369 phy_power_on(gmac, false); 1370 gmac_clk_enable(gmac, false); 1371 } 1372 1373 static void rk_fix_speed(void *priv, unsigned int speed) 1374 { 1375 struct rk_priv_data *bsp_priv = priv; 1376 struct device *dev = &bsp_priv->pdev->dev; 1377 1378 switch (bsp_priv->phy_iface) { 1379 case PHY_INTERFACE_MODE_RGMII: 1380 case PHY_INTERFACE_MODE_RGMII_ID: 1381 case PHY_INTERFACE_MODE_RGMII_RXID: 1382 case PHY_INTERFACE_MODE_RGMII_TXID: 1383 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); 1384 break; 1385 case PHY_INTERFACE_MODE_RMII: 1386 bsp_priv->ops->set_rmii_speed(bsp_priv, speed); 1387 break; 1388 default: 1389 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 1390 } 1391 } 1392 1393 static int rk_gmac_probe(struct platform_device *pdev) 1394 { 1395 struct plat_stmmacenet_data *plat_dat; 1396 struct stmmac_resources stmmac_res; 1397 const struct rk_gmac_ops *data; 1398 int ret; 1399 1400 data = of_device_get_match_data(&pdev->dev); 1401 if (!data) { 1402 dev_err(&pdev->dev, "no of match data provided\n"); 1403 return -EINVAL; 1404 } 1405 1406 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 1407 if (ret) 1408 return ret; 1409 1410 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 1411 if (IS_ERR(plat_dat)) 1412 return PTR_ERR(plat_dat); 1413 1414 plat_dat->has_gmac = true; 1415 plat_dat->fix_mac_speed = rk_fix_speed; 1416 1417 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); 1418 if (IS_ERR(plat_dat->bsp_priv)) { 1419 ret = PTR_ERR(plat_dat->bsp_priv); 1420 goto err_remove_config_dt; 1421 } 1422 1423 ret = rk_gmac_clk_init(plat_dat); 1424 if (ret) 1425 return ret; 1426 1427 ret = rk_gmac_powerup(plat_dat->bsp_priv); 1428 if (ret) 1429 goto err_remove_config_dt; 1430 1431 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 1432 if (ret) 1433 goto err_gmac_powerdown; 1434 1435 return 0; 1436 1437 err_gmac_powerdown: 1438 rk_gmac_powerdown(plat_dat->bsp_priv); 1439 err_remove_config_dt: 1440 stmmac_remove_config_dt(pdev, plat_dat); 1441 1442 return ret; 1443 } 1444 1445 static int rk_gmac_remove(struct platform_device *pdev) 1446 { 1447 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); 1448 int ret = stmmac_dvr_remove(&pdev->dev); 1449 1450 rk_gmac_powerdown(bsp_priv); 1451 1452 return ret; 1453 } 1454 1455 #ifdef CONFIG_PM_SLEEP 1456 static int rk_gmac_suspend(struct device *dev) 1457 { 1458 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1459 int ret = stmmac_suspend(dev); 1460 1461 /* Keep the PHY up if we use Wake-on-Lan. */ 1462 if (!device_may_wakeup(dev)) { 1463 rk_gmac_powerdown(bsp_priv); 1464 bsp_priv->suspended = true; 1465 } 1466 1467 return ret; 1468 } 1469 1470 static int rk_gmac_resume(struct device *dev) 1471 { 1472 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); 1473 1474 /* The PHY was up for Wake-on-Lan. */ 1475 if (bsp_priv->suspended) { 1476 rk_gmac_powerup(bsp_priv); 1477 bsp_priv->suspended = false; 1478 } 1479 1480 return stmmac_resume(dev); 1481 } 1482 #endif /* CONFIG_PM_SLEEP */ 1483 1484 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); 1485 1486 static const struct of_device_id rk_gmac_dwmac_match[] = { 1487 { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, 1488 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, 1489 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, 1490 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, 1491 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, 1492 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, 1493 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, 1494 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, 1495 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, 1496 { } 1497 }; 1498 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); 1499 1500 static struct platform_driver rk_gmac_dwmac_driver = { 1501 .probe = rk_gmac_probe, 1502 .remove = rk_gmac_remove, 1503 .driver = { 1504 .name = "rk_gmac-dwmac", 1505 .pm = &rk_gmac_pm_ops, 1506 .of_match_table = rk_gmac_dwmac_match, 1507 }, 1508 }; 1509 module_platform_driver(rk_gmac_dwmac_driver); 1510 1511 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); 1512 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); 1513 MODULE_LICENSE("GPL"); 1514