1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3  * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4  *
5  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6  *
7  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
8  */
9 
10 #include <linux/stmmac.h>
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/phy.h>
14 #include <linux/of_net.h>
15 #include <linux/gpio.h>
16 #include <linux/module.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/delay.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
24 #include <linux/pm_runtime.h>
25 
26 #include "stmmac_platform.h"
27 
28 struct rk_priv_data;
29 struct rk_gmac_ops {
30 	void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
31 			     int tx_delay, int rx_delay);
32 	void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
33 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
34 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
35 	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
36 				    bool enable);
37 	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
38 	bool regs_valid;
39 	u32 regs[];
40 };
41 
42 struct rk_priv_data {
43 	struct platform_device *pdev;
44 	phy_interface_t phy_iface;
45 	int id;
46 	struct regulator *regulator;
47 	bool suspended;
48 	const struct rk_gmac_ops *ops;
49 
50 	bool clk_enabled;
51 	bool clock_input;
52 	bool integrated_phy;
53 
54 	struct clk *clk_mac;
55 	struct clk *gmac_clkin;
56 	struct clk *mac_clk_rx;
57 	struct clk *mac_clk_tx;
58 	struct clk *clk_mac_ref;
59 	struct clk *clk_mac_refout;
60 	struct clk *clk_mac_speed;
61 	struct clk *aclk_mac;
62 	struct clk *pclk_mac;
63 	struct clk *clk_phy;
64 
65 	struct reset_control *phy_reset;
66 
67 	int tx_delay;
68 	int rx_delay;
69 
70 	struct regmap *grf;
71 	struct regmap *php_grf;
72 };
73 
74 #define HIWORD_UPDATE(val, mask, shift) \
75 		((val) << (shift) | (mask) << ((shift) + 16))
76 
77 #define GRF_BIT(nr)	(BIT(nr) | BIT(nr+16))
78 #define GRF_CLR_BIT(nr)	(BIT(nr+16))
79 
80 #define DELAY_ENABLE(soc, tx, rx) \
81 	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
82 	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
83 
84 #define PX30_GRF_GMAC_CON1		0x0904
85 
86 /* PX30_GRF_GMAC_CON1 */
87 #define PX30_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
88 					 GRF_BIT(6))
89 #define PX30_GMAC_SPEED_10M		GRF_CLR_BIT(2)
90 #define PX30_GMAC_SPEED_100M		GRF_BIT(2)
91 
92 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
93 {
94 	struct device *dev = &bsp_priv->pdev->dev;
95 
96 	if (IS_ERR(bsp_priv->grf)) {
97 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
98 		return;
99 	}
100 
101 	regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
102 		     PX30_GMAC_PHY_INTF_SEL_RMII);
103 }
104 
105 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
106 {
107 	struct device *dev = &bsp_priv->pdev->dev;
108 	int ret;
109 
110 	if (IS_ERR(bsp_priv->clk_mac_speed)) {
111 		dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
112 		return;
113 	}
114 
115 	if (speed == 10) {
116 		regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
117 			     PX30_GMAC_SPEED_10M);
118 
119 		ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
120 		if (ret)
121 			dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
122 				__func__, ret);
123 	} else if (speed == 100) {
124 		regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
125 			     PX30_GMAC_SPEED_100M);
126 
127 		ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
128 		if (ret)
129 			dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
130 				__func__, ret);
131 
132 	} else {
133 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
134 	}
135 }
136 
137 static const struct rk_gmac_ops px30_ops = {
138 	.set_to_rmii = px30_set_to_rmii,
139 	.set_rmii_speed = px30_set_rmii_speed,
140 };
141 
142 #define RK3128_GRF_MAC_CON0	0x0168
143 #define RK3128_GRF_MAC_CON1	0x016c
144 
145 /* RK3128_GRF_MAC_CON0 */
146 #define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
147 #define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
148 #define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
149 #define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
150 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
151 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
152 
153 /* RK3128_GRF_MAC_CON1 */
154 #define RK3128_GMAC_PHY_INTF_SEL_RGMII	\
155 		(GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
156 #define RK3128_GMAC_PHY_INTF_SEL_RMII	\
157 		(GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
158 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
159 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
160 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
161 #define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
162 #define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
163 #define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
164 #define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
165 #define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
166 #define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
167 #define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
168 #define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
169 
170 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
171 				int tx_delay, int rx_delay)
172 {
173 	struct device *dev = &bsp_priv->pdev->dev;
174 
175 	if (IS_ERR(bsp_priv->grf)) {
176 		dev_err(dev, "Missing rockchip,grf property\n");
177 		return;
178 	}
179 
180 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
181 		     RK3128_GMAC_PHY_INTF_SEL_RGMII |
182 		     RK3128_GMAC_RMII_MODE_CLR);
183 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
184 		     DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
185 		     RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
186 		     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
187 }
188 
189 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
190 {
191 	struct device *dev = &bsp_priv->pdev->dev;
192 
193 	if (IS_ERR(bsp_priv->grf)) {
194 		dev_err(dev, "Missing rockchip,grf property\n");
195 		return;
196 	}
197 
198 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
199 		     RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
200 }
201 
202 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
203 {
204 	struct device *dev = &bsp_priv->pdev->dev;
205 
206 	if (IS_ERR(bsp_priv->grf)) {
207 		dev_err(dev, "Missing rockchip,grf property\n");
208 		return;
209 	}
210 
211 	if (speed == 10)
212 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
213 			     RK3128_GMAC_CLK_2_5M);
214 	else if (speed == 100)
215 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
216 			     RK3128_GMAC_CLK_25M);
217 	else if (speed == 1000)
218 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
219 			     RK3128_GMAC_CLK_125M);
220 	else
221 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
222 }
223 
224 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
225 {
226 	struct device *dev = &bsp_priv->pdev->dev;
227 
228 	if (IS_ERR(bsp_priv->grf)) {
229 		dev_err(dev, "Missing rockchip,grf property\n");
230 		return;
231 	}
232 
233 	if (speed == 10) {
234 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
235 			     RK3128_GMAC_RMII_CLK_2_5M |
236 			     RK3128_GMAC_SPEED_10M);
237 	} else if (speed == 100) {
238 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
239 			     RK3128_GMAC_RMII_CLK_25M |
240 			     RK3128_GMAC_SPEED_100M);
241 	} else {
242 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
243 	}
244 }
245 
246 static const struct rk_gmac_ops rk3128_ops = {
247 	.set_to_rgmii = rk3128_set_to_rgmii,
248 	.set_to_rmii = rk3128_set_to_rmii,
249 	.set_rgmii_speed = rk3128_set_rgmii_speed,
250 	.set_rmii_speed = rk3128_set_rmii_speed,
251 };
252 
253 #define RK3228_GRF_MAC_CON0	0x0900
254 #define RK3228_GRF_MAC_CON1	0x0904
255 
256 #define RK3228_GRF_CON_MUX	0x50
257 
258 /* RK3228_GRF_MAC_CON0 */
259 #define RK3228_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
260 #define RK3228_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
261 
262 /* RK3228_GRF_MAC_CON1 */
263 #define RK3228_GMAC_PHY_INTF_SEL_RGMII	\
264 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
265 #define RK3228_GMAC_PHY_INTF_SEL_RMII	\
266 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
267 #define RK3228_GMAC_FLOW_CTRL		GRF_BIT(3)
268 #define RK3228_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
269 #define RK3228_GMAC_SPEED_10M		GRF_CLR_BIT(2)
270 #define RK3228_GMAC_SPEED_100M		GRF_BIT(2)
271 #define RK3228_GMAC_RMII_CLK_25M	GRF_BIT(7)
272 #define RK3228_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(7)
273 #define RK3228_GMAC_CLK_125M		(GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
274 #define RK3228_GMAC_CLK_25M		(GRF_BIT(8) | GRF_BIT(9))
275 #define RK3228_GMAC_CLK_2_5M		(GRF_CLR_BIT(8) | GRF_BIT(9))
276 #define RK3228_GMAC_RMII_MODE		GRF_BIT(10)
277 #define RK3228_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(10)
278 #define RK3228_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(0)
279 #define RK3228_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
280 #define RK3228_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(1)
281 #define RK3228_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
282 
283 /* RK3228_GRF_COM_MUX */
284 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY	GRF_BIT(15)
285 
286 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
287 				int tx_delay, int rx_delay)
288 {
289 	struct device *dev = &bsp_priv->pdev->dev;
290 
291 	if (IS_ERR(bsp_priv->grf)) {
292 		dev_err(dev, "Missing rockchip,grf property\n");
293 		return;
294 	}
295 
296 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
297 		     RK3228_GMAC_PHY_INTF_SEL_RGMII |
298 		     RK3228_GMAC_RMII_MODE_CLR |
299 		     DELAY_ENABLE(RK3228, tx_delay, rx_delay));
300 
301 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
302 		     RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
303 		     RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
304 }
305 
306 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
307 {
308 	struct device *dev = &bsp_priv->pdev->dev;
309 
310 	if (IS_ERR(bsp_priv->grf)) {
311 		dev_err(dev, "Missing rockchip,grf property\n");
312 		return;
313 	}
314 
315 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
316 		     RK3228_GMAC_PHY_INTF_SEL_RMII |
317 		     RK3228_GMAC_RMII_MODE);
318 
319 	/* set MAC to RMII mode */
320 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
321 }
322 
323 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
324 {
325 	struct device *dev = &bsp_priv->pdev->dev;
326 
327 	if (IS_ERR(bsp_priv->grf)) {
328 		dev_err(dev, "Missing rockchip,grf property\n");
329 		return;
330 	}
331 
332 	if (speed == 10)
333 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
334 			     RK3228_GMAC_CLK_2_5M);
335 	else if (speed == 100)
336 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
337 			     RK3228_GMAC_CLK_25M);
338 	else if (speed == 1000)
339 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
340 			     RK3228_GMAC_CLK_125M);
341 	else
342 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
343 }
344 
345 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
346 {
347 	struct device *dev = &bsp_priv->pdev->dev;
348 
349 	if (IS_ERR(bsp_priv->grf)) {
350 		dev_err(dev, "Missing rockchip,grf property\n");
351 		return;
352 	}
353 
354 	if (speed == 10)
355 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
356 			     RK3228_GMAC_RMII_CLK_2_5M |
357 			     RK3228_GMAC_SPEED_10M);
358 	else if (speed == 100)
359 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
360 			     RK3228_GMAC_RMII_CLK_25M |
361 			     RK3228_GMAC_SPEED_100M);
362 	else
363 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
364 }
365 
366 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
367 {
368 	regmap_write(priv->grf, RK3228_GRF_CON_MUX,
369 		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
370 }
371 
372 static const struct rk_gmac_ops rk3228_ops = {
373 	.set_to_rgmii = rk3228_set_to_rgmii,
374 	.set_to_rmii = rk3228_set_to_rmii,
375 	.set_rgmii_speed = rk3228_set_rgmii_speed,
376 	.set_rmii_speed = rk3228_set_rmii_speed,
377 	.integrated_phy_powerup =  rk3228_integrated_phy_powerup,
378 };
379 
380 #define RK3288_GRF_SOC_CON1	0x0248
381 #define RK3288_GRF_SOC_CON3	0x0250
382 
383 /*RK3288_GRF_SOC_CON1*/
384 #define RK3288_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(6) | GRF_CLR_BIT(7) | \
385 					 GRF_CLR_BIT(8))
386 #define RK3288_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
387 					 GRF_BIT(8))
388 #define RK3288_GMAC_FLOW_CTRL		GRF_BIT(9)
389 #define RK3288_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(9)
390 #define RK3288_GMAC_SPEED_10M		GRF_CLR_BIT(10)
391 #define RK3288_GMAC_SPEED_100M		GRF_BIT(10)
392 #define RK3288_GMAC_RMII_CLK_25M	GRF_BIT(11)
393 #define RK3288_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(11)
394 #define RK3288_GMAC_CLK_125M		(GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
395 #define RK3288_GMAC_CLK_25M		(GRF_BIT(12) | GRF_BIT(13))
396 #define RK3288_GMAC_CLK_2_5M		(GRF_CLR_BIT(12) | GRF_BIT(13))
397 #define RK3288_GMAC_RMII_MODE		GRF_BIT(14)
398 #define RK3288_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(14)
399 
400 /*RK3288_GRF_SOC_CON3*/
401 #define RK3288_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)
402 #define RK3288_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)
403 #define RK3288_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
404 #define RK3288_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
405 #define RK3288_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
406 #define RK3288_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
407 
408 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
409 				int tx_delay, int rx_delay)
410 {
411 	struct device *dev = &bsp_priv->pdev->dev;
412 
413 	if (IS_ERR(bsp_priv->grf)) {
414 		dev_err(dev, "Missing rockchip,grf property\n");
415 		return;
416 	}
417 
418 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
419 		     RK3288_GMAC_PHY_INTF_SEL_RGMII |
420 		     RK3288_GMAC_RMII_MODE_CLR);
421 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
422 		     DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
423 		     RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
424 		     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
425 }
426 
427 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
428 {
429 	struct device *dev = &bsp_priv->pdev->dev;
430 
431 	if (IS_ERR(bsp_priv->grf)) {
432 		dev_err(dev, "Missing rockchip,grf property\n");
433 		return;
434 	}
435 
436 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
437 		     RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
438 }
439 
440 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
441 {
442 	struct device *dev = &bsp_priv->pdev->dev;
443 
444 	if (IS_ERR(bsp_priv->grf)) {
445 		dev_err(dev, "Missing rockchip,grf property\n");
446 		return;
447 	}
448 
449 	if (speed == 10)
450 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
451 			     RK3288_GMAC_CLK_2_5M);
452 	else if (speed == 100)
453 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
454 			     RK3288_GMAC_CLK_25M);
455 	else if (speed == 1000)
456 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
457 			     RK3288_GMAC_CLK_125M);
458 	else
459 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
460 }
461 
462 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
463 {
464 	struct device *dev = &bsp_priv->pdev->dev;
465 
466 	if (IS_ERR(bsp_priv->grf)) {
467 		dev_err(dev, "Missing rockchip,grf property\n");
468 		return;
469 	}
470 
471 	if (speed == 10) {
472 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
473 			     RK3288_GMAC_RMII_CLK_2_5M |
474 			     RK3288_GMAC_SPEED_10M);
475 	} else if (speed == 100) {
476 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
477 			     RK3288_GMAC_RMII_CLK_25M |
478 			     RK3288_GMAC_SPEED_100M);
479 	} else {
480 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
481 	}
482 }
483 
484 static const struct rk_gmac_ops rk3288_ops = {
485 	.set_to_rgmii = rk3288_set_to_rgmii,
486 	.set_to_rmii = rk3288_set_to_rmii,
487 	.set_rgmii_speed = rk3288_set_rgmii_speed,
488 	.set_rmii_speed = rk3288_set_rmii_speed,
489 };
490 
491 #define RK3308_GRF_MAC_CON0		0x04a0
492 
493 /* RK3308_GRF_MAC_CON0 */
494 #define RK3308_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
495 					GRF_BIT(4))
496 #define RK3308_GMAC_FLOW_CTRL		GRF_BIT(3)
497 #define RK3308_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
498 #define RK3308_GMAC_SPEED_10M		GRF_CLR_BIT(0)
499 #define RK3308_GMAC_SPEED_100M		GRF_BIT(0)
500 
501 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
502 {
503 	struct device *dev = &bsp_priv->pdev->dev;
504 
505 	if (IS_ERR(bsp_priv->grf)) {
506 		dev_err(dev, "Missing rockchip,grf property\n");
507 		return;
508 	}
509 
510 	regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
511 		     RK3308_GMAC_PHY_INTF_SEL_RMII);
512 }
513 
514 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
515 {
516 	struct device *dev = &bsp_priv->pdev->dev;
517 
518 	if (IS_ERR(bsp_priv->grf)) {
519 		dev_err(dev, "Missing rockchip,grf property\n");
520 		return;
521 	}
522 
523 	if (speed == 10) {
524 		regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
525 			     RK3308_GMAC_SPEED_10M);
526 	} else if (speed == 100) {
527 		regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
528 			     RK3308_GMAC_SPEED_100M);
529 	} else {
530 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
531 	}
532 }
533 
534 static const struct rk_gmac_ops rk3308_ops = {
535 	.set_to_rmii = rk3308_set_to_rmii,
536 	.set_rmii_speed = rk3308_set_rmii_speed,
537 };
538 
539 #define RK3328_GRF_MAC_CON0	0x0900
540 #define RK3328_GRF_MAC_CON1	0x0904
541 #define RK3328_GRF_MAC_CON2	0x0908
542 #define RK3328_GRF_MACPHY_CON1	0xb04
543 
544 /* RK3328_GRF_MAC_CON0 */
545 #define RK3328_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
546 #define RK3328_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
547 
548 /* RK3328_GRF_MAC_CON1 */
549 #define RK3328_GMAC_PHY_INTF_SEL_RGMII	\
550 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
551 #define RK3328_GMAC_PHY_INTF_SEL_RMII	\
552 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
553 #define RK3328_GMAC_FLOW_CTRL		GRF_BIT(3)
554 #define RK3328_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
555 #define RK3328_GMAC_SPEED_10M		GRF_CLR_BIT(2)
556 #define RK3328_GMAC_SPEED_100M		GRF_BIT(2)
557 #define RK3328_GMAC_RMII_CLK_25M	GRF_BIT(7)
558 #define RK3328_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(7)
559 #define RK3328_GMAC_CLK_125M		(GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
560 #define RK3328_GMAC_CLK_25M		(GRF_BIT(11) | GRF_BIT(12))
561 #define RK3328_GMAC_CLK_2_5M		(GRF_CLR_BIT(11) | GRF_BIT(12))
562 #define RK3328_GMAC_RMII_MODE		GRF_BIT(9)
563 #define RK3328_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(9)
564 #define RK3328_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(0)
565 #define RK3328_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
566 #define RK3328_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(1)
567 #define RK3328_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
568 
569 /* RK3328_GRF_MACPHY_CON1 */
570 #define RK3328_MACPHY_RMII_MODE		GRF_BIT(9)
571 
572 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
573 				int tx_delay, int rx_delay)
574 {
575 	struct device *dev = &bsp_priv->pdev->dev;
576 
577 	if (IS_ERR(bsp_priv->grf)) {
578 		dev_err(dev, "Missing rockchip,grf property\n");
579 		return;
580 	}
581 
582 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
583 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
584 		     RK3328_GMAC_RMII_MODE_CLR |
585 		     RK3328_GMAC_RXCLK_DLY_ENABLE |
586 		     RK3328_GMAC_TXCLK_DLY_ENABLE);
587 
588 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
589 		     RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
590 		     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
591 }
592 
593 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
594 {
595 	struct device *dev = &bsp_priv->pdev->dev;
596 	unsigned int reg;
597 
598 	if (IS_ERR(bsp_priv->grf)) {
599 		dev_err(dev, "Missing rockchip,grf property\n");
600 		return;
601 	}
602 
603 	reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
604 		  RK3328_GRF_MAC_CON1;
605 
606 	regmap_write(bsp_priv->grf, reg,
607 		     RK3328_GMAC_PHY_INTF_SEL_RMII |
608 		     RK3328_GMAC_RMII_MODE);
609 }
610 
611 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
612 {
613 	struct device *dev = &bsp_priv->pdev->dev;
614 
615 	if (IS_ERR(bsp_priv->grf)) {
616 		dev_err(dev, "Missing rockchip,grf property\n");
617 		return;
618 	}
619 
620 	if (speed == 10)
621 		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
622 			     RK3328_GMAC_CLK_2_5M);
623 	else if (speed == 100)
624 		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
625 			     RK3328_GMAC_CLK_25M);
626 	else if (speed == 1000)
627 		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
628 			     RK3328_GMAC_CLK_125M);
629 	else
630 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
631 }
632 
633 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
634 {
635 	struct device *dev = &bsp_priv->pdev->dev;
636 	unsigned int reg;
637 
638 	if (IS_ERR(bsp_priv->grf)) {
639 		dev_err(dev, "Missing rockchip,grf property\n");
640 		return;
641 	}
642 
643 	reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
644 		  RK3328_GRF_MAC_CON1;
645 
646 	if (speed == 10)
647 		regmap_write(bsp_priv->grf, reg,
648 			     RK3328_GMAC_RMII_CLK_2_5M |
649 			     RK3328_GMAC_SPEED_10M);
650 	else if (speed == 100)
651 		regmap_write(bsp_priv->grf, reg,
652 			     RK3328_GMAC_RMII_CLK_25M |
653 			     RK3328_GMAC_SPEED_100M);
654 	else
655 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
656 }
657 
658 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
659 {
660 	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
661 		     RK3328_MACPHY_RMII_MODE);
662 }
663 
664 static const struct rk_gmac_ops rk3328_ops = {
665 	.set_to_rgmii = rk3328_set_to_rgmii,
666 	.set_to_rmii = rk3328_set_to_rmii,
667 	.set_rgmii_speed = rk3328_set_rgmii_speed,
668 	.set_rmii_speed = rk3328_set_rmii_speed,
669 	.integrated_phy_powerup =  rk3328_integrated_phy_powerup,
670 };
671 
672 #define RK3366_GRF_SOC_CON6	0x0418
673 #define RK3366_GRF_SOC_CON7	0x041c
674 
675 /* RK3366_GRF_SOC_CON6 */
676 #define RK3366_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \
677 					 GRF_CLR_BIT(11))
678 #define RK3366_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
679 					 GRF_BIT(11))
680 #define RK3366_GMAC_FLOW_CTRL		GRF_BIT(8)
681 #define RK3366_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)
682 #define RK3366_GMAC_SPEED_10M		GRF_CLR_BIT(7)
683 #define RK3366_GMAC_SPEED_100M		GRF_BIT(7)
684 #define RK3366_GMAC_RMII_CLK_25M	GRF_BIT(3)
685 #define RK3366_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)
686 #define RK3366_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
687 #define RK3366_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))
688 #define RK3366_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))
689 #define RK3366_GMAC_RMII_MODE		GRF_BIT(6)
690 #define RK3366_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)
691 
692 /* RK3366_GRF_SOC_CON7 */
693 #define RK3366_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)
694 #define RK3366_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)
695 #define RK3366_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
696 #define RK3366_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
697 #define RK3366_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
698 #define RK3366_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
699 
700 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
701 				int tx_delay, int rx_delay)
702 {
703 	struct device *dev = &bsp_priv->pdev->dev;
704 
705 	if (IS_ERR(bsp_priv->grf)) {
706 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
707 		return;
708 	}
709 
710 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
711 		     RK3366_GMAC_PHY_INTF_SEL_RGMII |
712 		     RK3366_GMAC_RMII_MODE_CLR);
713 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
714 		     DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
715 		     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
716 		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
717 }
718 
719 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
720 {
721 	struct device *dev = &bsp_priv->pdev->dev;
722 
723 	if (IS_ERR(bsp_priv->grf)) {
724 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
725 		return;
726 	}
727 
728 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
729 		     RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
730 }
731 
732 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
733 {
734 	struct device *dev = &bsp_priv->pdev->dev;
735 
736 	if (IS_ERR(bsp_priv->grf)) {
737 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
738 		return;
739 	}
740 
741 	if (speed == 10)
742 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
743 			     RK3366_GMAC_CLK_2_5M);
744 	else if (speed == 100)
745 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
746 			     RK3366_GMAC_CLK_25M);
747 	else if (speed == 1000)
748 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
749 			     RK3366_GMAC_CLK_125M);
750 	else
751 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
752 }
753 
754 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
755 {
756 	struct device *dev = &bsp_priv->pdev->dev;
757 
758 	if (IS_ERR(bsp_priv->grf)) {
759 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
760 		return;
761 	}
762 
763 	if (speed == 10) {
764 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
765 			     RK3366_GMAC_RMII_CLK_2_5M |
766 			     RK3366_GMAC_SPEED_10M);
767 	} else if (speed == 100) {
768 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
769 			     RK3366_GMAC_RMII_CLK_25M |
770 			     RK3366_GMAC_SPEED_100M);
771 	} else {
772 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
773 	}
774 }
775 
776 static const struct rk_gmac_ops rk3366_ops = {
777 	.set_to_rgmii = rk3366_set_to_rgmii,
778 	.set_to_rmii = rk3366_set_to_rmii,
779 	.set_rgmii_speed = rk3366_set_rgmii_speed,
780 	.set_rmii_speed = rk3366_set_rmii_speed,
781 };
782 
783 #define RK3368_GRF_SOC_CON15	0x043c
784 #define RK3368_GRF_SOC_CON16	0x0440
785 
786 /* RK3368_GRF_SOC_CON15 */
787 #define RK3368_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \
788 					 GRF_CLR_BIT(11))
789 #define RK3368_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
790 					 GRF_BIT(11))
791 #define RK3368_GMAC_FLOW_CTRL		GRF_BIT(8)
792 #define RK3368_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)
793 #define RK3368_GMAC_SPEED_10M		GRF_CLR_BIT(7)
794 #define RK3368_GMAC_SPEED_100M		GRF_BIT(7)
795 #define RK3368_GMAC_RMII_CLK_25M	GRF_BIT(3)
796 #define RK3368_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)
797 #define RK3368_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
798 #define RK3368_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))
799 #define RK3368_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))
800 #define RK3368_GMAC_RMII_MODE		GRF_BIT(6)
801 #define RK3368_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)
802 
803 /* RK3368_GRF_SOC_CON16 */
804 #define RK3368_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)
805 #define RK3368_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)
806 #define RK3368_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
807 #define RK3368_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
808 #define RK3368_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
809 #define RK3368_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
810 
811 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
812 				int tx_delay, int rx_delay)
813 {
814 	struct device *dev = &bsp_priv->pdev->dev;
815 
816 	if (IS_ERR(bsp_priv->grf)) {
817 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
818 		return;
819 	}
820 
821 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
822 		     RK3368_GMAC_PHY_INTF_SEL_RGMII |
823 		     RK3368_GMAC_RMII_MODE_CLR);
824 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
825 		     DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
826 		     RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
827 		     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
828 }
829 
830 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
831 {
832 	struct device *dev = &bsp_priv->pdev->dev;
833 
834 	if (IS_ERR(bsp_priv->grf)) {
835 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
836 		return;
837 	}
838 
839 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
840 		     RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
841 }
842 
843 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
844 {
845 	struct device *dev = &bsp_priv->pdev->dev;
846 
847 	if (IS_ERR(bsp_priv->grf)) {
848 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
849 		return;
850 	}
851 
852 	if (speed == 10)
853 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
854 			     RK3368_GMAC_CLK_2_5M);
855 	else if (speed == 100)
856 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
857 			     RK3368_GMAC_CLK_25M);
858 	else if (speed == 1000)
859 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
860 			     RK3368_GMAC_CLK_125M);
861 	else
862 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
863 }
864 
865 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
866 {
867 	struct device *dev = &bsp_priv->pdev->dev;
868 
869 	if (IS_ERR(bsp_priv->grf)) {
870 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
871 		return;
872 	}
873 
874 	if (speed == 10) {
875 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
876 			     RK3368_GMAC_RMII_CLK_2_5M |
877 			     RK3368_GMAC_SPEED_10M);
878 	} else if (speed == 100) {
879 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
880 			     RK3368_GMAC_RMII_CLK_25M |
881 			     RK3368_GMAC_SPEED_100M);
882 	} else {
883 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
884 	}
885 }
886 
887 static const struct rk_gmac_ops rk3368_ops = {
888 	.set_to_rgmii = rk3368_set_to_rgmii,
889 	.set_to_rmii = rk3368_set_to_rmii,
890 	.set_rgmii_speed = rk3368_set_rgmii_speed,
891 	.set_rmii_speed = rk3368_set_rmii_speed,
892 };
893 
894 #define RK3399_GRF_SOC_CON5	0xc214
895 #define RK3399_GRF_SOC_CON6	0xc218
896 
897 /* RK3399_GRF_SOC_CON5 */
898 #define RK3399_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \
899 					 GRF_CLR_BIT(11))
900 #define RK3399_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
901 					 GRF_BIT(11))
902 #define RK3399_GMAC_FLOW_CTRL		GRF_BIT(8)
903 #define RK3399_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)
904 #define RK3399_GMAC_SPEED_10M		GRF_CLR_BIT(7)
905 #define RK3399_GMAC_SPEED_100M		GRF_BIT(7)
906 #define RK3399_GMAC_RMII_CLK_25M	GRF_BIT(3)
907 #define RK3399_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)
908 #define RK3399_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
909 #define RK3399_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))
910 #define RK3399_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))
911 #define RK3399_GMAC_RMII_MODE		GRF_BIT(6)
912 #define RK3399_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)
913 
914 /* RK3399_GRF_SOC_CON6 */
915 #define RK3399_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)
916 #define RK3399_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)
917 #define RK3399_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
918 #define RK3399_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
919 #define RK3399_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
920 #define RK3399_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
921 
922 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
923 				int tx_delay, int rx_delay)
924 {
925 	struct device *dev = &bsp_priv->pdev->dev;
926 
927 	if (IS_ERR(bsp_priv->grf)) {
928 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
929 		return;
930 	}
931 
932 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
933 		     RK3399_GMAC_PHY_INTF_SEL_RGMII |
934 		     RK3399_GMAC_RMII_MODE_CLR);
935 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
936 		     DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
937 		     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
938 		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
939 }
940 
941 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
942 {
943 	struct device *dev = &bsp_priv->pdev->dev;
944 
945 	if (IS_ERR(bsp_priv->grf)) {
946 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
947 		return;
948 	}
949 
950 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
951 		     RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
952 }
953 
954 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
955 {
956 	struct device *dev = &bsp_priv->pdev->dev;
957 
958 	if (IS_ERR(bsp_priv->grf)) {
959 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
960 		return;
961 	}
962 
963 	if (speed == 10)
964 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
965 			     RK3399_GMAC_CLK_2_5M);
966 	else if (speed == 100)
967 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
968 			     RK3399_GMAC_CLK_25M);
969 	else if (speed == 1000)
970 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
971 			     RK3399_GMAC_CLK_125M);
972 	else
973 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
974 }
975 
976 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
977 {
978 	struct device *dev = &bsp_priv->pdev->dev;
979 
980 	if (IS_ERR(bsp_priv->grf)) {
981 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
982 		return;
983 	}
984 
985 	if (speed == 10) {
986 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
987 			     RK3399_GMAC_RMII_CLK_2_5M |
988 			     RK3399_GMAC_SPEED_10M);
989 	} else if (speed == 100) {
990 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
991 			     RK3399_GMAC_RMII_CLK_25M |
992 			     RK3399_GMAC_SPEED_100M);
993 	} else {
994 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
995 	}
996 }
997 
998 static const struct rk_gmac_ops rk3399_ops = {
999 	.set_to_rgmii = rk3399_set_to_rgmii,
1000 	.set_to_rmii = rk3399_set_to_rmii,
1001 	.set_rgmii_speed = rk3399_set_rgmii_speed,
1002 	.set_rmii_speed = rk3399_set_rmii_speed,
1003 };
1004 
1005 #define RK3568_GRF_GMAC0_CON0		0x0380
1006 #define RK3568_GRF_GMAC0_CON1		0x0384
1007 #define RK3568_GRF_GMAC1_CON0		0x0388
1008 #define RK3568_GRF_GMAC1_CON1		0x038c
1009 
1010 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1011 #define RK3568_GMAC_PHY_INTF_SEL_RGMII	\
1012 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1013 #define RK3568_GMAC_PHY_INTF_SEL_RMII	\
1014 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1015 #define RK3568_GMAC_FLOW_CTRL			GRF_BIT(3)
1016 #define RK3568_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(3)
1017 #define RK3568_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1018 #define RK3568_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
1019 #define RK3568_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1020 #define RK3568_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)
1021 
1022 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1023 #define RK3568_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1024 #define RK3568_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1025 
1026 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1027 				int tx_delay, int rx_delay)
1028 {
1029 	struct device *dev = &bsp_priv->pdev->dev;
1030 	u32 con0, con1;
1031 
1032 	if (IS_ERR(bsp_priv->grf)) {
1033 		dev_err(dev, "Missing rockchip,grf property\n");
1034 		return;
1035 	}
1036 
1037 	con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1038 				     RK3568_GRF_GMAC0_CON0;
1039 	con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1040 				     RK3568_GRF_GMAC0_CON1;
1041 
1042 	regmap_write(bsp_priv->grf, con0,
1043 		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1044 		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1045 
1046 	regmap_write(bsp_priv->grf, con1,
1047 		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
1048 		     RK3568_GMAC_RXCLK_DLY_ENABLE |
1049 		     RK3568_GMAC_TXCLK_DLY_ENABLE);
1050 }
1051 
1052 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1053 {
1054 	struct device *dev = &bsp_priv->pdev->dev;
1055 	u32 con1;
1056 
1057 	if (IS_ERR(bsp_priv->grf)) {
1058 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1059 		return;
1060 	}
1061 
1062 	con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1063 				     RK3568_GRF_GMAC0_CON1;
1064 	regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1065 }
1066 
1067 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1068 {
1069 	struct device *dev = &bsp_priv->pdev->dev;
1070 	unsigned long rate;
1071 	int ret;
1072 
1073 	switch (speed) {
1074 	case 10:
1075 		rate = 2500000;
1076 		break;
1077 	case 100:
1078 		rate = 25000000;
1079 		break;
1080 	case 1000:
1081 		rate = 125000000;
1082 		break;
1083 	default:
1084 		dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1085 		return;
1086 	}
1087 
1088 	ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1089 	if (ret)
1090 		dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1091 			__func__, rate, ret);
1092 }
1093 
1094 static const struct rk_gmac_ops rk3568_ops = {
1095 	.set_to_rgmii = rk3568_set_to_rgmii,
1096 	.set_to_rmii = rk3568_set_to_rmii,
1097 	.set_rgmii_speed = rk3568_set_gmac_speed,
1098 	.set_rmii_speed = rk3568_set_gmac_speed,
1099 	.regs_valid = true,
1100 	.regs = {
1101 		0xfe2a0000, /* gmac0 */
1102 		0xfe010000, /* gmac1 */
1103 		0x0, /* sentinel */
1104 	},
1105 };
1106 
1107 /* sys_grf */
1108 #define RK3588_GRF_GMAC_CON7			0X031c
1109 #define RK3588_GRF_GMAC_CON8			0X0320
1110 #define RK3588_GRF_GMAC_CON9			0X0324
1111 
1112 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
1113 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
1114 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
1115 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)
1116 
1117 #define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1118 #define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1119 
1120 /* php_grf */
1121 #define RK3588_GRF_GMAC_CON0			0X0008
1122 #define RK3588_GRF_CLK_CON1			0X0070
1123 
1124 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
1125 	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1126 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
1127 	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1128 
1129 #define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
1130 #define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))
1131 
1132 #define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)
1133 #define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)
1134 
1135 #define RK3588_GMA_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
1136 #define RK3588_GMA_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)
1137 
1138 #define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
1139 			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1140 #define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
1141 			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1142 #define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
1143 			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1144 
1145 #define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
1146 #define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)
1147 
1148 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1149 				int tx_delay, int rx_delay)
1150 {
1151 	struct device *dev = &bsp_priv->pdev->dev;
1152 	u32 offset_con, id = bsp_priv->id;
1153 
1154 	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1155 		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1156 		return;
1157 	}
1158 
1159 	offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
1160 					 RK3588_GRF_GMAC_CON8;
1161 
1162 	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1163 		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1164 
1165 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1166 		     RK3588_GMAC_CLK_RGMII_MODE(id));
1167 
1168 	regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1169 		     RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
1170 		     RK3588_GMAC_TXCLK_DLY_ENABLE(id));
1171 
1172 	regmap_write(bsp_priv->grf, offset_con,
1173 		     RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
1174 		     RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
1175 }
1176 
1177 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1178 {
1179 	struct device *dev = &bsp_priv->pdev->dev;
1180 
1181 	if (IS_ERR(bsp_priv->php_grf)) {
1182 		dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1183 		return;
1184 	}
1185 
1186 	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1187 		     RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
1188 
1189 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1190 		     RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
1191 }
1192 
1193 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1194 {
1195 	struct device *dev = &bsp_priv->pdev->dev;
1196 	unsigned int val = 0, id = bsp_priv->id;
1197 
1198 	switch (speed) {
1199 	case 10:
1200 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1201 			val = RK3588_GMA_CLK_RMII_DIV20(id);
1202 		else
1203 			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1204 		break;
1205 	case 100:
1206 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1207 			val = RK3588_GMA_CLK_RMII_DIV2(id);
1208 		else
1209 			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1210 		break;
1211 	case 1000:
1212 		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1213 			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1214 		else
1215 			goto err;
1216 		break;
1217 	default:
1218 		goto err;
1219 	}
1220 
1221 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1222 
1223 	return;
1224 err:
1225 	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1226 }
1227 
1228 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1229 				       bool enable)
1230 {
1231 	unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) :
1232 				   RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id);
1233 
1234 	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
1235 			RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
1236 
1237 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1238 }
1239 
1240 static const struct rk_gmac_ops rk3588_ops = {
1241 	.set_to_rgmii = rk3588_set_to_rgmii,
1242 	.set_to_rmii = rk3588_set_to_rmii,
1243 	.set_rgmii_speed = rk3588_set_gmac_speed,
1244 	.set_rmii_speed = rk3588_set_gmac_speed,
1245 	.set_clock_selection = rk3588_set_clock_selection,
1246 	.regs_valid = true,
1247 	.regs = {
1248 		0xfe1b0000, /* gmac0 */
1249 		0xfe1c0000, /* gmac1 */
1250 		0x0, /* sentinel */
1251 	},
1252 };
1253 
1254 #define RV1108_GRF_GMAC_CON0		0X0900
1255 
1256 /* RV1108_GRF_GMAC_CON0 */
1257 #define RV1108_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1258 					GRF_BIT(6))
1259 #define RV1108_GMAC_FLOW_CTRL		GRF_BIT(3)
1260 #define RV1108_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
1261 #define RV1108_GMAC_SPEED_10M		GRF_CLR_BIT(2)
1262 #define RV1108_GMAC_SPEED_100M		GRF_BIT(2)
1263 #define RV1108_GMAC_RMII_CLK_25M	GRF_BIT(7)
1264 #define RV1108_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(7)
1265 
1266 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1267 {
1268 	struct device *dev = &bsp_priv->pdev->dev;
1269 
1270 	if (IS_ERR(bsp_priv->grf)) {
1271 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1272 		return;
1273 	}
1274 
1275 	regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1276 		     RV1108_GMAC_PHY_INTF_SEL_RMII);
1277 }
1278 
1279 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1280 {
1281 	struct device *dev = &bsp_priv->pdev->dev;
1282 
1283 	if (IS_ERR(bsp_priv->grf)) {
1284 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1285 		return;
1286 	}
1287 
1288 	if (speed == 10) {
1289 		regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1290 			     RV1108_GMAC_RMII_CLK_2_5M |
1291 			     RV1108_GMAC_SPEED_10M);
1292 	} else if (speed == 100) {
1293 		regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1294 			     RV1108_GMAC_RMII_CLK_25M |
1295 			     RV1108_GMAC_SPEED_100M);
1296 	} else {
1297 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1298 	}
1299 }
1300 
1301 static const struct rk_gmac_ops rv1108_ops = {
1302 	.set_to_rmii = rv1108_set_to_rmii,
1303 	.set_rmii_speed = rv1108_set_rmii_speed,
1304 };
1305 
1306 #define RV1126_GRF_GMAC_CON0		0X0070
1307 #define RV1126_GRF_GMAC_CON1		0X0074
1308 #define RV1126_GRF_GMAC_CON2		0X0078
1309 
1310 /* RV1126_GRF_GMAC_CON0 */
1311 #define RV1126_GMAC_PHY_INTF_SEL_RGMII	\
1312 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1313 #define RV1126_GMAC_PHY_INTF_SEL_RMII	\
1314 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1315 #define RV1126_GMAC_FLOW_CTRL			GRF_BIT(7)
1316 #define RV1126_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(7)
1317 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE		GRF_BIT(1)
1318 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1319 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE		GRF_BIT(0)
1320 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1321 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE		GRF_BIT(3)
1322 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1323 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE		GRF_BIT(2)
1324 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
1325 
1326 /* RV1126_GRF_GMAC_CON1 */
1327 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1328 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1329 /* RV1126_GRF_GMAC_CON2 */
1330 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1331 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1332 
1333 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1334 				int tx_delay, int rx_delay)
1335 {
1336 	struct device *dev = &bsp_priv->pdev->dev;
1337 
1338 	if (IS_ERR(bsp_priv->grf)) {
1339 		dev_err(dev, "Missing rockchip,grf property\n");
1340 		return;
1341 	}
1342 
1343 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1344 		     RV1126_GMAC_PHY_INTF_SEL_RGMII |
1345 		     RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1346 		     RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1347 		     RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1348 		     RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
1349 
1350 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1351 		     RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1352 		     RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
1353 
1354 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1355 		     RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1356 		     RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
1357 }
1358 
1359 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
1360 {
1361 	struct device *dev = &bsp_priv->pdev->dev;
1362 
1363 	if (IS_ERR(bsp_priv->grf)) {
1364 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1365 		return;
1366 	}
1367 
1368 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1369 		     RV1126_GMAC_PHY_INTF_SEL_RMII);
1370 }
1371 
1372 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1373 {
1374 	struct device *dev = &bsp_priv->pdev->dev;
1375 	unsigned long rate;
1376 	int ret;
1377 
1378 	switch (speed) {
1379 	case 10:
1380 		rate = 2500000;
1381 		break;
1382 	case 100:
1383 		rate = 25000000;
1384 		break;
1385 	case 1000:
1386 		rate = 125000000;
1387 		break;
1388 	default:
1389 		dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1390 		return;
1391 	}
1392 
1393 	ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1394 	if (ret)
1395 		dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1396 			__func__, rate, ret);
1397 }
1398 
1399 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1400 {
1401 	struct device *dev = &bsp_priv->pdev->dev;
1402 	unsigned long rate;
1403 	int ret;
1404 
1405 	switch (speed) {
1406 	case 10:
1407 		rate = 2500000;
1408 		break;
1409 	case 100:
1410 		rate = 25000000;
1411 		break;
1412 	default:
1413 		dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1414 		return;
1415 	}
1416 
1417 	ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1418 	if (ret)
1419 		dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1420 			__func__, rate, ret);
1421 }
1422 
1423 static const struct rk_gmac_ops rv1126_ops = {
1424 	.set_to_rgmii = rv1126_set_to_rgmii,
1425 	.set_to_rmii = rv1126_set_to_rmii,
1426 	.set_rgmii_speed = rv1126_set_rgmii_speed,
1427 	.set_rmii_speed = rv1126_set_rmii_speed,
1428 };
1429 
1430 #define RK_GRF_MACPHY_CON0		0xb00
1431 #define RK_GRF_MACPHY_CON1		0xb04
1432 #define RK_GRF_MACPHY_CON2		0xb08
1433 #define RK_GRF_MACPHY_CON3		0xb0c
1434 
1435 #define RK_MACPHY_ENABLE		GRF_BIT(0)
1436 #define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
1437 #define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
1438 #define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
1439 #define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
1440 #define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
1441 
1442 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1443 {
1444 	if (priv->ops->integrated_phy_powerup)
1445 		priv->ops->integrated_phy_powerup(priv);
1446 
1447 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1448 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1449 
1450 	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1451 	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1452 
1453 	if (priv->phy_reset) {
1454 		/* PHY needs to be disabled before trying to reset it */
1455 		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1456 		if (priv->phy_reset)
1457 			reset_control_assert(priv->phy_reset);
1458 		usleep_range(10, 20);
1459 		if (priv->phy_reset)
1460 			reset_control_deassert(priv->phy_reset);
1461 		usleep_range(10, 20);
1462 		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1463 		msleep(30);
1464 	}
1465 }
1466 
1467 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1468 {
1469 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1470 	if (priv->phy_reset)
1471 		reset_control_assert(priv->phy_reset);
1472 }
1473 
1474 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1475 {
1476 	struct rk_priv_data *bsp_priv = plat->bsp_priv;
1477 	struct device *dev = &bsp_priv->pdev->dev;
1478 	int ret;
1479 
1480 	bsp_priv->clk_enabled = false;
1481 
1482 	bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1483 	if (IS_ERR(bsp_priv->mac_clk_rx))
1484 		dev_err(dev, "cannot get clock %s\n",
1485 			"mac_clk_rx");
1486 
1487 	bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1488 	if (IS_ERR(bsp_priv->mac_clk_tx))
1489 		dev_err(dev, "cannot get clock %s\n",
1490 			"mac_clk_tx");
1491 
1492 	bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1493 	if (IS_ERR(bsp_priv->aclk_mac))
1494 		dev_err(dev, "cannot get clock %s\n",
1495 			"aclk_mac");
1496 
1497 	bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1498 	if (IS_ERR(bsp_priv->pclk_mac))
1499 		dev_err(dev, "cannot get clock %s\n",
1500 			"pclk_mac");
1501 
1502 	bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1503 	if (IS_ERR(bsp_priv->clk_mac))
1504 		dev_err(dev, "cannot get clock %s\n",
1505 			"stmmaceth");
1506 
1507 	if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1508 		bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1509 		if (IS_ERR(bsp_priv->clk_mac_ref))
1510 			dev_err(dev, "cannot get clock %s\n",
1511 				"clk_mac_ref");
1512 
1513 		if (!bsp_priv->clock_input) {
1514 			bsp_priv->clk_mac_refout =
1515 				devm_clk_get(dev, "clk_mac_refout");
1516 			if (IS_ERR(bsp_priv->clk_mac_refout))
1517 				dev_err(dev, "cannot get clock %s\n",
1518 					"clk_mac_refout");
1519 		}
1520 	}
1521 
1522 	bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
1523 	if (IS_ERR(bsp_priv->clk_mac_speed))
1524 		dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
1525 
1526 	if (bsp_priv->clock_input) {
1527 		dev_info(dev, "clock input from PHY\n");
1528 	} else {
1529 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1530 			clk_set_rate(bsp_priv->clk_mac, 50000000);
1531 	}
1532 
1533 	if (plat->phy_node && bsp_priv->integrated_phy) {
1534 		bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1535 		if (IS_ERR(bsp_priv->clk_phy)) {
1536 			ret = PTR_ERR(bsp_priv->clk_phy);
1537 			dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1538 			return -EINVAL;
1539 		}
1540 		clk_set_rate(bsp_priv->clk_phy, 50000000);
1541 	}
1542 
1543 	return 0;
1544 }
1545 
1546 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1547 {
1548 	int phy_iface = bsp_priv->phy_iface;
1549 
1550 	if (enable) {
1551 		if (!bsp_priv->clk_enabled) {
1552 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1553 				if (!IS_ERR(bsp_priv->mac_clk_rx))
1554 					clk_prepare_enable(
1555 						bsp_priv->mac_clk_rx);
1556 
1557 				if (!IS_ERR(bsp_priv->clk_mac_ref))
1558 					clk_prepare_enable(
1559 						bsp_priv->clk_mac_ref);
1560 
1561 				if (!IS_ERR(bsp_priv->clk_mac_refout))
1562 					clk_prepare_enable(
1563 						bsp_priv->clk_mac_refout);
1564 			}
1565 
1566 			if (!IS_ERR(bsp_priv->clk_phy))
1567 				clk_prepare_enable(bsp_priv->clk_phy);
1568 
1569 			if (!IS_ERR(bsp_priv->aclk_mac))
1570 				clk_prepare_enable(bsp_priv->aclk_mac);
1571 
1572 			if (!IS_ERR(bsp_priv->pclk_mac))
1573 				clk_prepare_enable(bsp_priv->pclk_mac);
1574 
1575 			if (!IS_ERR(bsp_priv->mac_clk_tx))
1576 				clk_prepare_enable(bsp_priv->mac_clk_tx);
1577 
1578 			if (!IS_ERR(bsp_priv->clk_mac_speed))
1579 				clk_prepare_enable(bsp_priv->clk_mac_speed);
1580 
1581 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1582 				bsp_priv->ops->set_clock_selection(bsp_priv,
1583 					       bsp_priv->clock_input, true);
1584 
1585 			/**
1586 			 * if (!IS_ERR(bsp_priv->clk_mac))
1587 			 *	clk_prepare_enable(bsp_priv->clk_mac);
1588 			 */
1589 			mdelay(5);
1590 			bsp_priv->clk_enabled = true;
1591 		}
1592 	} else {
1593 		if (bsp_priv->clk_enabled) {
1594 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1595 				clk_disable_unprepare(bsp_priv->mac_clk_rx);
1596 
1597 				clk_disable_unprepare(bsp_priv->clk_mac_ref);
1598 
1599 				clk_disable_unprepare(bsp_priv->clk_mac_refout);
1600 			}
1601 
1602 			clk_disable_unprepare(bsp_priv->clk_phy);
1603 
1604 			clk_disable_unprepare(bsp_priv->aclk_mac);
1605 
1606 			clk_disable_unprepare(bsp_priv->pclk_mac);
1607 
1608 			clk_disable_unprepare(bsp_priv->mac_clk_tx);
1609 
1610 			clk_disable_unprepare(bsp_priv->clk_mac_speed);
1611 
1612 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1613 				bsp_priv->ops->set_clock_selection(bsp_priv,
1614 					      bsp_priv->clock_input, false);
1615 			/**
1616 			 * if (!IS_ERR(bsp_priv->clk_mac))
1617 			 *	clk_disable_unprepare(bsp_priv->clk_mac);
1618 			 */
1619 			bsp_priv->clk_enabled = false;
1620 		}
1621 	}
1622 
1623 	return 0;
1624 }
1625 
1626 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1627 {
1628 	struct regulator *ldo = bsp_priv->regulator;
1629 	int ret;
1630 	struct device *dev = &bsp_priv->pdev->dev;
1631 
1632 	if (!ldo)
1633 		return 0;
1634 
1635 	if (enable) {
1636 		ret = regulator_enable(ldo);
1637 		if (ret)
1638 			dev_err(dev, "fail to enable phy-supply\n");
1639 	} else {
1640 		ret = regulator_disable(ldo);
1641 		if (ret)
1642 			dev_err(dev, "fail to disable phy-supply\n");
1643 	}
1644 
1645 	return 0;
1646 }
1647 
1648 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1649 					  struct plat_stmmacenet_data *plat,
1650 					  const struct rk_gmac_ops *ops)
1651 {
1652 	struct rk_priv_data *bsp_priv;
1653 	struct device *dev = &pdev->dev;
1654 	struct resource *res;
1655 	int ret;
1656 	const char *strings = NULL;
1657 	int value;
1658 
1659 	bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1660 	if (!bsp_priv)
1661 		return ERR_PTR(-ENOMEM);
1662 
1663 	of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1664 	bsp_priv->ops = ops;
1665 
1666 	/* Some SoCs have multiple MAC controllers, which need
1667 	 * to be distinguished.
1668 	 */
1669 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 	if (res && ops->regs_valid) {
1671 		int i = 0;
1672 
1673 		while (ops->regs[i]) {
1674 			if (ops->regs[i] == res->start) {
1675 				bsp_priv->id = i;
1676 				break;
1677 			}
1678 			i++;
1679 		}
1680 	}
1681 
1682 	bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
1683 	if (IS_ERR(bsp_priv->regulator)) {
1684 		if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
1685 			dev_err(dev, "phy regulator is not available yet, deferred probing\n");
1686 			return ERR_PTR(-EPROBE_DEFER);
1687 		}
1688 		dev_err(dev, "no regulator found\n");
1689 		bsp_priv->regulator = NULL;
1690 	}
1691 
1692 	ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1693 	if (ret) {
1694 		dev_err(dev, "Can not read property: clock_in_out.\n");
1695 		bsp_priv->clock_input = true;
1696 	} else {
1697 		dev_info(dev, "clock input or output? (%s).\n",
1698 			 strings);
1699 		if (!strcmp(strings, "input"))
1700 			bsp_priv->clock_input = true;
1701 		else
1702 			bsp_priv->clock_input = false;
1703 	}
1704 
1705 	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1706 	if (ret) {
1707 		bsp_priv->tx_delay = 0x30;
1708 		dev_err(dev, "Can not read property: tx_delay.");
1709 		dev_err(dev, "set tx_delay to 0x%x\n",
1710 			bsp_priv->tx_delay);
1711 	} else {
1712 		dev_info(dev, "TX delay(0x%x).\n", value);
1713 		bsp_priv->tx_delay = value;
1714 	}
1715 
1716 	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1717 	if (ret) {
1718 		bsp_priv->rx_delay = 0x10;
1719 		dev_err(dev, "Can not read property: rx_delay.");
1720 		dev_err(dev, "set rx_delay to 0x%x\n",
1721 			bsp_priv->rx_delay);
1722 	} else {
1723 		dev_info(dev, "RX delay(0x%x).\n", value);
1724 		bsp_priv->rx_delay = value;
1725 	}
1726 
1727 	bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1728 							"rockchip,grf");
1729 	bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1730 							    "rockchip,php-grf");
1731 
1732 	if (plat->phy_node) {
1733 		bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1734 								 "phy-is-integrated");
1735 		if (bsp_priv->integrated_phy) {
1736 			bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1737 			if (IS_ERR(bsp_priv->phy_reset)) {
1738 				dev_err(&pdev->dev, "No PHY reset control found.\n");
1739 				bsp_priv->phy_reset = NULL;
1740 			}
1741 		}
1742 	}
1743 	dev_info(dev, "integrated PHY? (%s).\n",
1744 		 bsp_priv->integrated_phy ? "yes" : "no");
1745 
1746 	bsp_priv->pdev = pdev;
1747 
1748 	return bsp_priv;
1749 }
1750 
1751 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1752 {
1753 	switch (bsp_priv->phy_iface) {
1754 	case PHY_INTERFACE_MODE_RGMII:
1755 	case PHY_INTERFACE_MODE_RGMII_ID:
1756 	case PHY_INTERFACE_MODE_RGMII_RXID:
1757 	case PHY_INTERFACE_MODE_RGMII_TXID:
1758 		if (!bsp_priv->ops->set_to_rgmii)
1759 			return -EINVAL;
1760 		break;
1761 	case PHY_INTERFACE_MODE_RMII:
1762 		if (!bsp_priv->ops->set_to_rmii)
1763 			return -EINVAL;
1764 		break;
1765 	default:
1766 		dev_err(&bsp_priv->pdev->dev,
1767 			"unsupported interface %d", bsp_priv->phy_iface);
1768 	}
1769 	return 0;
1770 }
1771 
1772 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1773 {
1774 	int ret;
1775 	struct device *dev = &bsp_priv->pdev->dev;
1776 
1777 	ret = rk_gmac_check_ops(bsp_priv);
1778 	if (ret)
1779 		return ret;
1780 
1781 	ret = gmac_clk_enable(bsp_priv, true);
1782 	if (ret)
1783 		return ret;
1784 
1785 	/*rmii or rgmii*/
1786 	switch (bsp_priv->phy_iface) {
1787 	case PHY_INTERFACE_MODE_RGMII:
1788 		dev_info(dev, "init for RGMII\n");
1789 		bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1790 					    bsp_priv->rx_delay);
1791 		break;
1792 	case PHY_INTERFACE_MODE_RGMII_ID:
1793 		dev_info(dev, "init for RGMII_ID\n");
1794 		bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1795 		break;
1796 	case PHY_INTERFACE_MODE_RGMII_RXID:
1797 		dev_info(dev, "init for RGMII_RXID\n");
1798 		bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1799 		break;
1800 	case PHY_INTERFACE_MODE_RGMII_TXID:
1801 		dev_info(dev, "init for RGMII_TXID\n");
1802 		bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1803 		break;
1804 	case PHY_INTERFACE_MODE_RMII:
1805 		dev_info(dev, "init for RMII\n");
1806 		bsp_priv->ops->set_to_rmii(bsp_priv);
1807 		break;
1808 	default:
1809 		dev_err(dev, "NO interface defined!\n");
1810 	}
1811 
1812 	ret = phy_power_on(bsp_priv, true);
1813 	if (ret) {
1814 		gmac_clk_enable(bsp_priv, false);
1815 		return ret;
1816 	}
1817 
1818 	pm_runtime_get_sync(dev);
1819 
1820 	if (bsp_priv->integrated_phy)
1821 		rk_gmac_integrated_phy_powerup(bsp_priv);
1822 
1823 	return 0;
1824 }
1825 
1826 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1827 {
1828 	if (gmac->integrated_phy)
1829 		rk_gmac_integrated_phy_powerdown(gmac);
1830 
1831 	pm_runtime_put_sync(&gmac->pdev->dev);
1832 
1833 	phy_power_on(gmac, false);
1834 	gmac_clk_enable(gmac, false);
1835 }
1836 
1837 static void rk_fix_speed(void *priv, unsigned int speed)
1838 {
1839 	struct rk_priv_data *bsp_priv = priv;
1840 	struct device *dev = &bsp_priv->pdev->dev;
1841 
1842 	switch (bsp_priv->phy_iface) {
1843 	case PHY_INTERFACE_MODE_RGMII:
1844 	case PHY_INTERFACE_MODE_RGMII_ID:
1845 	case PHY_INTERFACE_MODE_RGMII_RXID:
1846 	case PHY_INTERFACE_MODE_RGMII_TXID:
1847 		if (bsp_priv->ops->set_rgmii_speed)
1848 			bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1849 		break;
1850 	case PHY_INTERFACE_MODE_RMII:
1851 		if (bsp_priv->ops->set_rmii_speed)
1852 			bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1853 		break;
1854 	default:
1855 		dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1856 	}
1857 }
1858 
1859 static int rk_gmac_probe(struct platform_device *pdev)
1860 {
1861 	struct plat_stmmacenet_data *plat_dat;
1862 	struct stmmac_resources stmmac_res;
1863 	const struct rk_gmac_ops *data;
1864 	int ret;
1865 
1866 	data = of_device_get_match_data(&pdev->dev);
1867 	if (!data) {
1868 		dev_err(&pdev->dev, "no of match data provided\n");
1869 		return -EINVAL;
1870 	}
1871 
1872 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1873 	if (ret)
1874 		return ret;
1875 
1876 	plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
1877 	if (IS_ERR(plat_dat))
1878 		return PTR_ERR(plat_dat);
1879 
1880 	/* If the stmmac is not already selected as gmac4,
1881 	 * then make sure we fallback to gmac.
1882 	 */
1883 	if (!plat_dat->has_gmac4)
1884 		plat_dat->has_gmac = true;
1885 	plat_dat->fix_mac_speed = rk_fix_speed;
1886 
1887 	plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1888 	if (IS_ERR(plat_dat->bsp_priv)) {
1889 		ret = PTR_ERR(plat_dat->bsp_priv);
1890 		goto err_remove_config_dt;
1891 	}
1892 
1893 	ret = rk_gmac_clk_init(plat_dat);
1894 	if (ret)
1895 		goto err_remove_config_dt;
1896 
1897 	ret = rk_gmac_powerup(plat_dat->bsp_priv);
1898 	if (ret)
1899 		goto err_remove_config_dt;
1900 
1901 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1902 	if (ret)
1903 		goto err_gmac_powerdown;
1904 
1905 	return 0;
1906 
1907 err_gmac_powerdown:
1908 	rk_gmac_powerdown(plat_dat->bsp_priv);
1909 err_remove_config_dt:
1910 	stmmac_remove_config_dt(pdev, plat_dat);
1911 
1912 	return ret;
1913 }
1914 
1915 static int rk_gmac_remove(struct platform_device *pdev)
1916 {
1917 	struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1918 
1919 	stmmac_dvr_remove(&pdev->dev);
1920 
1921 	rk_gmac_powerdown(bsp_priv);
1922 
1923 	return 0;
1924 }
1925 
1926 #ifdef CONFIG_PM_SLEEP
1927 static int rk_gmac_suspend(struct device *dev)
1928 {
1929 	struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1930 	int ret = stmmac_suspend(dev);
1931 
1932 	/* Keep the PHY up if we use Wake-on-Lan. */
1933 	if (!device_may_wakeup(dev)) {
1934 		rk_gmac_powerdown(bsp_priv);
1935 		bsp_priv->suspended = true;
1936 	}
1937 
1938 	return ret;
1939 }
1940 
1941 static int rk_gmac_resume(struct device *dev)
1942 {
1943 	struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1944 
1945 	/* The PHY was up for Wake-on-Lan. */
1946 	if (bsp_priv->suspended) {
1947 		rk_gmac_powerup(bsp_priv);
1948 		bsp_priv->suspended = false;
1949 	}
1950 
1951 	return stmmac_resume(dev);
1952 }
1953 #endif /* CONFIG_PM_SLEEP */
1954 
1955 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1956 
1957 static const struct of_device_id rk_gmac_dwmac_match[] = {
1958 	{ .compatible = "rockchip,px30-gmac",	.data = &px30_ops   },
1959 	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1960 	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1961 	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1962 	{ .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1963 	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1964 	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1965 	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1966 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1967 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1968 	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
1969 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1970 	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
1971 	{ }
1972 };
1973 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1974 
1975 static struct platform_driver rk_gmac_dwmac_driver = {
1976 	.probe  = rk_gmac_probe,
1977 	.remove = rk_gmac_remove,
1978 	.driver = {
1979 		.name           = "rk_gmac-dwmac",
1980 		.pm		= &rk_gmac_pm_ops,
1981 		.of_match_table = rk_gmac_dwmac_match,
1982 	},
1983 };
1984 module_platform_driver(rk_gmac_dwmac_driver);
1985 
1986 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1987 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1988 MODULE_LICENSE("GPL");
1989