1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-19, Linaro Limited 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_device.h> 7 #include <linux/platform_device.h> 8 #include <linux/phy.h> 9 #include "stmmac.h" 10 #include "stmmac_platform.h" 11 12 #define RGMII_IO_MACRO_CONFIG 0x0 13 #define SDCC_HC_REG_DLL_CONFIG 0x4 14 #define SDCC_TEST_CTL 0x8 15 #define SDCC_HC_REG_DDR_CONFIG 0xC 16 #define SDCC_HC_REG_DLL_CONFIG2 0x10 17 #define SDC4_STATUS 0x14 18 #define SDCC_USR_CTL 0x18 19 #define RGMII_IO_MACRO_CONFIG2 0x1C 20 #define RGMII_IO_MACRO_DEBUG1 0x20 21 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 22 23 /* RGMII_IO_MACRO_CONFIG fields */ 24 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 25 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 26 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 27 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 28 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 29 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 30 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 31 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 32 #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 33 #define RGMII_CONFIG_PROG_SWAP BIT(1) 34 #define RGMII_CONFIG_DDR_MODE BIT(0) 35 36 /* SDCC_HC_REG_DLL_CONFIG fields */ 37 #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 38 #define SDCC_DLL_CONFIG_PDN BIT(29) 39 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 40 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 41 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 42 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 43 #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 44 #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 45 #define SDCC_DLL_MCLK_GATING_EN BIT(5) 46 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 47 48 /* SDCC_HC_REG_DDR_CONFIG fields */ 49 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 50 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 51 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 52 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 53 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 54 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 55 56 /* SDCC_HC_REG_DLL_CONFIG2 fields */ 57 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 58 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 59 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 60 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 61 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 62 63 /* SDC4_STATUS bits */ 64 #define SDC4_STATUS_DLL_LOCK BIT(7) 65 66 /* RGMII_IO_MACRO_CONFIG2 fields */ 67 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 68 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 69 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 70 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 71 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 72 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 73 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 74 75 struct ethqos_emac_por { 76 unsigned int offset; 77 unsigned int value; 78 }; 79 80 struct ethqos_emac_driver_data { 81 const struct ethqos_emac_por *por; 82 unsigned int num_por; 83 bool rgmii_config_loopback_en; 84 bool has_emac3; 85 struct dwmac4_addrs dwmac4_addrs; 86 }; 87 88 struct qcom_ethqos { 89 struct platform_device *pdev; 90 void __iomem *rgmii_base; 91 92 unsigned int rgmii_clk_rate; 93 struct clk *rgmii_clk; 94 unsigned int speed; 95 96 const struct ethqos_emac_por *por; 97 unsigned int num_por; 98 bool rgmii_config_loopback_en; 99 bool has_emac3; 100 }; 101 102 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 103 { 104 return readl(ethqos->rgmii_base + offset); 105 } 106 107 static void rgmii_writel(struct qcom_ethqos *ethqos, 108 int value, unsigned int offset) 109 { 110 writel(value, ethqos->rgmii_base + offset); 111 } 112 113 static void rgmii_updatel(struct qcom_ethqos *ethqos, 114 int mask, int val, unsigned int offset) 115 { 116 unsigned int temp; 117 118 temp = rgmii_readl(ethqos, offset); 119 temp = (temp & ~(mask)) | val; 120 rgmii_writel(ethqos, temp, offset); 121 } 122 123 static void rgmii_dump(void *priv) 124 { 125 struct qcom_ethqos *ethqos = priv; 126 127 dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n"); 128 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n", 129 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 130 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 131 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 132 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 133 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 134 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 135 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 136 dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n", 137 rgmii_readl(ethqos, SDC4_STATUS)); 138 dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n", 139 rgmii_readl(ethqos, SDCC_USR_CTL)); 140 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 141 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 142 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 143 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 144 dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 145 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 146 } 147 148 /* Clock rates */ 149 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 150 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 151 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 152 153 static void 154 ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) 155 { 156 switch (speed) { 157 case SPEED_1000: 158 ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; 159 break; 160 161 case SPEED_100: 162 ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 163 break; 164 165 case SPEED_10: 166 ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 167 break; 168 } 169 170 clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); 171 } 172 173 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 174 { 175 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 176 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 177 } 178 179 static const struct ethqos_emac_por emac_v2_3_0_por[] = { 180 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 181 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 182 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 183 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 184 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 185 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 186 }; 187 188 static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 189 .por = emac_v2_3_0_por, 190 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 191 .rgmii_config_loopback_en = true, 192 .has_emac3 = false, 193 }; 194 195 static const struct ethqos_emac_por emac_v2_1_0_por[] = { 196 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 197 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 198 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 199 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 200 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 201 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 202 }; 203 204 static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 205 .por = emac_v2_1_0_por, 206 .num_por = ARRAY_SIZE(emac_v2_1_0_por), 207 .rgmii_config_loopback_en = false, 208 .has_emac3 = false, 209 }; 210 211 static const struct ethqos_emac_por emac_v3_0_0_por[] = { 212 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 213 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 214 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 215 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 216 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 217 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 218 }; 219 220 static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 221 .por = emac_v3_0_0_por, 222 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 223 .rgmii_config_loopback_en = false, 224 .has_emac3 = true, 225 .dwmac4_addrs = { 226 .dma_chan = 0x00008100, 227 .dma_chan_offset = 0x1000, 228 .mtl_chan = 0x00008000, 229 .mtl_chan_offset = 0x1000, 230 .mtl_ets_ctrl = 0x00008010, 231 .mtl_ets_ctrl_offset = 0x1000, 232 .mtl_txq_weight = 0x00008018, 233 .mtl_txq_weight_offset = 0x1000, 234 .mtl_send_slp_cred = 0x0000801c, 235 .mtl_send_slp_cred_offset = 0x1000, 236 .mtl_high_cred = 0x00008020, 237 .mtl_high_cred_offset = 0x1000, 238 .mtl_low_cred = 0x00008024, 239 .mtl_low_cred_offset = 0x1000, 240 }, 241 }; 242 243 static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 244 { 245 unsigned int val; 246 int retry = 1000; 247 248 /* Set CDR_EN */ 249 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 250 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 251 252 /* Set CDR_EXT_EN */ 253 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 254 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 255 256 /* Clear CK_OUT_EN */ 257 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 258 0, SDCC_HC_REG_DLL_CONFIG); 259 260 /* Set DLL_EN */ 261 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 262 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 263 264 if (!ethqos->has_emac3) { 265 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 266 0, SDCC_HC_REG_DLL_CONFIG); 267 268 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 269 0, SDCC_HC_REG_DLL_CONFIG); 270 } 271 272 /* Wait for CK_OUT_EN clear */ 273 do { 274 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 275 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 276 if (!val) 277 break; 278 mdelay(1); 279 retry--; 280 } while (retry > 0); 281 if (!retry) 282 dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n"); 283 284 /* Set CK_OUT_EN */ 285 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 286 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 287 288 /* Wait for CK_OUT_EN set */ 289 retry = 1000; 290 do { 291 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 292 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 293 if (val) 294 break; 295 mdelay(1); 296 retry--; 297 } while (retry > 0); 298 if (!retry) 299 dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n"); 300 301 /* Set DDR_CAL_EN */ 302 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 303 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 304 305 if (!ethqos->has_emac3) { 306 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 307 0, SDCC_HC_REG_DLL_CONFIG2); 308 309 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 310 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 311 312 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 313 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 314 315 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 316 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 317 SDCC_HC_REG_DLL_CONFIG2); 318 } 319 320 return 0; 321 } 322 323 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 324 { 325 int phase_shift; 326 int phy_mode; 327 int loopback; 328 329 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 330 phy_mode = device_get_phy_mode(ðqos->pdev->dev); 331 if (phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 332 phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 333 phase_shift = 0; 334 else 335 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 336 337 /* Disable loopback mode */ 338 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 339 0, RGMII_IO_MACRO_CONFIG2); 340 341 /* Determine if this platform wants loopback enabled after programming */ 342 if (ethqos->rgmii_config_loopback_en) 343 loopback = RGMII_CONFIG_LOOPBACK_EN; 344 else 345 loopback = 0; 346 347 /* Select RGMII, write 0 to interface select */ 348 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 349 0, RGMII_IO_MACRO_CONFIG); 350 351 switch (ethqos->speed) { 352 case SPEED_1000: 353 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 354 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 355 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 356 0, RGMII_IO_MACRO_CONFIG); 357 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 358 RGMII_CONFIG_POS_NEG_DATA_SEL, 359 RGMII_IO_MACRO_CONFIG); 360 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 361 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 362 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 363 0, RGMII_IO_MACRO_CONFIG2); 364 365 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 366 phase_shift, RGMII_IO_MACRO_CONFIG2); 367 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 368 0, RGMII_IO_MACRO_CONFIG2); 369 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 370 RGMII_CONFIG2_RX_PROG_SWAP, 371 RGMII_IO_MACRO_CONFIG2); 372 373 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 374 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 375 */ 376 if (ethqos->has_emac3) { 377 /* 0.9 ns */ 378 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 379 115, SDCC_HC_REG_DDR_CONFIG); 380 } else { 381 /* 1.8 ns */ 382 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 383 57, SDCC_HC_REG_DDR_CONFIG); 384 } 385 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 386 SDCC_DDR_CONFIG_PRG_DLY_EN, 387 SDCC_HC_REG_DDR_CONFIG); 388 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 389 loopback, RGMII_IO_MACRO_CONFIG); 390 break; 391 392 case SPEED_100: 393 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 394 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 395 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 396 RGMII_CONFIG_BYPASS_TX_ID_EN, 397 RGMII_IO_MACRO_CONFIG); 398 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 399 0, RGMII_IO_MACRO_CONFIG); 400 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 401 0, RGMII_IO_MACRO_CONFIG); 402 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 403 0, RGMII_IO_MACRO_CONFIG2); 404 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 405 phase_shift, RGMII_IO_MACRO_CONFIG2); 406 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 407 BIT(6), RGMII_IO_MACRO_CONFIG); 408 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 409 0, RGMII_IO_MACRO_CONFIG2); 410 411 if (ethqos->has_emac3) 412 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 413 RGMII_CONFIG2_RX_PROG_SWAP, 414 RGMII_IO_MACRO_CONFIG2); 415 else 416 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 417 0, RGMII_IO_MACRO_CONFIG2); 418 419 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 420 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 421 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 422 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 423 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 424 SDCC_HC_REG_DDR_CONFIG); 425 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 426 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 427 SDCC_HC_REG_DDR_CONFIG); 428 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 429 loopback, RGMII_IO_MACRO_CONFIG); 430 break; 431 432 case SPEED_10: 433 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 434 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 435 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 436 RGMII_CONFIG_BYPASS_TX_ID_EN, 437 RGMII_IO_MACRO_CONFIG); 438 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 439 0, RGMII_IO_MACRO_CONFIG); 440 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 441 0, RGMII_IO_MACRO_CONFIG); 442 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 443 0, RGMII_IO_MACRO_CONFIG2); 444 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 445 phase_shift, RGMII_IO_MACRO_CONFIG2); 446 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 447 BIT(12) | GENMASK(9, 8), 448 RGMII_IO_MACRO_CONFIG); 449 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 450 0, RGMII_IO_MACRO_CONFIG2); 451 if (ethqos->has_emac3) 452 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 453 RGMII_CONFIG2_RX_PROG_SWAP, 454 RGMII_IO_MACRO_CONFIG2); 455 else 456 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 457 0, RGMII_IO_MACRO_CONFIG2); 458 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 459 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 460 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 461 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 462 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 463 SDCC_HC_REG_DDR_CONFIG); 464 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 465 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 466 SDCC_HC_REG_DDR_CONFIG); 467 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 468 loopback, RGMII_IO_MACRO_CONFIG); 469 break; 470 default: 471 dev_err(ðqos->pdev->dev, 472 "Invalid speed %d\n", ethqos->speed); 473 return -EINVAL; 474 } 475 476 return 0; 477 } 478 479 static int ethqos_configure(struct qcom_ethqos *ethqos) 480 { 481 volatile unsigned int dll_lock; 482 unsigned int i, retry = 1000; 483 484 /* Reset to POR values and enable clk */ 485 for (i = 0; i < ethqos->num_por; i++) 486 rgmii_writel(ethqos, ethqos->por[i].value, 487 ethqos->por[i].offset); 488 ethqos_set_func_clk_en(ethqos); 489 490 /* Initialize the DLL first */ 491 492 /* Set DLL_RST */ 493 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 494 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 495 496 /* Set PDN */ 497 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 498 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 499 500 if (ethqos->has_emac3) { 501 if (ethqos->speed == SPEED_1000) { 502 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 503 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 504 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 505 } else { 506 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 507 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 508 } 509 } 510 511 /* Clear DLL_RST */ 512 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 513 SDCC_HC_REG_DLL_CONFIG); 514 515 /* Clear PDN */ 516 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 517 SDCC_HC_REG_DLL_CONFIG); 518 519 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 520 /* Set DLL_EN */ 521 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 522 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 523 524 /* Set CK_OUT_EN */ 525 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 526 SDCC_DLL_CONFIG_CK_OUT_EN, 527 SDCC_HC_REG_DLL_CONFIG); 528 529 /* Set USR_CTL bit 26 with mask of 3 bits */ 530 if (!ethqos->has_emac3) 531 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 532 SDCC_USR_CTL); 533 534 /* wait for DLL LOCK */ 535 do { 536 mdelay(1); 537 dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 538 if (dll_lock & SDC4_STATUS_DLL_LOCK) 539 break; 540 retry--; 541 } while (retry > 0); 542 if (!retry) 543 dev_err(ðqos->pdev->dev, 544 "Timeout while waiting for DLL lock\n"); 545 } 546 547 if (ethqos->speed == SPEED_1000) 548 ethqos_dll_configure(ethqos); 549 550 ethqos_rgmii_macro_init(ethqos); 551 552 return 0; 553 } 554 555 static void ethqos_fix_mac_speed(void *priv, unsigned int speed) 556 { 557 struct qcom_ethqos *ethqos = priv; 558 559 ethqos->speed = speed; 560 ethqos_update_rgmii_clk(ethqos, speed); 561 ethqos_configure(ethqos); 562 } 563 564 static int ethqos_clks_config(void *priv, bool enabled) 565 { 566 struct qcom_ethqos *ethqos = priv; 567 int ret = 0; 568 569 if (enabled) { 570 ret = clk_prepare_enable(ethqos->rgmii_clk); 571 if (ret) { 572 dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); 573 return ret; 574 } 575 576 /* Enable functional clock to prevent DMA reset to timeout due 577 * to lacking PHY clock after the hardware block has been power 578 * cycled. The actual configuration will be adjusted once 579 * ethqos_fix_mac_speed() is invoked. 580 */ 581 ethqos_set_func_clk_en(ethqos); 582 } else { 583 clk_disable_unprepare(ethqos->rgmii_clk); 584 } 585 586 return ret; 587 } 588 589 static int qcom_ethqos_probe(struct platform_device *pdev) 590 { 591 struct device_node *np = pdev->dev.of_node; 592 struct plat_stmmacenet_data *plat_dat; 593 struct stmmac_resources stmmac_res; 594 const struct ethqos_emac_driver_data *data; 595 struct qcom_ethqos *ethqos; 596 int ret; 597 598 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 599 if (ret) 600 return ret; 601 602 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 603 if (IS_ERR(plat_dat)) { 604 dev_err(&pdev->dev, "dt configuration failed\n"); 605 return PTR_ERR(plat_dat); 606 } 607 608 plat_dat->clks_config = ethqos_clks_config; 609 610 ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL); 611 if (!ethqos) { 612 ret = -ENOMEM; 613 goto err_mem; 614 } 615 616 ethqos->pdev = pdev; 617 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 618 if (IS_ERR(ethqos->rgmii_base)) { 619 ret = PTR_ERR(ethqos->rgmii_base); 620 goto err_mem; 621 } 622 623 data = of_device_get_match_data(&pdev->dev); 624 ethqos->por = data->por; 625 ethqos->num_por = data->num_por; 626 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 627 ethqos->has_emac3 = data->has_emac3; 628 629 ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii"); 630 if (IS_ERR(ethqos->rgmii_clk)) { 631 ret = PTR_ERR(ethqos->rgmii_clk); 632 goto err_mem; 633 } 634 635 ret = ethqos_clks_config(ethqos, true); 636 if (ret) 637 goto err_mem; 638 639 ethqos->speed = SPEED_1000; 640 ethqos_update_rgmii_clk(ethqos, SPEED_1000); 641 ethqos_set_func_clk_en(ethqos); 642 643 plat_dat->bsp_priv = ethqos; 644 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 645 plat_dat->dump_debug_regs = rgmii_dump; 646 plat_dat->has_gmac4 = 1; 647 if (ethqos->has_emac3) 648 plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 649 plat_dat->pmt = 1; 650 plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); 651 if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 652 plat_dat->rx_clk_runs_in_lpi = 1; 653 654 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 655 if (ret) 656 goto err_clk; 657 658 return ret; 659 660 err_clk: 661 ethqos_clks_config(ethqos, false); 662 663 err_mem: 664 stmmac_remove_config_dt(pdev, plat_dat); 665 666 return ret; 667 } 668 669 static int qcom_ethqos_remove(struct platform_device *pdev) 670 { 671 struct qcom_ethqos *ethqos; 672 int ret; 673 674 ethqos = get_stmmac_bsp_priv(&pdev->dev); 675 if (!ethqos) 676 return -ENODEV; 677 678 ret = stmmac_pltfr_remove(pdev); 679 ethqos_clks_config(ethqos, false); 680 681 return ret; 682 } 683 684 static const struct of_device_id qcom_ethqos_match[] = { 685 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 686 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 687 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 688 { } 689 }; 690 MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 691 692 static struct platform_driver qcom_ethqos_driver = { 693 .probe = qcom_ethqos_probe, 694 .remove = qcom_ethqos_remove, 695 .driver = { 696 .name = "qcom-ethqos", 697 .pm = &stmmac_pltfr_pm_ops, 698 .of_match_table = qcom_ethqos_match, 699 }, 700 }; 701 module_platform_driver(qcom_ethqos_driver); 702 703 MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 704 MODULE_LICENSE("GPL v2"); 705