1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-19, Linaro Limited 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_net.h> 7 #include <linux/platform_device.h> 8 #include <linux/phy.h> 9 #include <linux/phy/phy.h> 10 11 #include "stmmac.h" 12 #include "stmmac_platform.h" 13 14 #define RGMII_IO_MACRO_CONFIG 0x0 15 #define SDCC_HC_REG_DLL_CONFIG 0x4 16 #define SDCC_TEST_CTL 0x8 17 #define SDCC_HC_REG_DDR_CONFIG 0xC 18 #define SDCC_HC_REG_DLL_CONFIG2 0x10 19 #define SDC4_STATUS 0x14 20 #define SDCC_USR_CTL 0x18 21 #define RGMII_IO_MACRO_CONFIG2 0x1C 22 #define RGMII_IO_MACRO_DEBUG1 0x20 23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 24 25 /* RGMII_IO_MACRO_CONFIG fields */ 26 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 27 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 28 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 29 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 30 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 31 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 32 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 33 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 34 #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 35 #define RGMII_CONFIG_PROG_SWAP BIT(1) 36 #define RGMII_CONFIG_DDR_MODE BIT(0) 37 #define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10) 38 39 /* SDCC_HC_REG_DLL_CONFIG fields */ 40 #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 41 #define SDCC_DLL_CONFIG_PDN BIT(29) 42 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 43 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 44 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 45 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 46 #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 47 #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 48 #define SDCC_DLL_MCLK_GATING_EN BIT(5) 49 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 50 51 /* SDCC_HC_REG_DDR_CONFIG fields */ 52 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 53 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 55 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 56 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 57 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 58 59 /* SDCC_HC_REG_DLL_CONFIG2 fields */ 60 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 61 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 62 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 63 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 64 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 65 66 /* SDC4_STATUS bits */ 67 #define SDC4_STATUS_DLL_LOCK BIT(7) 68 69 /* RGMII_IO_MACRO_CONFIG2 fields */ 70 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 71 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 72 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 73 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 74 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 75 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 76 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 77 78 /* MAC_CTRL_REG bits */ 79 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14) 80 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15) 81 82 #define SGMII_10M_RX_CLK_DVDR 0x31 83 84 struct ethqos_emac_por { 85 unsigned int offset; 86 unsigned int value; 87 }; 88 89 struct ethqos_emac_driver_data { 90 const struct ethqos_emac_por *por; 91 unsigned int num_por; 92 bool rgmii_config_loopback_en; 93 bool has_emac_ge_3; 94 const char *link_clk_name; 95 bool has_integrated_pcs; 96 u32 dma_addr_width; 97 struct dwmac4_addrs dwmac4_addrs; 98 }; 99 100 struct qcom_ethqos { 101 struct platform_device *pdev; 102 void __iomem *rgmii_base; 103 void __iomem *mac_base; 104 int (*configure_func)(struct qcom_ethqos *ethqos); 105 106 unsigned int link_clk_rate; 107 struct clk *link_clk; 108 struct phy *serdes_phy; 109 unsigned int speed; 110 phy_interface_t phy_mode; 111 112 const struct ethqos_emac_por *por; 113 unsigned int num_por; 114 bool rgmii_config_loopback_en; 115 bool has_emac_ge_3; 116 }; 117 118 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 119 { 120 return readl(ethqos->rgmii_base + offset); 121 } 122 123 static void rgmii_writel(struct qcom_ethqos *ethqos, 124 int value, unsigned int offset) 125 { 126 writel(value, ethqos->rgmii_base + offset); 127 } 128 129 static void rgmii_updatel(struct qcom_ethqos *ethqos, 130 int mask, int val, unsigned int offset) 131 { 132 unsigned int temp; 133 134 temp = rgmii_readl(ethqos, offset); 135 temp = (temp & ~(mask)) | val; 136 rgmii_writel(ethqos, temp, offset); 137 } 138 139 static void rgmii_dump(void *priv) 140 { 141 struct qcom_ethqos *ethqos = priv; 142 struct device *dev = ðqos->pdev->dev; 143 144 dev_dbg(dev, "Rgmii register dump\n"); 145 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 146 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 147 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 148 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 149 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 150 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 151 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 152 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 153 dev_dbg(dev, "SDC4_STATUS: %x\n", 154 rgmii_readl(ethqos, SDC4_STATUS)); 155 dev_dbg(dev, "SDCC_USR_CTL: %x\n", 156 rgmii_readl(ethqos, SDCC_USR_CTL)); 157 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 158 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 159 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 160 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 161 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 162 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 163 } 164 165 /* Clock rates */ 166 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 167 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 168 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 169 170 static void 171 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed) 172 { 173 switch (speed) { 174 case SPEED_1000: 175 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ; 176 break; 177 178 case SPEED_100: 179 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 180 break; 181 182 case SPEED_10: 183 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 184 break; 185 } 186 187 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate); 188 } 189 190 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 191 { 192 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 193 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 194 } 195 196 static const struct ethqos_emac_por emac_v2_3_0_por[] = { 197 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 198 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 199 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 200 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 201 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 202 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 203 }; 204 205 static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 206 .por = emac_v2_3_0_por, 207 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 208 .rgmii_config_loopback_en = true, 209 .has_emac_ge_3 = false, 210 }; 211 212 static const struct ethqos_emac_por emac_v2_1_0_por[] = { 213 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 214 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 215 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 216 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 217 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 218 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 219 }; 220 221 static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 222 .por = emac_v2_1_0_por, 223 .num_por = ARRAY_SIZE(emac_v2_1_0_por), 224 .rgmii_config_loopback_en = false, 225 .has_emac_ge_3 = false, 226 }; 227 228 static const struct ethqos_emac_por emac_v3_0_0_por[] = { 229 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 230 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 231 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 232 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 233 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 234 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 235 }; 236 237 static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 238 .por = emac_v3_0_0_por, 239 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 240 .rgmii_config_loopback_en = false, 241 .has_emac_ge_3 = true, 242 .dwmac4_addrs = { 243 .dma_chan = 0x00008100, 244 .dma_chan_offset = 0x1000, 245 .mtl_chan = 0x00008000, 246 .mtl_chan_offset = 0x1000, 247 .mtl_ets_ctrl = 0x00008010, 248 .mtl_ets_ctrl_offset = 0x1000, 249 .mtl_txq_weight = 0x00008018, 250 .mtl_txq_weight_offset = 0x1000, 251 .mtl_send_slp_cred = 0x0000801c, 252 .mtl_send_slp_cred_offset = 0x1000, 253 .mtl_high_cred = 0x00008020, 254 .mtl_high_cred_offset = 0x1000, 255 .mtl_low_cred = 0x00008024, 256 .mtl_low_cred_offset = 0x1000, 257 }, 258 }; 259 260 static const struct ethqos_emac_por emac_v4_0_0_por[] = { 261 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 262 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 263 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 264 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 265 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 266 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 267 }; 268 269 static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 270 .por = emac_v4_0_0_por, 271 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 272 .rgmii_config_loopback_en = false, 273 .has_emac_ge_3 = true, 274 .link_clk_name = "phyaux", 275 .has_integrated_pcs = true, 276 .dma_addr_width = 36, 277 .dwmac4_addrs = { 278 .dma_chan = 0x00008100, 279 .dma_chan_offset = 0x1000, 280 .mtl_chan = 0x00008000, 281 .mtl_chan_offset = 0x1000, 282 .mtl_ets_ctrl = 0x00008010, 283 .mtl_ets_ctrl_offset = 0x1000, 284 .mtl_txq_weight = 0x00008018, 285 .mtl_txq_weight_offset = 0x1000, 286 .mtl_send_slp_cred = 0x0000801c, 287 .mtl_send_slp_cred_offset = 0x1000, 288 .mtl_high_cred = 0x00008020, 289 .mtl_high_cred_offset = 0x1000, 290 .mtl_low_cred = 0x00008024, 291 .mtl_low_cred_offset = 0x1000, 292 }, 293 }; 294 295 static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 296 { 297 struct device *dev = ðqos->pdev->dev; 298 unsigned int val; 299 int retry = 1000; 300 301 /* Set CDR_EN */ 302 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 303 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 304 305 /* Set CDR_EXT_EN */ 306 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 307 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 308 309 /* Clear CK_OUT_EN */ 310 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 311 0, SDCC_HC_REG_DLL_CONFIG); 312 313 /* Set DLL_EN */ 314 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 315 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 316 317 if (!ethqos->has_emac_ge_3) { 318 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 319 0, SDCC_HC_REG_DLL_CONFIG); 320 321 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 322 0, SDCC_HC_REG_DLL_CONFIG); 323 } 324 325 /* Wait for CK_OUT_EN clear */ 326 do { 327 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 328 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 329 if (!val) 330 break; 331 mdelay(1); 332 retry--; 333 } while (retry > 0); 334 if (!retry) 335 dev_err(dev, "Clear CK_OUT_EN timedout\n"); 336 337 /* Set CK_OUT_EN */ 338 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 339 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 340 341 /* Wait for CK_OUT_EN set */ 342 retry = 1000; 343 do { 344 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 345 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 346 if (val) 347 break; 348 mdelay(1); 349 retry--; 350 } while (retry > 0); 351 if (!retry) 352 dev_err(dev, "Set CK_OUT_EN timedout\n"); 353 354 /* Set DDR_CAL_EN */ 355 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 356 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 357 358 if (!ethqos->has_emac_ge_3) { 359 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 360 0, SDCC_HC_REG_DLL_CONFIG2); 361 362 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 363 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 364 365 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 366 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 367 368 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 369 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 370 SDCC_HC_REG_DLL_CONFIG2); 371 } 372 373 return 0; 374 } 375 376 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 377 { 378 struct device *dev = ðqos->pdev->dev; 379 int phase_shift; 380 int loopback; 381 382 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 383 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 384 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 385 phase_shift = 0; 386 else 387 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 388 389 /* Disable loopback mode */ 390 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 391 0, RGMII_IO_MACRO_CONFIG2); 392 393 /* Determine if this platform wants loopback enabled after programming */ 394 if (ethqos->rgmii_config_loopback_en) 395 loopback = RGMII_CONFIG_LOOPBACK_EN; 396 else 397 loopback = 0; 398 399 /* Select RGMII, write 0 to interface select */ 400 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 401 0, RGMII_IO_MACRO_CONFIG); 402 403 switch (ethqos->speed) { 404 case SPEED_1000: 405 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 406 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 407 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 408 0, RGMII_IO_MACRO_CONFIG); 409 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 410 RGMII_CONFIG_POS_NEG_DATA_SEL, 411 RGMII_IO_MACRO_CONFIG); 412 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 413 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 414 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 415 0, RGMII_IO_MACRO_CONFIG2); 416 417 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 418 phase_shift, RGMII_IO_MACRO_CONFIG2); 419 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 420 0, RGMII_IO_MACRO_CONFIG2); 421 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 422 RGMII_CONFIG2_RX_PROG_SWAP, 423 RGMII_IO_MACRO_CONFIG2); 424 425 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 426 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 427 */ 428 if (ethqos->has_emac_ge_3) { 429 /* 0.9 ns */ 430 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 431 115, SDCC_HC_REG_DDR_CONFIG); 432 } else { 433 /* 1.8 ns */ 434 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 435 57, SDCC_HC_REG_DDR_CONFIG); 436 } 437 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 438 SDCC_DDR_CONFIG_PRG_DLY_EN, 439 SDCC_HC_REG_DDR_CONFIG); 440 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 441 loopback, RGMII_IO_MACRO_CONFIG); 442 break; 443 444 case SPEED_100: 445 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 446 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 447 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 448 RGMII_CONFIG_BYPASS_TX_ID_EN, 449 RGMII_IO_MACRO_CONFIG); 450 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 451 0, RGMII_IO_MACRO_CONFIG); 452 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 453 0, RGMII_IO_MACRO_CONFIG); 454 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 455 0, RGMII_IO_MACRO_CONFIG2); 456 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 457 phase_shift, RGMII_IO_MACRO_CONFIG2); 458 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 459 BIT(6), RGMII_IO_MACRO_CONFIG); 460 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 461 0, RGMII_IO_MACRO_CONFIG2); 462 463 if (ethqos->has_emac_ge_3) 464 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 465 RGMII_CONFIG2_RX_PROG_SWAP, 466 RGMII_IO_MACRO_CONFIG2); 467 else 468 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 469 0, RGMII_IO_MACRO_CONFIG2); 470 471 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 472 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 473 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 474 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 475 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 476 SDCC_HC_REG_DDR_CONFIG); 477 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 478 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 479 SDCC_HC_REG_DDR_CONFIG); 480 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 481 loopback, RGMII_IO_MACRO_CONFIG); 482 break; 483 484 case SPEED_10: 485 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 486 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 487 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 488 RGMII_CONFIG_BYPASS_TX_ID_EN, 489 RGMII_IO_MACRO_CONFIG); 490 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 491 0, RGMII_IO_MACRO_CONFIG); 492 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 493 0, RGMII_IO_MACRO_CONFIG); 494 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 495 0, RGMII_IO_MACRO_CONFIG2); 496 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 497 phase_shift, RGMII_IO_MACRO_CONFIG2); 498 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 499 BIT(12) | GENMASK(9, 8), 500 RGMII_IO_MACRO_CONFIG); 501 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 502 0, RGMII_IO_MACRO_CONFIG2); 503 if (ethqos->has_emac_ge_3) 504 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 505 RGMII_CONFIG2_RX_PROG_SWAP, 506 RGMII_IO_MACRO_CONFIG2); 507 else 508 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 509 0, RGMII_IO_MACRO_CONFIG2); 510 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 511 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 512 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 513 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 514 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 515 SDCC_HC_REG_DDR_CONFIG); 516 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 517 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 518 SDCC_HC_REG_DDR_CONFIG); 519 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 520 loopback, RGMII_IO_MACRO_CONFIG); 521 break; 522 default: 523 dev_err(dev, "Invalid speed %d\n", ethqos->speed); 524 return -EINVAL; 525 } 526 527 return 0; 528 } 529 530 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos) 531 { 532 struct device *dev = ðqos->pdev->dev; 533 volatile unsigned int dll_lock; 534 unsigned int i, retry = 1000; 535 536 /* Reset to POR values and enable clk */ 537 for (i = 0; i < ethqos->num_por; i++) 538 rgmii_writel(ethqos, ethqos->por[i].value, 539 ethqos->por[i].offset); 540 ethqos_set_func_clk_en(ethqos); 541 542 /* Initialize the DLL first */ 543 544 /* Set DLL_RST */ 545 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 546 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 547 548 /* Set PDN */ 549 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 550 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 551 552 if (ethqos->has_emac_ge_3) { 553 if (ethqos->speed == SPEED_1000) { 554 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 555 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 556 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 557 } else { 558 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 559 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 560 } 561 } 562 563 /* Clear DLL_RST */ 564 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 565 SDCC_HC_REG_DLL_CONFIG); 566 567 /* Clear PDN */ 568 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 569 SDCC_HC_REG_DLL_CONFIG); 570 571 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 572 /* Set DLL_EN */ 573 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 574 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 575 576 /* Set CK_OUT_EN */ 577 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 578 SDCC_DLL_CONFIG_CK_OUT_EN, 579 SDCC_HC_REG_DLL_CONFIG); 580 581 /* Set USR_CTL bit 26 with mask of 3 bits */ 582 if (!ethqos->has_emac_ge_3) 583 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 584 SDCC_USR_CTL); 585 586 /* wait for DLL LOCK */ 587 do { 588 mdelay(1); 589 dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 590 if (dll_lock & SDC4_STATUS_DLL_LOCK) 591 break; 592 retry--; 593 } while (retry > 0); 594 if (!retry) 595 dev_err(dev, "Timeout while waiting for DLL lock\n"); 596 } 597 598 if (ethqos->speed == SPEED_1000) 599 ethqos_dll_configure(ethqos); 600 601 ethqos_rgmii_macro_init(ethqos); 602 603 return 0; 604 } 605 606 /* On interface toggle MAC registers gets reset. 607 * Configure MAC block for SGMII on ethernet phy link up 608 */ 609 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos) 610 { 611 int val; 612 613 val = readl(ethqos->mac_base + MAC_CTRL_REG); 614 615 switch (ethqos->speed) { 616 case SPEED_1000: 617 val &= ~ETHQOS_MAC_CTRL_PORT_SEL; 618 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 619 RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 620 RGMII_IO_MACRO_CONFIG2); 621 break; 622 case SPEED_100: 623 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE; 624 break; 625 case SPEED_10: 626 val |= ETHQOS_MAC_CTRL_PORT_SEL; 627 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE; 628 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, 629 FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 630 SGMII_10M_RX_CLK_DVDR), 631 RGMII_IO_MACRO_CONFIG); 632 break; 633 } 634 635 writel(val, ethqos->mac_base + MAC_CTRL_REG); 636 637 return val; 638 } 639 640 static int ethqos_configure(struct qcom_ethqos *ethqos) 641 { 642 return ethqos->configure_func(ethqos); 643 } 644 645 static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) 646 { 647 struct qcom_ethqos *ethqos = priv; 648 649 ethqos->speed = speed; 650 ethqos_update_link_clk(ethqos, speed); 651 ethqos_configure(ethqos); 652 } 653 654 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) 655 { 656 struct qcom_ethqos *ethqos = priv; 657 int ret; 658 659 ret = phy_init(ethqos->serdes_phy); 660 if (ret) 661 return ret; 662 663 ret = phy_power_on(ethqos->serdes_phy); 664 if (ret) 665 return ret; 666 667 return phy_set_speed(ethqos->serdes_phy, ethqos->speed); 668 } 669 670 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv) 671 { 672 struct qcom_ethqos *ethqos = priv; 673 674 phy_power_off(ethqos->serdes_phy); 675 phy_exit(ethqos->serdes_phy); 676 } 677 678 static int ethqos_clks_config(void *priv, bool enabled) 679 { 680 struct qcom_ethqos *ethqos = priv; 681 int ret = 0; 682 683 if (enabled) { 684 ret = clk_prepare_enable(ethqos->link_clk); 685 if (ret) { 686 dev_err(ðqos->pdev->dev, "link_clk enable failed\n"); 687 return ret; 688 } 689 690 /* Enable functional clock to prevent DMA reset to timeout due 691 * to lacking PHY clock after the hardware block has been power 692 * cycled. The actual configuration will be adjusted once 693 * ethqos_fix_mac_speed() is invoked. 694 */ 695 ethqos_set_func_clk_en(ethqos); 696 } else { 697 clk_disable_unprepare(ethqos->link_clk); 698 } 699 700 return ret; 701 } 702 703 static void ethqos_clks_disable(void *data) 704 { 705 ethqos_clks_config(data, false); 706 } 707 708 static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) 709 { 710 struct plat_stmmacenet_data *plat_dat = priv->plat; 711 int err; 712 713 if (!plat_dat->clk_ptp_ref) 714 return; 715 716 /* Max the PTP ref clock out to get the best resolution possible */ 717 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX); 718 if (err) 719 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err); 720 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref); 721 722 netdev_dbg(priv->dev, "PTP rate %d\n", plat_dat->clk_ptp_rate); 723 } 724 725 static int qcom_ethqos_probe(struct platform_device *pdev) 726 { 727 struct device_node *np = pdev->dev.of_node; 728 const struct ethqos_emac_driver_data *data; 729 struct plat_stmmacenet_data *plat_dat; 730 struct stmmac_resources stmmac_res; 731 struct device *dev = &pdev->dev; 732 struct qcom_ethqos *ethqos; 733 int ret; 734 735 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 736 if (ret) 737 return dev_err_probe(dev, ret, 738 "Failed to get platform resources\n"); 739 740 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 741 if (IS_ERR(plat_dat)) { 742 return dev_err_probe(dev, PTR_ERR(plat_dat), 743 "dt configuration failed\n"); 744 } 745 746 plat_dat->clks_config = ethqos_clks_config; 747 748 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 749 if (!ethqos) 750 return -ENOMEM; 751 752 ret = of_get_phy_mode(np, ðqos->phy_mode); 753 if (ret) 754 return dev_err_probe(dev, ret, "Failed to get phy mode\n"); 755 switch (ethqos->phy_mode) { 756 case PHY_INTERFACE_MODE_RGMII: 757 case PHY_INTERFACE_MODE_RGMII_ID: 758 case PHY_INTERFACE_MODE_RGMII_RXID: 759 case PHY_INTERFACE_MODE_RGMII_TXID: 760 ethqos->configure_func = ethqos_configure_rgmii; 761 break; 762 case PHY_INTERFACE_MODE_SGMII: 763 ethqos->configure_func = ethqos_configure_sgmii; 764 break; 765 default: 766 dev_err(dev, "Unsupported phy mode %s\n", 767 phy_modes(ethqos->phy_mode)); 768 return -EINVAL; 769 } 770 771 ethqos->pdev = pdev; 772 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 773 if (IS_ERR(ethqos->rgmii_base)) 774 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), 775 "Failed to map rgmii resource\n"); 776 777 ethqos->mac_base = stmmac_res.addr; 778 779 data = of_device_get_match_data(dev); 780 ethqos->por = data->por; 781 ethqos->num_por = data->num_por; 782 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 783 ethqos->has_emac_ge_3 = data->has_emac_ge_3; 784 785 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); 786 if (IS_ERR(ethqos->link_clk)) 787 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), 788 "Failed to get link_clk\n"); 789 790 ret = ethqos_clks_config(ethqos, true); 791 if (ret) 792 return ret; 793 794 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 795 if (ret) 796 return ret; 797 798 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes"); 799 if (IS_ERR(ethqos->serdes_phy)) 800 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy), 801 "Failed to get serdes phy\n"); 802 803 ethqos->speed = SPEED_1000; 804 ethqos_update_link_clk(ethqos, SPEED_1000); 805 ethqos_set_func_clk_en(ethqos); 806 807 plat_dat->bsp_priv = ethqos; 808 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 809 plat_dat->dump_debug_regs = rgmii_dump; 810 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; 811 plat_dat->has_gmac4 = 1; 812 if (ethqos->has_emac_ge_3) 813 plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 814 plat_dat->pmt = 1; 815 if (of_property_read_bool(np, "snps,tso")) 816 plat_dat->flags |= STMMAC_FLAG_TSO_EN; 817 if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 818 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI; 819 if (data->has_integrated_pcs) 820 plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS; 821 if (data->dma_addr_width) 822 plat_dat->host_dma_width = data->dma_addr_width; 823 824 if (ethqos->serdes_phy) { 825 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; 826 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; 827 } 828 829 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); 830 } 831 832 static const struct of_device_id qcom_ethqos_match[] = { 833 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 834 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, 835 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 836 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 837 { } 838 }; 839 MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 840 841 static struct platform_driver qcom_ethqos_driver = { 842 .probe = qcom_ethqos_probe, 843 .driver = { 844 .name = "qcom-ethqos", 845 .pm = &stmmac_pltfr_pm_ops, 846 .of_match_table = qcom_ethqos_match, 847 }, 848 }; 849 module_platform_driver(qcom_ethqos_driver); 850 851 MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 852 MODULE_LICENSE("GPL v2"); 853