1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-19, Linaro Limited 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_device.h> 7 #include <linux/platform_device.h> 8 #include <linux/phy.h> 9 #include <linux/phy/phy.h> 10 #include <linux/property.h> 11 12 #include "stmmac.h" 13 #include "stmmac_platform.h" 14 15 #define RGMII_IO_MACRO_CONFIG 0x0 16 #define SDCC_HC_REG_DLL_CONFIG 0x4 17 #define SDCC_TEST_CTL 0x8 18 #define SDCC_HC_REG_DDR_CONFIG 0xC 19 #define SDCC_HC_REG_DLL_CONFIG2 0x10 20 #define SDC4_STATUS 0x14 21 #define SDCC_USR_CTL 0x18 22 #define RGMII_IO_MACRO_CONFIG2 0x1C 23 #define RGMII_IO_MACRO_DEBUG1 0x20 24 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 25 26 /* RGMII_IO_MACRO_CONFIG fields */ 27 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 28 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 29 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 30 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 31 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 32 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 33 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 34 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 35 #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 36 #define RGMII_CONFIG_PROG_SWAP BIT(1) 37 #define RGMII_CONFIG_DDR_MODE BIT(0) 38 39 /* SDCC_HC_REG_DLL_CONFIG fields */ 40 #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 41 #define SDCC_DLL_CONFIG_PDN BIT(29) 42 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 43 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 44 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 45 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 46 #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 47 #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 48 #define SDCC_DLL_MCLK_GATING_EN BIT(5) 49 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 50 51 /* SDCC_HC_REG_DDR_CONFIG fields */ 52 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 53 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 55 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 56 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 57 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 58 59 /* SDCC_HC_REG_DLL_CONFIG2 fields */ 60 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 61 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 62 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 63 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 64 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 65 66 /* SDC4_STATUS bits */ 67 #define SDC4_STATUS_DLL_LOCK BIT(7) 68 69 /* RGMII_IO_MACRO_CONFIG2 fields */ 70 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 71 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 72 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 73 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 74 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 75 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 76 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 77 78 /* MAC_CTRL_REG bits */ 79 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14) 80 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15) 81 82 struct ethqos_emac_por { 83 unsigned int offset; 84 unsigned int value; 85 }; 86 87 struct ethqos_emac_driver_data { 88 const struct ethqos_emac_por *por; 89 unsigned int num_por; 90 bool rgmii_config_loopback_en; 91 bool has_emac_ge_3; 92 const char *link_clk_name; 93 bool has_integrated_pcs; 94 struct dwmac4_addrs dwmac4_addrs; 95 }; 96 97 struct qcom_ethqos { 98 struct platform_device *pdev; 99 void __iomem *rgmii_base; 100 void __iomem *mac_base; 101 int (*configure_func)(struct qcom_ethqos *ethqos); 102 103 unsigned int link_clk_rate; 104 struct clk *link_clk; 105 struct phy *serdes_phy; 106 unsigned int speed; 107 int phy_mode; 108 109 const struct ethqos_emac_por *por; 110 unsigned int num_por; 111 bool rgmii_config_loopback_en; 112 bool has_emac_ge_3; 113 }; 114 115 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 116 { 117 return readl(ethqos->rgmii_base + offset); 118 } 119 120 static void rgmii_writel(struct qcom_ethqos *ethqos, 121 int value, unsigned int offset) 122 { 123 writel(value, ethqos->rgmii_base + offset); 124 } 125 126 static void rgmii_updatel(struct qcom_ethqos *ethqos, 127 int mask, int val, unsigned int offset) 128 { 129 unsigned int temp; 130 131 temp = rgmii_readl(ethqos, offset); 132 temp = (temp & ~(mask)) | val; 133 rgmii_writel(ethqos, temp, offset); 134 } 135 136 static void rgmii_dump(void *priv) 137 { 138 struct qcom_ethqos *ethqos = priv; 139 struct device *dev = ðqos->pdev->dev; 140 141 dev_dbg(dev, "Rgmii register dump\n"); 142 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 143 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 144 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 145 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 146 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 147 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 148 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 149 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 150 dev_dbg(dev, "SDC4_STATUS: %x\n", 151 rgmii_readl(ethqos, SDC4_STATUS)); 152 dev_dbg(dev, "SDCC_USR_CTL: %x\n", 153 rgmii_readl(ethqos, SDCC_USR_CTL)); 154 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 155 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 156 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 157 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 158 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 159 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 160 } 161 162 /* Clock rates */ 163 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 164 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 165 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 166 167 static void 168 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed) 169 { 170 switch (speed) { 171 case SPEED_1000: 172 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ; 173 break; 174 175 case SPEED_100: 176 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 177 break; 178 179 case SPEED_10: 180 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 181 break; 182 } 183 184 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate); 185 } 186 187 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 188 { 189 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 190 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 191 } 192 193 static const struct ethqos_emac_por emac_v2_3_0_por[] = { 194 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 195 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 196 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 197 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 198 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 199 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 200 }; 201 202 static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 203 .por = emac_v2_3_0_por, 204 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 205 .rgmii_config_loopback_en = true, 206 .has_emac_ge_3 = false, 207 }; 208 209 static const struct ethqos_emac_por emac_v2_1_0_por[] = { 210 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 211 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 212 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 213 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 214 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 215 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 216 }; 217 218 static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 219 .por = emac_v2_1_0_por, 220 .num_por = ARRAY_SIZE(emac_v2_1_0_por), 221 .rgmii_config_loopback_en = false, 222 .has_emac_ge_3 = false, 223 }; 224 225 static const struct ethqos_emac_por emac_v3_0_0_por[] = { 226 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 227 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 228 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 229 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 230 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 231 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 232 }; 233 234 static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 235 .por = emac_v3_0_0_por, 236 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 237 .rgmii_config_loopback_en = false, 238 .has_emac_ge_3 = true, 239 .dwmac4_addrs = { 240 .dma_chan = 0x00008100, 241 .dma_chan_offset = 0x1000, 242 .mtl_chan = 0x00008000, 243 .mtl_chan_offset = 0x1000, 244 .mtl_ets_ctrl = 0x00008010, 245 .mtl_ets_ctrl_offset = 0x1000, 246 .mtl_txq_weight = 0x00008018, 247 .mtl_txq_weight_offset = 0x1000, 248 .mtl_send_slp_cred = 0x0000801c, 249 .mtl_send_slp_cred_offset = 0x1000, 250 .mtl_high_cred = 0x00008020, 251 .mtl_high_cred_offset = 0x1000, 252 .mtl_low_cred = 0x00008024, 253 .mtl_low_cred_offset = 0x1000, 254 }, 255 }; 256 257 static const struct ethqos_emac_por emac_v4_0_0_por[] = { 258 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 259 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 260 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 261 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 262 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 263 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 264 }; 265 266 static const struct ethqos_emac_driver_data emac_v4_0_0_data = { 267 .por = emac_v4_0_0_por, 268 .num_por = ARRAY_SIZE(emac_v3_0_0_por), 269 .rgmii_config_loopback_en = false, 270 .has_emac_ge_3 = true, 271 .link_clk_name = "phyaux", 272 .has_integrated_pcs = true, 273 .dwmac4_addrs = { 274 .dma_chan = 0x00008100, 275 .dma_chan_offset = 0x1000, 276 .mtl_chan = 0x00008000, 277 .mtl_chan_offset = 0x1000, 278 .mtl_ets_ctrl = 0x00008010, 279 .mtl_ets_ctrl_offset = 0x1000, 280 .mtl_txq_weight = 0x00008018, 281 .mtl_txq_weight_offset = 0x1000, 282 .mtl_send_slp_cred = 0x0000801c, 283 .mtl_send_slp_cred_offset = 0x1000, 284 .mtl_high_cred = 0x00008020, 285 .mtl_high_cred_offset = 0x1000, 286 .mtl_low_cred = 0x00008024, 287 .mtl_low_cred_offset = 0x1000, 288 }, 289 }; 290 291 static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 292 { 293 struct device *dev = ðqos->pdev->dev; 294 unsigned int val; 295 int retry = 1000; 296 297 /* Set CDR_EN */ 298 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 299 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 300 301 /* Set CDR_EXT_EN */ 302 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 303 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 304 305 /* Clear CK_OUT_EN */ 306 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 307 0, SDCC_HC_REG_DLL_CONFIG); 308 309 /* Set DLL_EN */ 310 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 311 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 312 313 if (!ethqos->has_emac_ge_3) { 314 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 315 0, SDCC_HC_REG_DLL_CONFIG); 316 317 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 318 0, SDCC_HC_REG_DLL_CONFIG); 319 } 320 321 /* Wait for CK_OUT_EN clear */ 322 do { 323 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 324 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 325 if (!val) 326 break; 327 mdelay(1); 328 retry--; 329 } while (retry > 0); 330 if (!retry) 331 dev_err(dev, "Clear CK_OUT_EN timedout\n"); 332 333 /* Set CK_OUT_EN */ 334 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 335 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 336 337 /* Wait for CK_OUT_EN set */ 338 retry = 1000; 339 do { 340 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 341 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 342 if (val) 343 break; 344 mdelay(1); 345 retry--; 346 } while (retry > 0); 347 if (!retry) 348 dev_err(dev, "Set CK_OUT_EN timedout\n"); 349 350 /* Set DDR_CAL_EN */ 351 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 352 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 353 354 if (!ethqos->has_emac_ge_3) { 355 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 356 0, SDCC_HC_REG_DLL_CONFIG2); 357 358 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 359 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 360 361 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 362 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 363 364 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 365 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 366 SDCC_HC_REG_DLL_CONFIG2); 367 } 368 369 return 0; 370 } 371 372 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 373 { 374 struct device *dev = ðqos->pdev->dev; 375 int phase_shift; 376 int loopback; 377 378 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 379 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 380 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 381 phase_shift = 0; 382 else 383 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 384 385 /* Disable loopback mode */ 386 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 387 0, RGMII_IO_MACRO_CONFIG2); 388 389 /* Determine if this platform wants loopback enabled after programming */ 390 if (ethqos->rgmii_config_loopback_en) 391 loopback = RGMII_CONFIG_LOOPBACK_EN; 392 else 393 loopback = 0; 394 395 /* Select RGMII, write 0 to interface select */ 396 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 397 0, RGMII_IO_MACRO_CONFIG); 398 399 switch (ethqos->speed) { 400 case SPEED_1000: 401 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 402 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 403 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 404 0, RGMII_IO_MACRO_CONFIG); 405 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 406 RGMII_CONFIG_POS_NEG_DATA_SEL, 407 RGMII_IO_MACRO_CONFIG); 408 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 409 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 410 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 411 0, RGMII_IO_MACRO_CONFIG2); 412 413 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 414 phase_shift, RGMII_IO_MACRO_CONFIG2); 415 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 416 0, RGMII_IO_MACRO_CONFIG2); 417 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 418 RGMII_CONFIG2_RX_PROG_SWAP, 419 RGMII_IO_MACRO_CONFIG2); 420 421 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 422 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 423 */ 424 if (ethqos->has_emac_ge_3) { 425 /* 0.9 ns */ 426 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 427 115, SDCC_HC_REG_DDR_CONFIG); 428 } else { 429 /* 1.8 ns */ 430 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 431 57, SDCC_HC_REG_DDR_CONFIG); 432 } 433 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 434 SDCC_DDR_CONFIG_PRG_DLY_EN, 435 SDCC_HC_REG_DDR_CONFIG); 436 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 437 loopback, RGMII_IO_MACRO_CONFIG); 438 break; 439 440 case SPEED_100: 441 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 442 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 443 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 444 RGMII_CONFIG_BYPASS_TX_ID_EN, 445 RGMII_IO_MACRO_CONFIG); 446 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 447 0, RGMII_IO_MACRO_CONFIG); 448 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 449 0, RGMII_IO_MACRO_CONFIG); 450 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 451 0, RGMII_IO_MACRO_CONFIG2); 452 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 453 phase_shift, RGMII_IO_MACRO_CONFIG2); 454 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 455 BIT(6), RGMII_IO_MACRO_CONFIG); 456 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 457 0, RGMII_IO_MACRO_CONFIG2); 458 459 if (ethqos->has_emac_ge_3) 460 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 461 RGMII_CONFIG2_RX_PROG_SWAP, 462 RGMII_IO_MACRO_CONFIG2); 463 else 464 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 465 0, RGMII_IO_MACRO_CONFIG2); 466 467 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 468 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 469 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 470 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 471 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 472 SDCC_HC_REG_DDR_CONFIG); 473 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 474 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 475 SDCC_HC_REG_DDR_CONFIG); 476 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 477 loopback, RGMII_IO_MACRO_CONFIG); 478 break; 479 480 case SPEED_10: 481 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 482 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 483 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 484 RGMII_CONFIG_BYPASS_TX_ID_EN, 485 RGMII_IO_MACRO_CONFIG); 486 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 487 0, RGMII_IO_MACRO_CONFIG); 488 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 489 0, RGMII_IO_MACRO_CONFIG); 490 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 491 0, RGMII_IO_MACRO_CONFIG2); 492 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 493 phase_shift, RGMII_IO_MACRO_CONFIG2); 494 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 495 BIT(12) | GENMASK(9, 8), 496 RGMII_IO_MACRO_CONFIG); 497 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 498 0, RGMII_IO_MACRO_CONFIG2); 499 if (ethqos->has_emac_ge_3) 500 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 501 RGMII_CONFIG2_RX_PROG_SWAP, 502 RGMII_IO_MACRO_CONFIG2); 503 else 504 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 505 0, RGMII_IO_MACRO_CONFIG2); 506 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 507 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 508 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 509 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 510 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 511 SDCC_HC_REG_DDR_CONFIG); 512 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 513 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 514 SDCC_HC_REG_DDR_CONFIG); 515 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 516 loopback, RGMII_IO_MACRO_CONFIG); 517 break; 518 default: 519 dev_err(dev, "Invalid speed %d\n", ethqos->speed); 520 return -EINVAL; 521 } 522 523 return 0; 524 } 525 526 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos) 527 { 528 struct device *dev = ðqos->pdev->dev; 529 volatile unsigned int dll_lock; 530 unsigned int i, retry = 1000; 531 532 /* Reset to POR values and enable clk */ 533 for (i = 0; i < ethqos->num_por; i++) 534 rgmii_writel(ethqos, ethqos->por[i].value, 535 ethqos->por[i].offset); 536 ethqos_set_func_clk_en(ethqos); 537 538 /* Initialize the DLL first */ 539 540 /* Set DLL_RST */ 541 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 542 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 543 544 /* Set PDN */ 545 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 546 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 547 548 if (ethqos->has_emac_ge_3) { 549 if (ethqos->speed == SPEED_1000) { 550 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 551 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 552 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 553 } else { 554 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 555 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 556 } 557 } 558 559 /* Clear DLL_RST */ 560 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 561 SDCC_HC_REG_DLL_CONFIG); 562 563 /* Clear PDN */ 564 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 565 SDCC_HC_REG_DLL_CONFIG); 566 567 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 568 /* Set DLL_EN */ 569 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 570 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 571 572 /* Set CK_OUT_EN */ 573 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 574 SDCC_DLL_CONFIG_CK_OUT_EN, 575 SDCC_HC_REG_DLL_CONFIG); 576 577 /* Set USR_CTL bit 26 with mask of 3 bits */ 578 if (!ethqos->has_emac_ge_3) 579 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 580 SDCC_USR_CTL); 581 582 /* wait for DLL LOCK */ 583 do { 584 mdelay(1); 585 dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 586 if (dll_lock & SDC4_STATUS_DLL_LOCK) 587 break; 588 retry--; 589 } while (retry > 0); 590 if (!retry) 591 dev_err(dev, "Timeout while waiting for DLL lock\n"); 592 } 593 594 if (ethqos->speed == SPEED_1000) 595 ethqos_dll_configure(ethqos); 596 597 ethqos_rgmii_macro_init(ethqos); 598 599 return 0; 600 } 601 602 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos) 603 { 604 int val; 605 606 val = readl(ethqos->mac_base + MAC_CTRL_REG); 607 608 switch (ethqos->speed) { 609 case SPEED_1000: 610 val &= ~ETHQOS_MAC_CTRL_PORT_SEL; 611 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 612 RGMII_CONFIG2_RGMII_CLK_SEL_CFG, 613 RGMII_IO_MACRO_CONFIG2); 614 break; 615 case SPEED_100: 616 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE; 617 break; 618 case SPEED_10: 619 val |= ETHQOS_MAC_CTRL_PORT_SEL; 620 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE; 621 break; 622 } 623 624 writel(val, ethqos->mac_base + MAC_CTRL_REG); 625 626 return val; 627 } 628 629 static int ethqos_configure(struct qcom_ethqos *ethqos) 630 { 631 return ethqos->configure_func(ethqos); 632 } 633 634 static void ethqos_fix_mac_speed(void *priv, unsigned int speed) 635 { 636 struct qcom_ethqos *ethqos = priv; 637 638 ethqos->speed = speed; 639 ethqos_update_link_clk(ethqos, speed); 640 ethqos_configure(ethqos); 641 } 642 643 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) 644 { 645 struct qcom_ethqos *ethqos = priv; 646 int ret; 647 648 ret = phy_init(ethqos->serdes_phy); 649 if (ret) 650 return ret; 651 652 ret = phy_power_on(ethqos->serdes_phy); 653 if (ret) 654 return ret; 655 656 return phy_set_speed(ethqos->serdes_phy, ethqos->speed); 657 } 658 659 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv) 660 { 661 struct qcom_ethqos *ethqos = priv; 662 663 phy_power_off(ethqos->serdes_phy); 664 phy_exit(ethqos->serdes_phy); 665 } 666 667 static int ethqos_clks_config(void *priv, bool enabled) 668 { 669 struct qcom_ethqos *ethqos = priv; 670 int ret = 0; 671 672 if (enabled) { 673 ret = clk_prepare_enable(ethqos->link_clk); 674 if (ret) { 675 dev_err(ðqos->pdev->dev, "link_clk enable failed\n"); 676 return ret; 677 } 678 679 /* Enable functional clock to prevent DMA reset to timeout due 680 * to lacking PHY clock after the hardware block has been power 681 * cycled. The actual configuration will be adjusted once 682 * ethqos_fix_mac_speed() is invoked. 683 */ 684 ethqos_set_func_clk_en(ethqos); 685 } else { 686 clk_disable_unprepare(ethqos->link_clk); 687 } 688 689 return ret; 690 } 691 692 static void ethqos_clks_disable(void *data) 693 { 694 ethqos_clks_config(data, false); 695 } 696 697 static int qcom_ethqos_probe(struct platform_device *pdev) 698 { 699 struct device_node *np = pdev->dev.of_node; 700 const struct ethqos_emac_driver_data *data; 701 struct plat_stmmacenet_data *plat_dat; 702 struct stmmac_resources stmmac_res; 703 struct device *dev = &pdev->dev; 704 struct qcom_ethqos *ethqos; 705 int ret; 706 707 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 708 if (ret) 709 return ret; 710 711 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); 712 if (IS_ERR(plat_dat)) { 713 dev_err(dev, "dt configuration failed\n"); 714 return PTR_ERR(plat_dat); 715 } 716 717 plat_dat->clks_config = ethqos_clks_config; 718 719 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 720 if (!ethqos) 721 return -ENOMEM; 722 723 ethqos->phy_mode = device_get_phy_mode(dev); 724 switch (ethqos->phy_mode) { 725 case PHY_INTERFACE_MODE_RGMII: 726 case PHY_INTERFACE_MODE_RGMII_ID: 727 case PHY_INTERFACE_MODE_RGMII_RXID: 728 case PHY_INTERFACE_MODE_RGMII_TXID: 729 ethqos->configure_func = ethqos_configure_rgmii; 730 break; 731 case PHY_INTERFACE_MODE_SGMII: 732 ethqos->configure_func = ethqos_configure_sgmii; 733 break; 734 case -ENODEV: 735 return -ENODEV; 736 default: 737 return -EINVAL; 738 } 739 740 ethqos->pdev = pdev; 741 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 742 if (IS_ERR(ethqos->rgmii_base)) 743 return PTR_ERR(ethqos->rgmii_base); 744 745 ethqos->mac_base = stmmac_res.addr; 746 747 data = of_device_get_match_data(dev); 748 ethqos->por = data->por; 749 ethqos->num_por = data->num_por; 750 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 751 ethqos->has_emac_ge_3 = data->has_emac_ge_3; 752 753 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); 754 if (IS_ERR(ethqos->link_clk)) 755 return PTR_ERR(ethqos->link_clk); 756 757 ret = ethqos_clks_config(ethqos, true); 758 if (ret) 759 return ret; 760 761 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 762 if (ret) 763 return ret; 764 765 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes"); 766 if (IS_ERR(ethqos->serdes_phy)) 767 return PTR_ERR(ethqos->serdes_phy); 768 769 ethqos->speed = SPEED_1000; 770 ethqos_update_link_clk(ethqos, SPEED_1000); 771 ethqos_set_func_clk_en(ethqos); 772 773 plat_dat->bsp_priv = ethqos; 774 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 775 plat_dat->dump_debug_regs = rgmii_dump; 776 plat_dat->has_gmac4 = 1; 777 if (ethqos->has_emac_ge_3) 778 plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 779 plat_dat->pmt = 1; 780 plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); 781 if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 782 plat_dat->rx_clk_runs_in_lpi = 1; 783 plat_dat->has_integrated_pcs = data->has_integrated_pcs; 784 785 if (ethqos->serdes_phy) { 786 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; 787 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown; 788 } 789 790 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); 791 } 792 793 static const struct of_device_id qcom_ethqos_match[] = { 794 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 795 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, 796 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 797 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 798 { } 799 }; 800 MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 801 802 static struct platform_driver qcom_ethqos_driver = { 803 .probe = qcom_ethqos_probe, 804 .driver = { 805 .name = "qcom-ethqos", 806 .pm = &stmmac_pltfr_pm_ops, 807 .of_match_table = qcom_ethqos_match, 808 }, 809 }; 810 module_platform_driver(qcom_ethqos_driver); 811 812 MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 813 MODULE_LICENSE("GPL v2"); 814