1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-19, Linaro Limited 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/of_device.h> 7 #include <linux/platform_device.h> 8 #include <linux/phy.h> 9 #include "stmmac.h" 10 #include "stmmac_platform.h" 11 12 #define RGMII_IO_MACRO_CONFIG 0x0 13 #define SDCC_HC_REG_DLL_CONFIG 0x4 14 #define SDCC_HC_REG_DDR_CONFIG 0xC 15 #define SDCC_HC_REG_DLL_CONFIG2 0x10 16 #define SDC4_STATUS 0x14 17 #define SDCC_USR_CTL 0x18 18 #define RGMII_IO_MACRO_CONFIG2 0x1C 19 #define RGMII_IO_MACRO_DEBUG1 0x20 20 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 21 22 /* RGMII_IO_MACRO_CONFIG fields */ 23 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 24 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 25 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 26 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 27 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 28 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 29 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 30 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 31 #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 32 #define RGMII_CONFIG_PROG_SWAP BIT(1) 33 #define RGMII_CONFIG_DDR_MODE BIT(0) 34 35 /* SDCC_HC_REG_DLL_CONFIG fields */ 36 #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 37 #define SDCC_DLL_CONFIG_PDN BIT(29) 38 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 39 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 40 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 41 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 42 #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 43 #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 44 #define SDCC_DLL_MCLK_GATING_EN BIT(5) 45 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 46 47 /* SDCC_HC_REG_DDR_CONFIG fields */ 48 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 49 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 50 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 51 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 52 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 53 54 /* SDCC_HC_REG_DLL_CONFIG2 fields */ 55 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 56 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 57 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 58 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 59 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 60 61 /* SDC4_STATUS bits */ 62 #define SDC4_STATUS_DLL_LOCK BIT(7) 63 64 /* RGMII_IO_MACRO_CONFIG2 fields */ 65 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 66 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 67 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 68 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 69 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 70 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 71 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 72 73 struct ethqos_emac_por { 74 unsigned int offset; 75 unsigned int value; 76 }; 77 78 struct ethqos_emac_driver_data { 79 const struct ethqos_emac_por *por; 80 unsigned int num_por; 81 }; 82 83 struct qcom_ethqos { 84 struct platform_device *pdev; 85 void __iomem *rgmii_base; 86 87 unsigned int rgmii_clk_rate; 88 struct clk *rgmii_clk; 89 unsigned int speed; 90 91 const struct ethqos_emac_por *por; 92 unsigned int num_por; 93 }; 94 95 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 96 { 97 return readl(ethqos->rgmii_base + offset); 98 } 99 100 static void rgmii_writel(struct qcom_ethqos *ethqos, 101 int value, unsigned int offset) 102 { 103 writel(value, ethqos->rgmii_base + offset); 104 } 105 106 static void rgmii_updatel(struct qcom_ethqos *ethqos, 107 int mask, int val, unsigned int offset) 108 { 109 unsigned int temp; 110 111 temp = rgmii_readl(ethqos, offset); 112 temp = (temp & ~(mask)) | val; 113 rgmii_writel(ethqos, temp, offset); 114 } 115 116 static void rgmii_dump(void *priv) 117 { 118 struct qcom_ethqos *ethqos = priv; 119 120 dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n"); 121 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n", 122 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 123 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 124 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 125 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 126 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 127 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 128 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 129 dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n", 130 rgmii_readl(ethqos, SDC4_STATUS)); 131 dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n", 132 rgmii_readl(ethqos, SDCC_USR_CTL)); 133 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 134 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 135 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 136 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 137 dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 138 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 139 } 140 141 /* Clock rates */ 142 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 143 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 144 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 145 146 static void 147 ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) 148 { 149 switch (speed) { 150 case SPEED_1000: 151 ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; 152 break; 153 154 case SPEED_100: 155 ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 156 break; 157 158 case SPEED_10: 159 ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 160 break; 161 } 162 163 clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); 164 } 165 166 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 167 { 168 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 169 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 170 } 171 172 static const struct ethqos_emac_por emac_v2_3_0_por[] = { 173 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 174 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 175 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 176 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 177 { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 178 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 179 }; 180 181 static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 182 .por = emac_v2_3_0_por, 183 .num_por = ARRAY_SIZE(emac_v2_3_0_por), 184 }; 185 186 static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 187 { 188 unsigned int val; 189 int retry = 1000; 190 191 /* Set CDR_EN */ 192 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 193 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 194 195 /* Set CDR_EXT_EN */ 196 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 197 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 198 199 /* Clear CK_OUT_EN */ 200 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 201 0, SDCC_HC_REG_DLL_CONFIG); 202 203 /* Set DLL_EN */ 204 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 205 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 206 207 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 208 0, SDCC_HC_REG_DLL_CONFIG); 209 210 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 211 0, SDCC_HC_REG_DLL_CONFIG); 212 213 /* Wait for CK_OUT_EN clear */ 214 do { 215 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 216 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 217 if (!val) 218 break; 219 mdelay(1); 220 retry--; 221 } while (retry > 0); 222 if (!retry) 223 dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n"); 224 225 /* Set CK_OUT_EN */ 226 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 227 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 228 229 /* Wait for CK_OUT_EN set */ 230 retry = 1000; 231 do { 232 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 233 val &= SDCC_DLL_CONFIG_CK_OUT_EN; 234 if (val) 235 break; 236 mdelay(1); 237 retry--; 238 } while (retry > 0); 239 if (!retry) 240 dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n"); 241 242 /* Set DDR_CAL_EN */ 243 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 244 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 245 246 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 247 0, SDCC_HC_REG_DLL_CONFIG2); 248 249 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 250 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 251 252 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 253 BIT(2), SDCC_HC_REG_DLL_CONFIG2); 254 255 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 256 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 257 SDCC_HC_REG_DLL_CONFIG2); 258 259 return 0; 260 } 261 262 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 263 { 264 /* Disable loopback mode */ 265 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 266 0, RGMII_IO_MACRO_CONFIG2); 267 268 /* Select RGMII, write 0 to interface select */ 269 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 270 0, RGMII_IO_MACRO_CONFIG); 271 272 switch (ethqos->speed) { 273 case SPEED_1000: 274 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 275 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 276 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 277 0, RGMII_IO_MACRO_CONFIG); 278 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 279 RGMII_CONFIG_POS_NEG_DATA_SEL, 280 RGMII_IO_MACRO_CONFIG); 281 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 282 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 283 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 284 0, RGMII_IO_MACRO_CONFIG2); 285 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 286 RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 287 RGMII_IO_MACRO_CONFIG2); 288 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 289 0, RGMII_IO_MACRO_CONFIG2); 290 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 291 RGMII_CONFIG2_RX_PROG_SWAP, 292 RGMII_IO_MACRO_CONFIG2); 293 294 /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */ 295 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 296 57, SDCC_HC_REG_DDR_CONFIG); 297 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 298 SDCC_DDR_CONFIG_PRG_DLY_EN, 299 SDCC_HC_REG_DDR_CONFIG); 300 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 301 RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); 302 break; 303 304 case SPEED_100: 305 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 306 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 307 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 308 RGMII_CONFIG_BYPASS_TX_ID_EN, 309 RGMII_IO_MACRO_CONFIG); 310 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 311 0, RGMII_IO_MACRO_CONFIG); 312 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 313 0, RGMII_IO_MACRO_CONFIG); 314 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 315 0, RGMII_IO_MACRO_CONFIG2); 316 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 317 RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 318 RGMII_IO_MACRO_CONFIG2); 319 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 320 BIT(6), RGMII_IO_MACRO_CONFIG); 321 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 322 0, RGMII_IO_MACRO_CONFIG2); 323 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 324 0, RGMII_IO_MACRO_CONFIG2); 325 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 326 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 327 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 328 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 329 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 330 SDCC_HC_REG_DDR_CONFIG); 331 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 332 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 333 SDCC_HC_REG_DDR_CONFIG); 334 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 335 RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); 336 break; 337 338 case SPEED_10: 339 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 340 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 341 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 342 RGMII_CONFIG_BYPASS_TX_ID_EN, 343 RGMII_IO_MACRO_CONFIG); 344 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 345 0, RGMII_IO_MACRO_CONFIG); 346 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 347 0, RGMII_IO_MACRO_CONFIG); 348 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 349 0, RGMII_IO_MACRO_CONFIG2); 350 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 351 0, RGMII_IO_MACRO_CONFIG2); 352 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 353 BIT(12) | GENMASK(9, 8), 354 RGMII_IO_MACRO_CONFIG); 355 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 356 0, RGMII_IO_MACRO_CONFIG2); 357 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 358 0, RGMII_IO_MACRO_CONFIG2); 359 /* Write 0x5 to PRG_RCLK_DLY_CODE */ 360 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 361 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 362 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 363 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 364 SDCC_HC_REG_DDR_CONFIG); 365 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 366 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 367 SDCC_HC_REG_DDR_CONFIG); 368 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 369 RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG); 370 break; 371 default: 372 dev_err(ðqos->pdev->dev, 373 "Invalid speed %d\n", ethqos->speed); 374 return -EINVAL; 375 } 376 377 return 0; 378 } 379 380 static int ethqos_configure(struct qcom_ethqos *ethqos) 381 { 382 volatile unsigned int dll_lock; 383 unsigned int i, retry = 1000; 384 385 /* Reset to POR values and enable clk */ 386 for (i = 0; i < ethqos->num_por; i++) 387 rgmii_writel(ethqos, ethqos->por[i].value, 388 ethqos->por[i].offset); 389 ethqos_set_func_clk_en(ethqos); 390 391 /* Initialize the DLL first */ 392 393 /* Set DLL_RST */ 394 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 395 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 396 397 /* Set PDN */ 398 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 399 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 400 401 /* Clear DLL_RST */ 402 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 403 SDCC_HC_REG_DLL_CONFIG); 404 405 /* Clear PDN */ 406 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 407 SDCC_HC_REG_DLL_CONFIG); 408 409 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 410 /* Set DLL_EN */ 411 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 412 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 413 414 /* Set CK_OUT_EN */ 415 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 416 SDCC_DLL_CONFIG_CK_OUT_EN, 417 SDCC_HC_REG_DLL_CONFIG); 418 419 /* Set USR_CTL bit 26 with mask of 3 bits */ 420 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); 421 422 /* wait for DLL LOCK */ 423 do { 424 mdelay(1); 425 dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 426 if (dll_lock & SDC4_STATUS_DLL_LOCK) 427 break; 428 retry--; 429 } while (retry > 0); 430 if (!retry) 431 dev_err(ðqos->pdev->dev, 432 "Timeout while waiting for DLL lock\n"); 433 } 434 435 if (ethqos->speed == SPEED_1000) 436 ethqos_dll_configure(ethqos); 437 438 ethqos_rgmii_macro_init(ethqos); 439 440 return 0; 441 } 442 443 static void ethqos_fix_mac_speed(void *priv, unsigned int speed) 444 { 445 struct qcom_ethqos *ethqos = priv; 446 447 ethqos->speed = speed; 448 ethqos_update_rgmii_clk(ethqos, speed); 449 ethqos_configure(ethqos); 450 } 451 452 static int ethqos_clks_config(void *priv, bool enabled) 453 { 454 struct qcom_ethqos *ethqos = priv; 455 int ret = 0; 456 457 if (enabled) { 458 ret = clk_prepare_enable(ethqos->rgmii_clk); 459 if (ret) { 460 dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); 461 return ret; 462 } 463 } else { 464 clk_disable_unprepare(ethqos->rgmii_clk); 465 } 466 467 return ret; 468 } 469 470 static int qcom_ethqos_probe(struct platform_device *pdev) 471 { 472 struct device_node *np = pdev->dev.of_node; 473 struct plat_stmmacenet_data *plat_dat; 474 struct stmmac_resources stmmac_res; 475 const struct ethqos_emac_driver_data *data; 476 struct qcom_ethqos *ethqos; 477 int ret; 478 479 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 480 if (ret) 481 return ret; 482 483 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 484 if (IS_ERR(plat_dat)) { 485 dev_err(&pdev->dev, "dt configuration failed\n"); 486 return PTR_ERR(plat_dat); 487 } 488 489 plat_dat->clks_config = ethqos_clks_config; 490 491 ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL); 492 if (!ethqos) { 493 ret = -ENOMEM; 494 goto err_mem; 495 } 496 497 ethqos->pdev = pdev; 498 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 499 if (IS_ERR(ethqos->rgmii_base)) { 500 ret = PTR_ERR(ethqos->rgmii_base); 501 goto err_mem; 502 } 503 504 data = of_device_get_match_data(&pdev->dev); 505 ethqos->por = data->por; 506 ethqos->num_por = data->num_por; 507 508 ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii"); 509 if (IS_ERR(ethqos->rgmii_clk)) { 510 ret = PTR_ERR(ethqos->rgmii_clk); 511 goto err_mem; 512 } 513 514 ret = ethqos_clks_config(ethqos, true); 515 if (ret) 516 goto err_mem; 517 518 ethqos->speed = SPEED_1000; 519 ethqos_update_rgmii_clk(ethqos, SPEED_1000); 520 ethqos_set_func_clk_en(ethqos); 521 522 plat_dat->bsp_priv = ethqos; 523 plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 524 plat_dat->dump_debug_regs = rgmii_dump; 525 plat_dat->has_gmac4 = 1; 526 plat_dat->pmt = 1; 527 plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); 528 529 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 530 if (ret) 531 goto err_clk; 532 533 return ret; 534 535 err_clk: 536 ethqos_clks_config(ethqos, false); 537 538 err_mem: 539 stmmac_remove_config_dt(pdev, plat_dat); 540 541 return ret; 542 } 543 544 static int qcom_ethqos_remove(struct platform_device *pdev) 545 { 546 struct qcom_ethqos *ethqos; 547 int ret; 548 549 ethqos = get_stmmac_bsp_priv(&pdev->dev); 550 if (!ethqos) 551 return -ENODEV; 552 553 ret = stmmac_pltfr_remove(pdev); 554 ethqos_clks_config(ethqos, false); 555 556 return ret; 557 } 558 559 static const struct of_device_id qcom_ethqos_match[] = { 560 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 561 { } 562 }; 563 MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 564 565 static struct platform_driver qcom_ethqos_driver = { 566 .probe = qcom_ethqos_probe, 567 .remove = qcom_ethqos_remove, 568 .driver = { 569 .name = "qcom-ethqos", 570 .pm = &stmmac_pltfr_pm_ops, 571 .of_match_table = of_match_ptr(qcom_ethqos_match), 572 }, 573 }; 574 module_platform_driver(qcom_ethqos_driver); 575 576 MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 577 MODULE_LICENSE("GPL v2"); 578