1a7c30e62SVinod Koul // SPDX-License-Identifier: GPL-2.0 2a7c30e62SVinod Koul // Copyright (c) 2018-19, Linaro Limited 3a7c30e62SVinod Koul 4a7c30e62SVinod Koul #include <linux/module.h> 5a7c30e62SVinod Koul #include <linux/of.h> 6a7c30e62SVinod Koul #include <linux/of_device.h> 7a7c30e62SVinod Koul #include <linux/platform_device.h> 8a7c30e62SVinod Koul #include <linux/phy.h> 9*ee8daccaSBartosz Golaszewski #include <linux/property.h> 10a7c30e62SVinod Koul #include "stmmac.h" 11a7c30e62SVinod Koul #include "stmmac_platform.h" 12a7c30e62SVinod Koul 13a7c30e62SVinod Koul #define RGMII_IO_MACRO_CONFIG 0x0 14a7c30e62SVinod Koul #define SDCC_HC_REG_DLL_CONFIG 0x4 15b6837619SAndrew Halaney #define SDCC_TEST_CTL 0x8 16a7c30e62SVinod Koul #define SDCC_HC_REG_DDR_CONFIG 0xC 17a7c30e62SVinod Koul #define SDCC_HC_REG_DLL_CONFIG2 0x10 18a7c30e62SVinod Koul #define SDC4_STATUS 0x14 19a7c30e62SVinod Koul #define SDCC_USR_CTL 0x18 20a7c30e62SVinod Koul #define RGMII_IO_MACRO_CONFIG2 0x1C 21a7c30e62SVinod Koul #define RGMII_IO_MACRO_DEBUG1 0x20 22a7c30e62SVinod Koul #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 23a7c30e62SVinod Koul 24a7c30e62SVinod Koul /* RGMII_IO_MACRO_CONFIG fields */ 25a7c30e62SVinod Koul #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 26a7c30e62SVinod Koul #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 27a7c30e62SVinod Koul #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 28a7c30e62SVinod Koul #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 29a7c30e62SVinod Koul #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 30a7c30e62SVinod Koul #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 31a7c30e62SVinod Koul #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 32a7c30e62SVinod Koul #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 33a7c30e62SVinod Koul #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 34a7c30e62SVinod Koul #define RGMII_CONFIG_PROG_SWAP BIT(1) 35a7c30e62SVinod Koul #define RGMII_CONFIG_DDR_MODE BIT(0) 36a7c30e62SVinod Koul 37a7c30e62SVinod Koul /* SDCC_HC_REG_DLL_CONFIG fields */ 38a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 39a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_PDN BIT(29) 40a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 41a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 42a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 43a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 44a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 45a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 46a7c30e62SVinod Koul #define SDCC_DLL_MCLK_GATING_EN BIT(5) 47a7c30e62SVinod Koul #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 48a7c30e62SVinod Koul 49a7c30e62SVinod Koul /* SDCC_HC_REG_DDR_CONFIG fields */ 50a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 51a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 52a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 53a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 54b6837619SAndrew Halaney #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 55a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 56a7c30e62SVinod Koul 57a7c30e62SVinod Koul /* SDCC_HC_REG_DLL_CONFIG2 fields */ 58a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 59a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 60a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 61a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 62a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 63a7c30e62SVinod Koul 64a7c30e62SVinod Koul /* SDC4_STATUS bits */ 65a7c30e62SVinod Koul #define SDC4_STATUS_DLL_LOCK BIT(7) 66a7c30e62SVinod Koul 67a7c30e62SVinod Koul /* RGMII_IO_MACRO_CONFIG2 fields */ 68a7c30e62SVinod Koul #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 69a7c30e62SVinod Koul #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 70a7c30e62SVinod Koul #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 71a7c30e62SVinod Koul #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 72a7c30e62SVinod Koul #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 73a7c30e62SVinod Koul #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 74a7c30e62SVinod Koul #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 75a7c30e62SVinod Koul 76a7c30e62SVinod Koul struct ethqos_emac_por { 77a7c30e62SVinod Koul unsigned int offset; 78a7c30e62SVinod Koul unsigned int value; 79a7c30e62SVinod Koul }; 80a7c30e62SVinod Koul 81fd4a5177SVinod Koul struct ethqos_emac_driver_data { 82fd4a5177SVinod Koul const struct ethqos_emac_por *por; 83fd4a5177SVinod Koul unsigned int num_por; 84030f1d59SAndrew Halaney bool rgmii_config_loopback_en; 85b6837619SAndrew Halaney bool has_emac3; 86b6837619SAndrew Halaney struct dwmac4_addrs dwmac4_addrs; 87fd4a5177SVinod Koul }; 88fd4a5177SVinod Koul 89a7c30e62SVinod Koul struct qcom_ethqos { 90a7c30e62SVinod Koul struct platform_device *pdev; 91a7c30e62SVinod Koul void __iomem *rgmii_base; 92a7c30e62SVinod Koul 93a7c30e62SVinod Koul unsigned int rgmii_clk_rate; 94a7c30e62SVinod Koul struct clk *rgmii_clk; 95a7c30e62SVinod Koul unsigned int speed; 96a7c30e62SVinod Koul 97a7c30e62SVinod Koul const struct ethqos_emac_por *por; 98a7c30e62SVinod Koul unsigned int num_por; 99030f1d59SAndrew Halaney bool rgmii_config_loopback_en; 100b6837619SAndrew Halaney bool has_emac3; 101a7c30e62SVinod Koul }; 102a7c30e62SVinod Koul 103a7c30e62SVinod Koul static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 104a7c30e62SVinod Koul { 105a7c30e62SVinod Koul return readl(ethqos->rgmii_base + offset); 106a7c30e62SVinod Koul } 107a7c30e62SVinod Koul 108a7c30e62SVinod Koul static void rgmii_writel(struct qcom_ethqos *ethqos, 109a7c30e62SVinod Koul int value, unsigned int offset) 110a7c30e62SVinod Koul { 111a7c30e62SVinod Koul writel(value, ethqos->rgmii_base + offset); 112a7c30e62SVinod Koul } 113a7c30e62SVinod Koul 114a7c30e62SVinod Koul static void rgmii_updatel(struct qcom_ethqos *ethqos, 115a7c30e62SVinod Koul int mask, int val, unsigned int offset) 116a7c30e62SVinod Koul { 117a7c30e62SVinod Koul unsigned int temp; 118a7c30e62SVinod Koul 119a7c30e62SVinod Koul temp = rgmii_readl(ethqos, offset); 120a7c30e62SVinod Koul temp = (temp & ~(mask)) | val; 121a7c30e62SVinod Koul rgmii_writel(ethqos, temp, offset); 122a7c30e62SVinod Koul } 123a7c30e62SVinod Koul 1244047b9dbSBhupesh Sharma static void rgmii_dump(void *priv) 125a7c30e62SVinod Koul { 1264047b9dbSBhupesh Sharma struct qcom_ethqos *ethqos = priv; 127302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 1284047b9dbSBhupesh Sharma 129302555a0SBartosz Golaszewski dev_dbg(dev, "Rgmii register dump\n"); 130302555a0SBartosz Golaszewski dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 131a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 132302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 133a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 134302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 135a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 136302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 137a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 138302555a0SBartosz Golaszewski dev_dbg(dev, "SDC4_STATUS: %x\n", 139a7c30e62SVinod Koul rgmii_readl(ethqos, SDC4_STATUS)); 140302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_USR_CTL: %x\n", 141a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_USR_CTL)); 142302555a0SBartosz Golaszewski dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 143a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 144302555a0SBartosz Golaszewski dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 145a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 146302555a0SBartosz Golaszewski dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 147a7c30e62SVinod Koul rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 148a7c30e62SVinod Koul } 149a7c30e62SVinod Koul 150a7c30e62SVinod Koul /* Clock rates */ 151a7c30e62SVinod Koul #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 152a7c30e62SVinod Koul #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 153a7c30e62SVinod Koul #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 154a7c30e62SVinod Koul 155a7c30e62SVinod Koul static void 156a7c30e62SVinod Koul ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) 157a7c30e62SVinod Koul { 158a7c30e62SVinod Koul switch (speed) { 159a7c30e62SVinod Koul case SPEED_1000: 160a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; 161a7c30e62SVinod Koul break; 162a7c30e62SVinod Koul 163a7c30e62SVinod Koul case SPEED_100: 164a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 165a7c30e62SVinod Koul break; 166a7c30e62SVinod Koul 167a7c30e62SVinod Koul case SPEED_10: 168a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 169a7c30e62SVinod Koul break; 170a7c30e62SVinod Koul } 171a7c30e62SVinod Koul 172a7c30e62SVinod Koul clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); 173a7c30e62SVinod Koul } 174a7c30e62SVinod Koul 175a7c30e62SVinod Koul static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 176a7c30e62SVinod Koul { 177a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 178a7c30e62SVinod Koul RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 179a7c30e62SVinod Koul } 180a7c30e62SVinod Koul 181a7c30e62SVinod Koul static const struct ethqos_emac_por emac_v2_3_0_por[] = { 182a7c30e62SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 183a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 184a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 185a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 186a7c30e62SVinod Koul { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 187a7c30e62SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 188a7c30e62SVinod Koul }; 189a7c30e62SVinod Koul 190fd4a5177SVinod Koul static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 191fd4a5177SVinod Koul .por = emac_v2_3_0_por, 192fd4a5177SVinod Koul .num_por = ARRAY_SIZE(emac_v2_3_0_por), 193030f1d59SAndrew Halaney .rgmii_config_loopback_en = true, 194b6837619SAndrew Halaney .has_emac3 = false, 195fd4a5177SVinod Koul }; 196fd4a5177SVinod Koul 197d90b3120SVinod Koul static const struct ethqos_emac_por emac_v2_1_0_por[] = { 198d90b3120SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 199d90b3120SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 200d90b3120SVinod Koul { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 201d90b3120SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 202d90b3120SVinod Koul { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 203d90b3120SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 204d90b3120SVinod Koul }; 205d90b3120SVinod Koul 206d90b3120SVinod Koul static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 207d90b3120SVinod Koul .por = emac_v2_1_0_por, 208d90b3120SVinod Koul .num_por = ARRAY_SIZE(emac_v2_1_0_por), 209030f1d59SAndrew Halaney .rgmii_config_loopback_en = false, 210b6837619SAndrew Halaney .has_emac3 = false, 211b6837619SAndrew Halaney }; 212b6837619SAndrew Halaney 213b6837619SAndrew Halaney static const struct ethqos_emac_por emac_v3_0_0_por[] = { 214b6837619SAndrew Halaney { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 215b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 216b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 217b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 218b6837619SAndrew Halaney { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 219b6837619SAndrew Halaney { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 220b6837619SAndrew Halaney }; 221b6837619SAndrew Halaney 222b6837619SAndrew Halaney static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 223b6837619SAndrew Halaney .por = emac_v3_0_0_por, 224b6837619SAndrew Halaney .num_por = ARRAY_SIZE(emac_v3_0_0_por), 225b6837619SAndrew Halaney .rgmii_config_loopback_en = false, 226b6837619SAndrew Halaney .has_emac3 = true, 227b6837619SAndrew Halaney .dwmac4_addrs = { 228b6837619SAndrew Halaney .dma_chan = 0x00008100, 229b6837619SAndrew Halaney .dma_chan_offset = 0x1000, 230b6837619SAndrew Halaney .mtl_chan = 0x00008000, 231b6837619SAndrew Halaney .mtl_chan_offset = 0x1000, 232b6837619SAndrew Halaney .mtl_ets_ctrl = 0x00008010, 233b6837619SAndrew Halaney .mtl_ets_ctrl_offset = 0x1000, 234b6837619SAndrew Halaney .mtl_txq_weight = 0x00008018, 235b6837619SAndrew Halaney .mtl_txq_weight_offset = 0x1000, 236b6837619SAndrew Halaney .mtl_send_slp_cred = 0x0000801c, 237b6837619SAndrew Halaney .mtl_send_slp_cred_offset = 0x1000, 238b6837619SAndrew Halaney .mtl_high_cred = 0x00008020, 239b6837619SAndrew Halaney .mtl_high_cred_offset = 0x1000, 240b6837619SAndrew Halaney .mtl_low_cred = 0x00008024, 241b6837619SAndrew Halaney .mtl_low_cred_offset = 0x1000, 242b6837619SAndrew Halaney }, 243d90b3120SVinod Koul }; 244d90b3120SVinod Koul 245a7c30e62SVinod Koul static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 246a7c30e62SVinod Koul { 247302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 248a7c30e62SVinod Koul unsigned int val; 249a7c30e62SVinod Koul int retry = 1000; 250a7c30e62SVinod Koul 251a7c30e62SVinod Koul /* Set CDR_EN */ 252a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 253a7c30e62SVinod Koul SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 254a7c30e62SVinod Koul 255a7c30e62SVinod Koul /* Set CDR_EXT_EN */ 256a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 257a7c30e62SVinod Koul SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 258a7c30e62SVinod Koul 259a7c30e62SVinod Koul /* Clear CK_OUT_EN */ 260a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 261a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 262a7c30e62SVinod Koul 263a7c30e62SVinod Koul /* Set DLL_EN */ 264a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 265a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 266a7c30e62SVinod Koul 267b6837619SAndrew Halaney if (!ethqos->has_emac3) { 268a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 269a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 270a7c30e62SVinod Koul 271a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 272a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 273b6837619SAndrew Halaney } 274a7c30e62SVinod Koul 275a7c30e62SVinod Koul /* Wait for CK_OUT_EN clear */ 276a7c30e62SVinod Koul do { 277a7c30e62SVinod Koul val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 278a7c30e62SVinod Koul val &= SDCC_DLL_CONFIG_CK_OUT_EN; 279a7c30e62SVinod Koul if (!val) 280a7c30e62SVinod Koul break; 281a7c30e62SVinod Koul mdelay(1); 282a7c30e62SVinod Koul retry--; 283a7c30e62SVinod Koul } while (retry > 0); 284a7c30e62SVinod Koul if (!retry) 285302555a0SBartosz Golaszewski dev_err(dev, "Clear CK_OUT_EN timedout\n"); 286a7c30e62SVinod Koul 287a7c30e62SVinod Koul /* Set CK_OUT_EN */ 288a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 289a7c30e62SVinod Koul SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 290a7c30e62SVinod Koul 291a7c30e62SVinod Koul /* Wait for CK_OUT_EN set */ 292a7c30e62SVinod Koul retry = 1000; 293a7c30e62SVinod Koul do { 294a7c30e62SVinod Koul val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 295a7c30e62SVinod Koul val &= SDCC_DLL_CONFIG_CK_OUT_EN; 296a7c30e62SVinod Koul if (val) 297a7c30e62SVinod Koul break; 298a7c30e62SVinod Koul mdelay(1); 299a7c30e62SVinod Koul retry--; 300a7c30e62SVinod Koul } while (retry > 0); 301a7c30e62SVinod Koul if (!retry) 302302555a0SBartosz Golaszewski dev_err(dev, "Set CK_OUT_EN timedout\n"); 303a7c30e62SVinod Koul 304a7c30e62SVinod Koul /* Set DDR_CAL_EN */ 305a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 306a7c30e62SVinod Koul SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 307a7c30e62SVinod Koul 308b6837619SAndrew Halaney if (!ethqos->has_emac3) { 309a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 310a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG2); 311a7c30e62SVinod Koul 312a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 313a7c30e62SVinod Koul 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 314a7c30e62SVinod Koul 315a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 316a7c30e62SVinod Koul BIT(2), SDCC_HC_REG_DLL_CONFIG2); 317a7c30e62SVinod Koul 318a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 319a7c30e62SVinod Koul SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 320a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG2); 321b6837619SAndrew Halaney } 322a7c30e62SVinod Koul 323a7c30e62SVinod Koul return 0; 324a7c30e62SVinod Koul } 325a7c30e62SVinod Koul 326a7c30e62SVinod Koul static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 327a7c30e62SVinod Koul { 328302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 329164a9ebeSAndrew Halaney int phase_shift; 330164a9ebeSAndrew Halaney int phy_mode; 331030f1d59SAndrew Halaney int loopback; 332164a9ebeSAndrew Halaney 333164a9ebeSAndrew Halaney /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 334302555a0SBartosz Golaszewski phy_mode = device_get_phy_mode(dev); 335164a9ebeSAndrew Halaney if (phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 336164a9ebeSAndrew Halaney phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 337164a9ebeSAndrew Halaney phase_shift = 0; 338164a9ebeSAndrew Halaney else 339164a9ebeSAndrew Halaney phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 340164a9ebeSAndrew Halaney 341a7c30e62SVinod Koul /* Disable loopback mode */ 342a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 343a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 344a7c30e62SVinod Koul 345030f1d59SAndrew Halaney /* Determine if this platform wants loopback enabled after programming */ 346030f1d59SAndrew Halaney if (ethqos->rgmii_config_loopback_en) 347030f1d59SAndrew Halaney loopback = RGMII_CONFIG_LOOPBACK_EN; 348030f1d59SAndrew Halaney else 349030f1d59SAndrew Halaney loopback = 0; 350030f1d59SAndrew Halaney 351a7c30e62SVinod Koul /* Select RGMII, write 0 to interface select */ 352a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 353a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 354a7c30e62SVinod Koul 355a7c30e62SVinod Koul switch (ethqos->speed) { 356a7c30e62SVinod Koul case SPEED_1000: 357a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 358a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 359a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 360a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 361a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 362a7c30e62SVinod Koul RGMII_CONFIG_POS_NEG_DATA_SEL, 363a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 364a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 365a7c30e62SVinod Koul RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 366a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 367a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 368164a9ebeSAndrew Halaney 369a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 370164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 371a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 372a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 373a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 374a7c30e62SVinod Koul RGMII_CONFIG2_RX_PROG_SWAP, 375a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG2); 376a7c30e62SVinod Koul 377b6837619SAndrew Halaney /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 378b6837619SAndrew Halaney * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 379b6837619SAndrew Halaney */ 380b6837619SAndrew Halaney if (ethqos->has_emac3) { 381b6837619SAndrew Halaney /* 0.9 ns */ 382b6837619SAndrew Halaney rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 383b6837619SAndrew Halaney 115, SDCC_HC_REG_DDR_CONFIG); 384b6837619SAndrew Halaney } else { 385b6837619SAndrew Halaney /* 1.8 ns */ 386a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 387a7c30e62SVinod Koul 57, SDCC_HC_REG_DDR_CONFIG); 388b6837619SAndrew Halaney } 389a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 390a7c30e62SVinod Koul SDCC_DDR_CONFIG_PRG_DLY_EN, 391a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 392a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 393030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 394a7c30e62SVinod Koul break; 395a7c30e62SVinod Koul 396a7c30e62SVinod Koul case SPEED_100: 397a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 398a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 399a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 400a7c30e62SVinod Koul RGMII_CONFIG_BYPASS_TX_ID_EN, 401a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 402a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 403a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 404a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 405a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 406a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 407a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 408a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 409164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 410a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 411a7c30e62SVinod Koul BIT(6), RGMII_IO_MACRO_CONFIG); 412a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 413a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 414b6837619SAndrew Halaney 415b6837619SAndrew Halaney if (ethqos->has_emac3) 416b6837619SAndrew Halaney rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 417b6837619SAndrew Halaney RGMII_CONFIG2_RX_PROG_SWAP, 418b6837619SAndrew Halaney RGMII_IO_MACRO_CONFIG2); 419b6837619SAndrew Halaney else 420a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 421a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 422b6837619SAndrew Halaney 423a7c30e62SVinod Koul /* Write 0x5 to PRG_RCLK_DLY_CODE */ 424a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 425a7c30e62SVinod Koul (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 426a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 427a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 428a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 429a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 430a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 431a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 432a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 433030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 434a7c30e62SVinod Koul break; 435a7c30e62SVinod Koul 436a7c30e62SVinod Koul case SPEED_10: 437a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 438a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 439a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 440a7c30e62SVinod Koul RGMII_CONFIG_BYPASS_TX_ID_EN, 441a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 442a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 443a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 444a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 445a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 446a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 447a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 448a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 449164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 450a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 451a7c30e62SVinod Koul BIT(12) | GENMASK(9, 8), 452a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 453a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 454a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 455b6837619SAndrew Halaney if (ethqos->has_emac3) 456b6837619SAndrew Halaney rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 457b6837619SAndrew Halaney RGMII_CONFIG2_RX_PROG_SWAP, 458b6837619SAndrew Halaney RGMII_IO_MACRO_CONFIG2); 459b6837619SAndrew Halaney else 460a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 461a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 462a7c30e62SVinod Koul /* Write 0x5 to PRG_RCLK_DLY_CODE */ 463a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 464a7c30e62SVinod Koul (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 465a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 466a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 467a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 468a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 469a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 470a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 471a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 472030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 473a7c30e62SVinod Koul break; 474a7c30e62SVinod Koul default: 475302555a0SBartosz Golaszewski dev_err(dev, "Invalid speed %d\n", ethqos->speed); 476a7c30e62SVinod Koul return -EINVAL; 477a7c30e62SVinod Koul } 478a7c30e62SVinod Koul 479a7c30e62SVinod Koul return 0; 480a7c30e62SVinod Koul } 481a7c30e62SVinod Koul 482a7c30e62SVinod Koul static int ethqos_configure(struct qcom_ethqos *ethqos) 483a7c30e62SVinod Koul { 484302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 485a7c30e62SVinod Koul volatile unsigned int dll_lock; 486a7c30e62SVinod Koul unsigned int i, retry = 1000; 487a7c30e62SVinod Koul 488a7c30e62SVinod Koul /* Reset to POR values and enable clk */ 489a7c30e62SVinod Koul for (i = 0; i < ethqos->num_por; i++) 490a7c30e62SVinod Koul rgmii_writel(ethqos, ethqos->por[i].value, 491a7c30e62SVinod Koul ethqos->por[i].offset); 492a7c30e62SVinod Koul ethqos_set_func_clk_en(ethqos); 493a7c30e62SVinod Koul 494a7c30e62SVinod Koul /* Initialize the DLL first */ 495a7c30e62SVinod Koul 496a7c30e62SVinod Koul /* Set DLL_RST */ 497a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 498a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 499a7c30e62SVinod Koul 500a7c30e62SVinod Koul /* Set PDN */ 501a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 502a7c30e62SVinod Koul SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 503a7c30e62SVinod Koul 504b6837619SAndrew Halaney if (ethqos->has_emac3) { 505b6837619SAndrew Halaney if (ethqos->speed == SPEED_1000) { 506b6837619SAndrew Halaney rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 507b6837619SAndrew Halaney rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 508b6837619SAndrew Halaney rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 509b6837619SAndrew Halaney } else { 510b6837619SAndrew Halaney rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 511b6837619SAndrew Halaney rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 512b6837619SAndrew Halaney } 513b6837619SAndrew Halaney } 514b6837619SAndrew Halaney 515a7c30e62SVinod Koul /* Clear DLL_RST */ 516a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 517a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 518a7c30e62SVinod Koul 519a7c30e62SVinod Koul /* Clear PDN */ 520a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 521a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 522a7c30e62SVinod Koul 523a7c30e62SVinod Koul if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 524a7c30e62SVinod Koul /* Set DLL_EN */ 525a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 526a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 527a7c30e62SVinod Koul 528a7c30e62SVinod Koul /* Set CK_OUT_EN */ 529a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 530a7c30e62SVinod Koul SDCC_DLL_CONFIG_CK_OUT_EN, 531a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 532a7c30e62SVinod Koul 533a7c30e62SVinod Koul /* Set USR_CTL bit 26 with mask of 3 bits */ 534b6837619SAndrew Halaney if (!ethqos->has_emac3) 535b6837619SAndrew Halaney rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 536b6837619SAndrew Halaney SDCC_USR_CTL); 537a7c30e62SVinod Koul 538a7c30e62SVinod Koul /* wait for DLL LOCK */ 539a7c30e62SVinod Koul do { 540a7c30e62SVinod Koul mdelay(1); 541a7c30e62SVinod Koul dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 542a7c30e62SVinod Koul if (dll_lock & SDC4_STATUS_DLL_LOCK) 543a7c30e62SVinod Koul break; 5447d10f077SDejin Zheng retry--; 545a7c30e62SVinod Koul } while (retry > 0); 546a7c30e62SVinod Koul if (!retry) 547302555a0SBartosz Golaszewski dev_err(dev, "Timeout while waiting for DLL lock\n"); 548a7c30e62SVinod Koul } 549a7c30e62SVinod Koul 550a7c30e62SVinod Koul if (ethqos->speed == SPEED_1000) 551a7c30e62SVinod Koul ethqos_dll_configure(ethqos); 552a7c30e62SVinod Koul 553a7c30e62SVinod Koul ethqos_rgmii_macro_init(ethqos); 554a7c30e62SVinod Koul 555a7c30e62SVinod Koul return 0; 556a7c30e62SVinod Koul } 557a7c30e62SVinod Koul 558a7c30e62SVinod Koul static void ethqos_fix_mac_speed(void *priv, unsigned int speed) 559a7c30e62SVinod Koul { 560a7c30e62SVinod Koul struct qcom_ethqos *ethqos = priv; 561a7c30e62SVinod Koul 562a7c30e62SVinod Koul ethqos->speed = speed; 563a7c30e62SVinod Koul ethqos_update_rgmii_clk(ethqos, speed); 564a7c30e62SVinod Koul ethqos_configure(ethqos); 565a7c30e62SVinod Koul } 566a7c30e62SVinod Koul 5676c950ca7SBhupesh Sharma static int ethqos_clks_config(void *priv, bool enabled) 5686c950ca7SBhupesh Sharma { 5696c950ca7SBhupesh Sharma struct qcom_ethqos *ethqos = priv; 5706c950ca7SBhupesh Sharma int ret = 0; 5716c950ca7SBhupesh Sharma 5726c950ca7SBhupesh Sharma if (enabled) { 5736c950ca7SBhupesh Sharma ret = clk_prepare_enable(ethqos->rgmii_clk); 5746c950ca7SBhupesh Sharma if (ret) { 5756c950ca7SBhupesh Sharma dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); 5766c950ca7SBhupesh Sharma return ret; 5776c950ca7SBhupesh Sharma } 578ffba2123SBjorn Andersson 579ffba2123SBjorn Andersson /* Enable functional clock to prevent DMA reset to timeout due 580ffba2123SBjorn Andersson * to lacking PHY clock after the hardware block has been power 581ffba2123SBjorn Andersson * cycled. The actual configuration will be adjusted once 582ffba2123SBjorn Andersson * ethqos_fix_mac_speed() is invoked. 583ffba2123SBjorn Andersson */ 584ffba2123SBjorn Andersson ethqos_set_func_clk_en(ethqos); 5856c950ca7SBhupesh Sharma } else { 5866c950ca7SBhupesh Sharma clk_disable_unprepare(ethqos->rgmii_clk); 5876c950ca7SBhupesh Sharma } 5886c950ca7SBhupesh Sharma 5896c950ca7SBhupesh Sharma return ret; 5906c950ca7SBhupesh Sharma } 5916c950ca7SBhupesh Sharma 5929fc68f23SBartosz Golaszewski static void ethqos_clks_disable(void *data) 5939fc68f23SBartosz Golaszewski { 5949fc68f23SBartosz Golaszewski ethqos_clks_config(data, false); 5959fc68f23SBartosz Golaszewski } 5969fc68f23SBartosz Golaszewski 597a7c30e62SVinod Koul static int qcom_ethqos_probe(struct platform_device *pdev) 598a7c30e62SVinod Koul { 599a7c30e62SVinod Koul struct device_node *np = pdev->dev.of_node; 6007b5e64a9SBartosz Golaszewski const struct ethqos_emac_driver_data *data; 601a7c30e62SVinod Koul struct plat_stmmacenet_data *plat_dat; 602a7c30e62SVinod Koul struct stmmac_resources stmmac_res; 603302555a0SBartosz Golaszewski struct device *dev = &pdev->dev; 604a7c30e62SVinod Koul struct qcom_ethqos *ethqos; 605a7c30e62SVinod Koul int ret; 606a7c30e62SVinod Koul 607a7c30e62SVinod Koul ret = stmmac_get_platform_resources(pdev, &stmmac_res); 608a7c30e62SVinod Koul if (ret) 609a7c30e62SVinod Koul return ret; 610a7c30e62SVinod Koul 61183216e39SMichael Walle plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 612a7c30e62SVinod Koul if (IS_ERR(plat_dat)) { 613302555a0SBartosz Golaszewski dev_err(dev, "dt configuration failed\n"); 614a7c30e62SVinod Koul return PTR_ERR(plat_dat); 615a7c30e62SVinod Koul } 616a7c30e62SVinod Koul 6176c950ca7SBhupesh Sharma plat_dat->clks_config = ethqos_clks_config; 6186c950ca7SBhupesh Sharma 619302555a0SBartosz Golaszewski ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 620a7c30e62SVinod Koul if (!ethqos) { 621a7c30e62SVinod Koul ret = -ENOMEM; 6229bc58060SBartosz Golaszewski goto out_config_dt; 623a7c30e62SVinod Koul } 624a7c30e62SVinod Koul 625a7c30e62SVinod Koul ethqos->pdev = pdev; 6263a5a32b5SYang Yingliang ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 627a7c30e62SVinod Koul if (IS_ERR(ethqos->rgmii_base)) { 628a7c30e62SVinod Koul ret = PTR_ERR(ethqos->rgmii_base); 6299bc58060SBartosz Golaszewski goto out_config_dt; 630a7c30e62SVinod Koul } 631a7c30e62SVinod Koul 632302555a0SBartosz Golaszewski data = of_device_get_match_data(dev); 633fd4a5177SVinod Koul ethqos->por = data->por; 634fd4a5177SVinod Koul ethqos->num_por = data->num_por; 635030f1d59SAndrew Halaney ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 636b6837619SAndrew Halaney ethqos->has_emac3 = data->has_emac3; 637a7c30e62SVinod Koul 638302555a0SBartosz Golaszewski ethqos->rgmii_clk = devm_clk_get(dev, "rgmii"); 6398f4ebaaaSWei Yongjun if (IS_ERR(ethqos->rgmii_clk)) { 6408f4ebaaaSWei Yongjun ret = PTR_ERR(ethqos->rgmii_clk); 6419bc58060SBartosz Golaszewski goto out_config_dt; 642a7c30e62SVinod Koul } 643a7c30e62SVinod Koul 6446c950ca7SBhupesh Sharma ret = ethqos_clks_config(ethqos, true); 645a7c30e62SVinod Koul if (ret) 6469bc58060SBartosz Golaszewski goto out_config_dt; 647a7c30e62SVinod Koul 648302555a0SBartosz Golaszewski ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 6499fc68f23SBartosz Golaszewski if (ret) 6509bc58060SBartosz Golaszewski goto out_config_dt; 6519fc68f23SBartosz Golaszewski 652a7c30e62SVinod Koul ethqos->speed = SPEED_1000; 653a7c30e62SVinod Koul ethqos_update_rgmii_clk(ethqos, SPEED_1000); 654a7c30e62SVinod Koul ethqos_set_func_clk_en(ethqos); 655a7c30e62SVinod Koul 656a7c30e62SVinod Koul plat_dat->bsp_priv = ethqos; 657a7c30e62SVinod Koul plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 6584047b9dbSBhupesh Sharma plat_dat->dump_debug_regs = rgmii_dump; 659a7c30e62SVinod Koul plat_dat->has_gmac4 = 1; 6609bc00973SBartosz Golaszewski if (ethqos->has_emac3) 661b6837619SAndrew Halaney plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 662a7c30e62SVinod Koul plat_dat->pmt = 1; 663a7c30e62SVinod Koul plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); 66454aa39a5SAndrey Konovalov if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 66554aa39a5SAndrey Konovalov plat_dat->rx_clk_runs_in_lpi = 1; 666a7c30e62SVinod Koul 667302555a0SBartosz Golaszewski ret = stmmac_dvr_probe(dev, plat_dat, &stmmac_res); 668a7c30e62SVinod Koul if (ret) 6699bc58060SBartosz Golaszewski goto out_config_dt; 670a7c30e62SVinod Koul 671a7c30e62SVinod Koul return ret; 672a7c30e62SVinod Koul 6739bc58060SBartosz Golaszewski out_config_dt: 674a7c30e62SVinod Koul stmmac_remove_config_dt(pdev, plat_dat); 675a7c30e62SVinod Koul 676a7c30e62SVinod Koul return ret; 677a7c30e62SVinod Koul } 678a7c30e62SVinod Koul 679a7c30e62SVinod Koul static const struct of_device_id qcom_ethqos_match[] = { 680fd4a5177SVinod Koul { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 681b6837619SAndrew Halaney { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 682d90b3120SVinod Koul { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 683a7c30e62SVinod Koul { } 684a7c30e62SVinod Koul }; 685a7c30e62SVinod Koul MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 686a7c30e62SVinod Koul 687a7c30e62SVinod Koul static struct platform_driver qcom_ethqos_driver = { 688a7c30e62SVinod Koul .probe = qcom_ethqos_probe, 6899fc68f23SBartosz Golaszewski .remove_new = stmmac_pltfr_remove, 690a7c30e62SVinod Koul .driver = { 691a7c30e62SVinod Koul .name = "qcom-ethqos", 692a7c30e62SVinod Koul .pm = &stmmac_pltfr_pm_ops, 693dc54e450SKrzysztof Kozlowski .of_match_table = qcom_ethqos_match, 694a7c30e62SVinod Koul }, 695a7c30e62SVinod Koul }; 696a7c30e62SVinod Koul module_platform_driver(qcom_ethqos_driver); 697a7c30e62SVinod Koul 698a7c30e62SVinod Koul MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 699a7c30e62SVinod Koul MODULE_LICENSE("GPL v2"); 700