1a7c30e62SVinod Koul // SPDX-License-Identifier: GPL-2.0 2a7c30e62SVinod Koul // Copyright (c) 2018-19, Linaro Limited 3a7c30e62SVinod Koul 4a7c30e62SVinod Koul #include <linux/module.h> 5a7c30e62SVinod Koul #include <linux/of.h> 6a7c30e62SVinod Koul #include <linux/of_device.h> 7a7c30e62SVinod Koul #include <linux/platform_device.h> 8a7c30e62SVinod Koul #include <linux/phy.h> 9a7c30e62SVinod Koul #include "stmmac.h" 10a7c30e62SVinod Koul #include "stmmac_platform.h" 11a7c30e62SVinod Koul 12a7c30e62SVinod Koul #define RGMII_IO_MACRO_CONFIG 0x0 13a7c30e62SVinod Koul #define SDCC_HC_REG_DLL_CONFIG 0x4 14b6837619SAndrew Halaney #define SDCC_TEST_CTL 0x8 15a7c30e62SVinod Koul #define SDCC_HC_REG_DDR_CONFIG 0xC 16a7c30e62SVinod Koul #define SDCC_HC_REG_DLL_CONFIG2 0x10 17a7c30e62SVinod Koul #define SDC4_STATUS 0x14 18a7c30e62SVinod Koul #define SDCC_USR_CTL 0x18 19a7c30e62SVinod Koul #define RGMII_IO_MACRO_CONFIG2 0x1C 20a7c30e62SVinod Koul #define RGMII_IO_MACRO_DEBUG1 0x20 21a7c30e62SVinod Koul #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 22a7c30e62SVinod Koul 23a7c30e62SVinod Koul /* RGMII_IO_MACRO_CONFIG fields */ 24a7c30e62SVinod Koul #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 25a7c30e62SVinod Koul #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 26a7c30e62SVinod Koul #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 27a7c30e62SVinod Koul #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 28a7c30e62SVinod Koul #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 29a7c30e62SVinod Koul #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 30a7c30e62SVinod Koul #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 31a7c30e62SVinod Koul #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 32a7c30e62SVinod Koul #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 33a7c30e62SVinod Koul #define RGMII_CONFIG_PROG_SWAP BIT(1) 34a7c30e62SVinod Koul #define RGMII_CONFIG_DDR_MODE BIT(0) 35a7c30e62SVinod Koul 36a7c30e62SVinod Koul /* SDCC_HC_REG_DLL_CONFIG fields */ 37a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 38a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_PDN BIT(29) 39a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 40a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 41a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 42a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 43a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 44a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 45a7c30e62SVinod Koul #define SDCC_DLL_MCLK_GATING_EN BIT(5) 46a7c30e62SVinod Koul #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 47a7c30e62SVinod Koul 48a7c30e62SVinod Koul /* SDCC_HC_REG_DDR_CONFIG fields */ 49a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 50a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 51a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 52a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 53b6837619SAndrew Halaney #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 54a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 55a7c30e62SVinod Koul 56a7c30e62SVinod Koul /* SDCC_HC_REG_DLL_CONFIG2 fields */ 57a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 58a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 59a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 60a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 61a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 62a7c30e62SVinod Koul 63a7c30e62SVinod Koul /* SDC4_STATUS bits */ 64a7c30e62SVinod Koul #define SDC4_STATUS_DLL_LOCK BIT(7) 65a7c30e62SVinod Koul 66a7c30e62SVinod Koul /* RGMII_IO_MACRO_CONFIG2 fields */ 67a7c30e62SVinod Koul #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 68a7c30e62SVinod Koul #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 69a7c30e62SVinod Koul #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 70a7c30e62SVinod Koul #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 71a7c30e62SVinod Koul #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 72a7c30e62SVinod Koul #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 73a7c30e62SVinod Koul #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 74a7c30e62SVinod Koul 75a7c30e62SVinod Koul struct ethqos_emac_por { 76a7c30e62SVinod Koul unsigned int offset; 77a7c30e62SVinod Koul unsigned int value; 78a7c30e62SVinod Koul }; 79a7c30e62SVinod Koul 80fd4a5177SVinod Koul struct ethqos_emac_driver_data { 81fd4a5177SVinod Koul const struct ethqos_emac_por *por; 82fd4a5177SVinod Koul unsigned int num_por; 83030f1d59SAndrew Halaney bool rgmii_config_loopback_en; 84b6837619SAndrew Halaney bool has_emac3; 85b6837619SAndrew Halaney struct dwmac4_addrs dwmac4_addrs; 86fd4a5177SVinod Koul }; 87fd4a5177SVinod Koul 88a7c30e62SVinod Koul struct qcom_ethqos { 89a7c30e62SVinod Koul struct platform_device *pdev; 90a7c30e62SVinod Koul void __iomem *rgmii_base; 91a7c30e62SVinod Koul 92a7c30e62SVinod Koul unsigned int rgmii_clk_rate; 93a7c30e62SVinod Koul struct clk *rgmii_clk; 94a7c30e62SVinod Koul unsigned int speed; 95a7c30e62SVinod Koul 96a7c30e62SVinod Koul const struct ethqos_emac_por *por; 97a7c30e62SVinod Koul unsigned int num_por; 98030f1d59SAndrew Halaney bool rgmii_config_loopback_en; 99b6837619SAndrew Halaney bool has_emac3; 100a7c30e62SVinod Koul }; 101a7c30e62SVinod Koul 102a7c30e62SVinod Koul static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 103a7c30e62SVinod Koul { 104a7c30e62SVinod Koul return readl(ethqos->rgmii_base + offset); 105a7c30e62SVinod Koul } 106a7c30e62SVinod Koul 107a7c30e62SVinod Koul static void rgmii_writel(struct qcom_ethqos *ethqos, 108a7c30e62SVinod Koul int value, unsigned int offset) 109a7c30e62SVinod Koul { 110a7c30e62SVinod Koul writel(value, ethqos->rgmii_base + offset); 111a7c30e62SVinod Koul } 112a7c30e62SVinod Koul 113a7c30e62SVinod Koul static void rgmii_updatel(struct qcom_ethqos *ethqos, 114a7c30e62SVinod Koul int mask, int val, unsigned int offset) 115a7c30e62SVinod Koul { 116a7c30e62SVinod Koul unsigned int temp; 117a7c30e62SVinod Koul 118a7c30e62SVinod Koul temp = rgmii_readl(ethqos, offset); 119a7c30e62SVinod Koul temp = (temp & ~(mask)) | val; 120a7c30e62SVinod Koul rgmii_writel(ethqos, temp, offset); 121a7c30e62SVinod Koul } 122a7c30e62SVinod Koul 1234047b9dbSBhupesh Sharma static void rgmii_dump(void *priv) 124a7c30e62SVinod Koul { 1254047b9dbSBhupesh Sharma struct qcom_ethqos *ethqos = priv; 1264047b9dbSBhupesh Sharma 127a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n"); 128a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n", 129a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 130a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 131a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 132a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 133a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 134a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 135a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 136a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n", 137a7c30e62SVinod Koul rgmii_readl(ethqos, SDC4_STATUS)); 138a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n", 139a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_USR_CTL)); 140a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 141a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 142a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 143a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 144a7c30e62SVinod Koul dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 145a7c30e62SVinod Koul rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 146a7c30e62SVinod Koul } 147a7c30e62SVinod Koul 148a7c30e62SVinod Koul /* Clock rates */ 149a7c30e62SVinod Koul #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 150a7c30e62SVinod Koul #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 151a7c30e62SVinod Koul #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 152a7c30e62SVinod Koul 153a7c30e62SVinod Koul static void 154a7c30e62SVinod Koul ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) 155a7c30e62SVinod Koul { 156a7c30e62SVinod Koul switch (speed) { 157a7c30e62SVinod Koul case SPEED_1000: 158a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; 159a7c30e62SVinod Koul break; 160a7c30e62SVinod Koul 161a7c30e62SVinod Koul case SPEED_100: 162a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 163a7c30e62SVinod Koul break; 164a7c30e62SVinod Koul 165a7c30e62SVinod Koul case SPEED_10: 166a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 167a7c30e62SVinod Koul break; 168a7c30e62SVinod Koul } 169a7c30e62SVinod Koul 170a7c30e62SVinod Koul clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); 171a7c30e62SVinod Koul } 172a7c30e62SVinod Koul 173a7c30e62SVinod Koul static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 174a7c30e62SVinod Koul { 175a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 176a7c30e62SVinod Koul RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 177a7c30e62SVinod Koul } 178a7c30e62SVinod Koul 179a7c30e62SVinod Koul static const struct ethqos_emac_por emac_v2_3_0_por[] = { 180a7c30e62SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 181a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 182a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 183a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 184a7c30e62SVinod Koul { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 185a7c30e62SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 186a7c30e62SVinod Koul }; 187a7c30e62SVinod Koul 188fd4a5177SVinod Koul static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 189fd4a5177SVinod Koul .por = emac_v2_3_0_por, 190fd4a5177SVinod Koul .num_por = ARRAY_SIZE(emac_v2_3_0_por), 191030f1d59SAndrew Halaney .rgmii_config_loopback_en = true, 192b6837619SAndrew Halaney .has_emac3 = false, 193fd4a5177SVinod Koul }; 194fd4a5177SVinod Koul 195d90b3120SVinod Koul static const struct ethqos_emac_por emac_v2_1_0_por[] = { 196d90b3120SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 197d90b3120SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 198d90b3120SVinod Koul { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 199d90b3120SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 200d90b3120SVinod Koul { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 201d90b3120SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 202d90b3120SVinod Koul }; 203d90b3120SVinod Koul 204d90b3120SVinod Koul static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 205d90b3120SVinod Koul .por = emac_v2_1_0_por, 206d90b3120SVinod Koul .num_por = ARRAY_SIZE(emac_v2_1_0_por), 207030f1d59SAndrew Halaney .rgmii_config_loopback_en = false, 208b6837619SAndrew Halaney .has_emac3 = false, 209b6837619SAndrew Halaney }; 210b6837619SAndrew Halaney 211b6837619SAndrew Halaney static const struct ethqos_emac_por emac_v3_0_0_por[] = { 212b6837619SAndrew Halaney { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 213b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 214b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 215b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 216b6837619SAndrew Halaney { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 217b6837619SAndrew Halaney { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 218b6837619SAndrew Halaney }; 219b6837619SAndrew Halaney 220b6837619SAndrew Halaney static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 221b6837619SAndrew Halaney .por = emac_v3_0_0_por, 222b6837619SAndrew Halaney .num_por = ARRAY_SIZE(emac_v3_0_0_por), 223b6837619SAndrew Halaney .rgmii_config_loopback_en = false, 224b6837619SAndrew Halaney .has_emac3 = true, 225b6837619SAndrew Halaney .dwmac4_addrs = { 226b6837619SAndrew Halaney .dma_chan = 0x00008100, 227b6837619SAndrew Halaney .dma_chan_offset = 0x1000, 228b6837619SAndrew Halaney .mtl_chan = 0x00008000, 229b6837619SAndrew Halaney .mtl_chan_offset = 0x1000, 230b6837619SAndrew Halaney .mtl_ets_ctrl = 0x00008010, 231b6837619SAndrew Halaney .mtl_ets_ctrl_offset = 0x1000, 232b6837619SAndrew Halaney .mtl_txq_weight = 0x00008018, 233b6837619SAndrew Halaney .mtl_txq_weight_offset = 0x1000, 234b6837619SAndrew Halaney .mtl_send_slp_cred = 0x0000801c, 235b6837619SAndrew Halaney .mtl_send_slp_cred_offset = 0x1000, 236b6837619SAndrew Halaney .mtl_high_cred = 0x00008020, 237b6837619SAndrew Halaney .mtl_high_cred_offset = 0x1000, 238b6837619SAndrew Halaney .mtl_low_cred = 0x00008024, 239b6837619SAndrew Halaney .mtl_low_cred_offset = 0x1000, 240b6837619SAndrew Halaney }, 241d90b3120SVinod Koul }; 242d90b3120SVinod Koul 243a7c30e62SVinod Koul static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 244a7c30e62SVinod Koul { 245a7c30e62SVinod Koul unsigned int val; 246a7c30e62SVinod Koul int retry = 1000; 247a7c30e62SVinod Koul 248a7c30e62SVinod Koul /* Set CDR_EN */ 249a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 250a7c30e62SVinod Koul SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 251a7c30e62SVinod Koul 252a7c30e62SVinod Koul /* Set CDR_EXT_EN */ 253a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 254a7c30e62SVinod Koul SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 255a7c30e62SVinod Koul 256a7c30e62SVinod Koul /* Clear CK_OUT_EN */ 257a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 258a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 259a7c30e62SVinod Koul 260a7c30e62SVinod Koul /* Set DLL_EN */ 261a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 262a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 263a7c30e62SVinod Koul 264b6837619SAndrew Halaney if (!ethqos->has_emac3) { 265a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 266a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 267a7c30e62SVinod Koul 268a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 269a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 270b6837619SAndrew Halaney } 271a7c30e62SVinod Koul 272a7c30e62SVinod Koul /* Wait for CK_OUT_EN clear */ 273a7c30e62SVinod Koul do { 274a7c30e62SVinod Koul val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 275a7c30e62SVinod Koul val &= SDCC_DLL_CONFIG_CK_OUT_EN; 276a7c30e62SVinod Koul if (!val) 277a7c30e62SVinod Koul break; 278a7c30e62SVinod Koul mdelay(1); 279a7c30e62SVinod Koul retry--; 280a7c30e62SVinod Koul } while (retry > 0); 281a7c30e62SVinod Koul if (!retry) 282a7c30e62SVinod Koul dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n"); 283a7c30e62SVinod Koul 284a7c30e62SVinod Koul /* Set CK_OUT_EN */ 285a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 286a7c30e62SVinod Koul SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 287a7c30e62SVinod Koul 288a7c30e62SVinod Koul /* Wait for CK_OUT_EN set */ 289a7c30e62SVinod Koul retry = 1000; 290a7c30e62SVinod Koul do { 291a7c30e62SVinod Koul val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 292a7c30e62SVinod Koul val &= SDCC_DLL_CONFIG_CK_OUT_EN; 293a7c30e62SVinod Koul if (val) 294a7c30e62SVinod Koul break; 295a7c30e62SVinod Koul mdelay(1); 296a7c30e62SVinod Koul retry--; 297a7c30e62SVinod Koul } while (retry > 0); 298a7c30e62SVinod Koul if (!retry) 299a7c30e62SVinod Koul dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n"); 300a7c30e62SVinod Koul 301a7c30e62SVinod Koul /* Set DDR_CAL_EN */ 302a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 303a7c30e62SVinod Koul SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 304a7c30e62SVinod Koul 305b6837619SAndrew Halaney if (!ethqos->has_emac3) { 306a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 307a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG2); 308a7c30e62SVinod Koul 309a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 310a7c30e62SVinod Koul 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 311a7c30e62SVinod Koul 312a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 313a7c30e62SVinod Koul BIT(2), SDCC_HC_REG_DLL_CONFIG2); 314a7c30e62SVinod Koul 315a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 316a7c30e62SVinod Koul SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 317a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG2); 318b6837619SAndrew Halaney } 319a7c30e62SVinod Koul 320a7c30e62SVinod Koul return 0; 321a7c30e62SVinod Koul } 322a7c30e62SVinod Koul 323a7c30e62SVinod Koul static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 324a7c30e62SVinod Koul { 325164a9ebeSAndrew Halaney int phase_shift; 326164a9ebeSAndrew Halaney int phy_mode; 327030f1d59SAndrew Halaney int loopback; 328164a9ebeSAndrew Halaney 329164a9ebeSAndrew Halaney /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 330164a9ebeSAndrew Halaney phy_mode = device_get_phy_mode(ðqos->pdev->dev); 331164a9ebeSAndrew Halaney if (phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 332164a9ebeSAndrew Halaney phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 333164a9ebeSAndrew Halaney phase_shift = 0; 334164a9ebeSAndrew Halaney else 335164a9ebeSAndrew Halaney phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 336164a9ebeSAndrew Halaney 337a7c30e62SVinod Koul /* Disable loopback mode */ 338a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 339a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 340a7c30e62SVinod Koul 341030f1d59SAndrew Halaney /* Determine if this platform wants loopback enabled after programming */ 342030f1d59SAndrew Halaney if (ethqos->rgmii_config_loopback_en) 343030f1d59SAndrew Halaney loopback = RGMII_CONFIG_LOOPBACK_EN; 344030f1d59SAndrew Halaney else 345030f1d59SAndrew Halaney loopback = 0; 346030f1d59SAndrew Halaney 347a7c30e62SVinod Koul /* Select RGMII, write 0 to interface select */ 348a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 349a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 350a7c30e62SVinod Koul 351a7c30e62SVinod Koul switch (ethqos->speed) { 352a7c30e62SVinod Koul case SPEED_1000: 353a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 354a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 355a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 356a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 357a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 358a7c30e62SVinod Koul RGMII_CONFIG_POS_NEG_DATA_SEL, 359a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 360a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 361a7c30e62SVinod Koul RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 362a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 363a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 364164a9ebeSAndrew Halaney 365a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 366164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 367a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 368a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 369a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 370a7c30e62SVinod Koul RGMII_CONFIG2_RX_PROG_SWAP, 371a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG2); 372a7c30e62SVinod Koul 373b6837619SAndrew Halaney /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 374b6837619SAndrew Halaney * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 375b6837619SAndrew Halaney */ 376b6837619SAndrew Halaney if (ethqos->has_emac3) { 377b6837619SAndrew Halaney /* 0.9 ns */ 378b6837619SAndrew Halaney rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 379b6837619SAndrew Halaney 115, SDCC_HC_REG_DDR_CONFIG); 380b6837619SAndrew Halaney } else { 381b6837619SAndrew Halaney /* 1.8 ns */ 382a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 383a7c30e62SVinod Koul 57, SDCC_HC_REG_DDR_CONFIG); 384b6837619SAndrew Halaney } 385a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 386a7c30e62SVinod Koul SDCC_DDR_CONFIG_PRG_DLY_EN, 387a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 388a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 389030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 390a7c30e62SVinod Koul break; 391a7c30e62SVinod Koul 392a7c30e62SVinod Koul case SPEED_100: 393a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 394a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 395a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 396a7c30e62SVinod Koul RGMII_CONFIG_BYPASS_TX_ID_EN, 397a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 398a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 399a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 400a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 401a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 402a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 403a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 404a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 405164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 406a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 407a7c30e62SVinod Koul BIT(6), RGMII_IO_MACRO_CONFIG); 408a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 409a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 410b6837619SAndrew Halaney 411b6837619SAndrew Halaney if (ethqos->has_emac3) 412b6837619SAndrew Halaney rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 413b6837619SAndrew Halaney RGMII_CONFIG2_RX_PROG_SWAP, 414b6837619SAndrew Halaney RGMII_IO_MACRO_CONFIG2); 415b6837619SAndrew Halaney else 416a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 417a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 418b6837619SAndrew Halaney 419a7c30e62SVinod Koul /* Write 0x5 to PRG_RCLK_DLY_CODE */ 420a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 421a7c30e62SVinod Koul (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 422a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 423a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 424a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 425a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 426a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 427a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 428a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 429030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 430a7c30e62SVinod Koul break; 431a7c30e62SVinod Koul 432a7c30e62SVinod Koul case SPEED_10: 433a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 434a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 435a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 436a7c30e62SVinod Koul RGMII_CONFIG_BYPASS_TX_ID_EN, 437a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 438a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 439a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 440a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 441a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 442a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 443a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 444a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 445164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 446a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 447a7c30e62SVinod Koul BIT(12) | GENMASK(9, 8), 448a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 449a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 450a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 451b6837619SAndrew Halaney if (ethqos->has_emac3) 452b6837619SAndrew Halaney rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 453b6837619SAndrew Halaney RGMII_CONFIG2_RX_PROG_SWAP, 454b6837619SAndrew Halaney RGMII_IO_MACRO_CONFIG2); 455b6837619SAndrew Halaney else 456a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 457a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 458a7c30e62SVinod Koul /* Write 0x5 to PRG_RCLK_DLY_CODE */ 459a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 460a7c30e62SVinod Koul (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 461a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 462a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 463a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 464a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 465a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 466a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 467a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 468030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 469a7c30e62SVinod Koul break; 470a7c30e62SVinod Koul default: 471a7c30e62SVinod Koul dev_err(ðqos->pdev->dev, 472a7c30e62SVinod Koul "Invalid speed %d\n", ethqos->speed); 473a7c30e62SVinod Koul return -EINVAL; 474a7c30e62SVinod Koul } 475a7c30e62SVinod Koul 476a7c30e62SVinod Koul return 0; 477a7c30e62SVinod Koul } 478a7c30e62SVinod Koul 479a7c30e62SVinod Koul static int ethqos_configure(struct qcom_ethqos *ethqos) 480a7c30e62SVinod Koul { 481a7c30e62SVinod Koul volatile unsigned int dll_lock; 482a7c30e62SVinod Koul unsigned int i, retry = 1000; 483a7c30e62SVinod Koul 484a7c30e62SVinod Koul /* Reset to POR values and enable clk */ 485a7c30e62SVinod Koul for (i = 0; i < ethqos->num_por; i++) 486a7c30e62SVinod Koul rgmii_writel(ethqos, ethqos->por[i].value, 487a7c30e62SVinod Koul ethqos->por[i].offset); 488a7c30e62SVinod Koul ethqos_set_func_clk_en(ethqos); 489a7c30e62SVinod Koul 490a7c30e62SVinod Koul /* Initialize the DLL first */ 491a7c30e62SVinod Koul 492a7c30e62SVinod Koul /* Set DLL_RST */ 493a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 494a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 495a7c30e62SVinod Koul 496a7c30e62SVinod Koul /* Set PDN */ 497a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 498a7c30e62SVinod Koul SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 499a7c30e62SVinod Koul 500b6837619SAndrew Halaney if (ethqos->has_emac3) { 501b6837619SAndrew Halaney if (ethqos->speed == SPEED_1000) { 502b6837619SAndrew Halaney rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 503b6837619SAndrew Halaney rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 504b6837619SAndrew Halaney rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 505b6837619SAndrew Halaney } else { 506b6837619SAndrew Halaney rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 507b6837619SAndrew Halaney rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 508b6837619SAndrew Halaney } 509b6837619SAndrew Halaney } 510b6837619SAndrew Halaney 511a7c30e62SVinod Koul /* Clear DLL_RST */ 512a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 513a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 514a7c30e62SVinod Koul 515a7c30e62SVinod Koul /* Clear PDN */ 516a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 517a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 518a7c30e62SVinod Koul 519a7c30e62SVinod Koul if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 520a7c30e62SVinod Koul /* Set DLL_EN */ 521a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 522a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 523a7c30e62SVinod Koul 524a7c30e62SVinod Koul /* Set CK_OUT_EN */ 525a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 526a7c30e62SVinod Koul SDCC_DLL_CONFIG_CK_OUT_EN, 527a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 528a7c30e62SVinod Koul 529a7c30e62SVinod Koul /* Set USR_CTL bit 26 with mask of 3 bits */ 530b6837619SAndrew Halaney if (!ethqos->has_emac3) 531b6837619SAndrew Halaney rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 532b6837619SAndrew Halaney SDCC_USR_CTL); 533a7c30e62SVinod Koul 534a7c30e62SVinod Koul /* wait for DLL LOCK */ 535a7c30e62SVinod Koul do { 536a7c30e62SVinod Koul mdelay(1); 537a7c30e62SVinod Koul dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 538a7c30e62SVinod Koul if (dll_lock & SDC4_STATUS_DLL_LOCK) 539a7c30e62SVinod Koul break; 5407d10f077SDejin Zheng retry--; 541a7c30e62SVinod Koul } while (retry > 0); 542a7c30e62SVinod Koul if (!retry) 543a7c30e62SVinod Koul dev_err(ðqos->pdev->dev, 544a7c30e62SVinod Koul "Timeout while waiting for DLL lock\n"); 545a7c30e62SVinod Koul } 546a7c30e62SVinod Koul 547a7c30e62SVinod Koul if (ethqos->speed == SPEED_1000) 548a7c30e62SVinod Koul ethqos_dll_configure(ethqos); 549a7c30e62SVinod Koul 550a7c30e62SVinod Koul ethqos_rgmii_macro_init(ethqos); 551a7c30e62SVinod Koul 552a7c30e62SVinod Koul return 0; 553a7c30e62SVinod Koul } 554a7c30e62SVinod Koul 555a7c30e62SVinod Koul static void ethqos_fix_mac_speed(void *priv, unsigned int speed) 556a7c30e62SVinod Koul { 557a7c30e62SVinod Koul struct qcom_ethqos *ethqos = priv; 558a7c30e62SVinod Koul 559a7c30e62SVinod Koul ethqos->speed = speed; 560a7c30e62SVinod Koul ethqos_update_rgmii_clk(ethqos, speed); 561a7c30e62SVinod Koul ethqos_configure(ethqos); 562a7c30e62SVinod Koul } 563a7c30e62SVinod Koul 5646c950ca7SBhupesh Sharma static int ethqos_clks_config(void *priv, bool enabled) 5656c950ca7SBhupesh Sharma { 5666c950ca7SBhupesh Sharma struct qcom_ethqos *ethqos = priv; 5676c950ca7SBhupesh Sharma int ret = 0; 5686c950ca7SBhupesh Sharma 5696c950ca7SBhupesh Sharma if (enabled) { 5706c950ca7SBhupesh Sharma ret = clk_prepare_enable(ethqos->rgmii_clk); 5716c950ca7SBhupesh Sharma if (ret) { 5726c950ca7SBhupesh Sharma dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); 5736c950ca7SBhupesh Sharma return ret; 5746c950ca7SBhupesh Sharma } 575ffba2123SBjorn Andersson 576ffba2123SBjorn Andersson /* Enable functional clock to prevent DMA reset to timeout due 577ffba2123SBjorn Andersson * to lacking PHY clock after the hardware block has been power 578ffba2123SBjorn Andersson * cycled. The actual configuration will be adjusted once 579ffba2123SBjorn Andersson * ethqos_fix_mac_speed() is invoked. 580ffba2123SBjorn Andersson */ 581ffba2123SBjorn Andersson ethqos_set_func_clk_en(ethqos); 5826c950ca7SBhupesh Sharma } else { 5836c950ca7SBhupesh Sharma clk_disable_unprepare(ethqos->rgmii_clk); 5846c950ca7SBhupesh Sharma } 5856c950ca7SBhupesh Sharma 5866c950ca7SBhupesh Sharma return ret; 5876c950ca7SBhupesh Sharma } 5886c950ca7SBhupesh Sharma 589*9fc68f23SBartosz Golaszewski static void ethqos_clks_disable(void *data) 590*9fc68f23SBartosz Golaszewski { 591*9fc68f23SBartosz Golaszewski ethqos_clks_config(data, false); 592*9fc68f23SBartosz Golaszewski } 593*9fc68f23SBartosz Golaszewski 594a7c30e62SVinod Koul static int qcom_ethqos_probe(struct platform_device *pdev) 595a7c30e62SVinod Koul { 596a7c30e62SVinod Koul struct device_node *np = pdev->dev.of_node; 597a7c30e62SVinod Koul struct plat_stmmacenet_data *plat_dat; 598a7c30e62SVinod Koul struct stmmac_resources stmmac_res; 599fd4a5177SVinod Koul const struct ethqos_emac_driver_data *data; 600a7c30e62SVinod Koul struct qcom_ethqos *ethqos; 601a7c30e62SVinod Koul int ret; 602a7c30e62SVinod Koul 603a7c30e62SVinod Koul ret = stmmac_get_platform_resources(pdev, &stmmac_res); 604a7c30e62SVinod Koul if (ret) 605a7c30e62SVinod Koul return ret; 606a7c30e62SVinod Koul 60783216e39SMichael Walle plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 608a7c30e62SVinod Koul if (IS_ERR(plat_dat)) { 609a7c30e62SVinod Koul dev_err(&pdev->dev, "dt configuration failed\n"); 610a7c30e62SVinod Koul return PTR_ERR(plat_dat); 611a7c30e62SVinod Koul } 612a7c30e62SVinod Koul 6136c950ca7SBhupesh Sharma plat_dat->clks_config = ethqos_clks_config; 6146c950ca7SBhupesh Sharma 615a7c30e62SVinod Koul ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL); 616a7c30e62SVinod Koul if (!ethqos) { 617a7c30e62SVinod Koul ret = -ENOMEM; 618a7c30e62SVinod Koul goto err_mem; 619a7c30e62SVinod Koul } 620a7c30e62SVinod Koul 621a7c30e62SVinod Koul ethqos->pdev = pdev; 6223a5a32b5SYang Yingliang ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 623a7c30e62SVinod Koul if (IS_ERR(ethqos->rgmii_base)) { 624a7c30e62SVinod Koul ret = PTR_ERR(ethqos->rgmii_base); 625a7c30e62SVinod Koul goto err_mem; 626a7c30e62SVinod Koul } 627a7c30e62SVinod Koul 628fd4a5177SVinod Koul data = of_device_get_match_data(&pdev->dev); 629fd4a5177SVinod Koul ethqos->por = data->por; 630fd4a5177SVinod Koul ethqos->num_por = data->num_por; 631030f1d59SAndrew Halaney ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 632b6837619SAndrew Halaney ethqos->has_emac3 = data->has_emac3; 633a7c30e62SVinod Koul 634a7c30e62SVinod Koul ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii"); 6358f4ebaaaSWei Yongjun if (IS_ERR(ethqos->rgmii_clk)) { 6368f4ebaaaSWei Yongjun ret = PTR_ERR(ethqos->rgmii_clk); 637a7c30e62SVinod Koul goto err_mem; 638a7c30e62SVinod Koul } 639a7c30e62SVinod Koul 6406c950ca7SBhupesh Sharma ret = ethqos_clks_config(ethqos, true); 641a7c30e62SVinod Koul if (ret) 642a7c30e62SVinod Koul goto err_mem; 643a7c30e62SVinod Koul 644*9fc68f23SBartosz Golaszewski ret = devm_add_action_or_reset(&pdev->dev, ethqos_clks_disable, ethqos); 645*9fc68f23SBartosz Golaszewski if (ret) 646*9fc68f23SBartosz Golaszewski goto err_mem; 647*9fc68f23SBartosz Golaszewski 648a7c30e62SVinod Koul ethqos->speed = SPEED_1000; 649a7c30e62SVinod Koul ethqos_update_rgmii_clk(ethqos, SPEED_1000); 650a7c30e62SVinod Koul ethqos_set_func_clk_en(ethqos); 651a7c30e62SVinod Koul 652a7c30e62SVinod Koul plat_dat->bsp_priv = ethqos; 653a7c30e62SVinod Koul plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 6544047b9dbSBhupesh Sharma plat_dat->dump_debug_regs = rgmii_dump; 655a7c30e62SVinod Koul plat_dat->has_gmac4 = 1; 6569bc00973SBartosz Golaszewski if (ethqos->has_emac3) 657b6837619SAndrew Halaney plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 658a7c30e62SVinod Koul plat_dat->pmt = 1; 659a7c30e62SVinod Koul plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); 66054aa39a5SAndrey Konovalov if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 66154aa39a5SAndrey Konovalov plat_dat->rx_clk_runs_in_lpi = 1; 662a7c30e62SVinod Koul 663a7c30e62SVinod Koul ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 664a7c30e62SVinod Koul if (ret) 665*9fc68f23SBartosz Golaszewski goto err_mem; 666a7c30e62SVinod Koul 667a7c30e62SVinod Koul return ret; 668a7c30e62SVinod Koul 669a7c30e62SVinod Koul err_mem: 670a7c30e62SVinod Koul stmmac_remove_config_dt(pdev, plat_dat); 671a7c30e62SVinod Koul 672a7c30e62SVinod Koul return ret; 673a7c30e62SVinod Koul } 674a7c30e62SVinod Koul 675a7c30e62SVinod Koul static const struct of_device_id qcom_ethqos_match[] = { 676fd4a5177SVinod Koul { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 677b6837619SAndrew Halaney { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 678d90b3120SVinod Koul { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 679a7c30e62SVinod Koul { } 680a7c30e62SVinod Koul }; 681a7c30e62SVinod Koul MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 682a7c30e62SVinod Koul 683a7c30e62SVinod Koul static struct platform_driver qcom_ethqos_driver = { 684a7c30e62SVinod Koul .probe = qcom_ethqos_probe, 685*9fc68f23SBartosz Golaszewski .remove_new = stmmac_pltfr_remove, 686a7c30e62SVinod Koul .driver = { 687a7c30e62SVinod Koul .name = "qcom-ethqos", 688a7c30e62SVinod Koul .pm = &stmmac_pltfr_pm_ops, 689dc54e450SKrzysztof Kozlowski .of_match_table = qcom_ethqos_match, 690a7c30e62SVinod Koul }, 691a7c30e62SVinod Koul }; 692a7c30e62SVinod Koul module_platform_driver(qcom_ethqos_driver); 693a7c30e62SVinod Koul 694a7c30e62SVinod Koul MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 695a7c30e62SVinod Koul MODULE_LICENSE("GPL v2"); 696