1a7c30e62SVinod Koul // SPDX-License-Identifier: GPL-2.0 2a7c30e62SVinod Koul // Copyright (c) 2018-19, Linaro Limited 3a7c30e62SVinod Koul 4a7c30e62SVinod Koul #include <linux/module.h> 5a7c30e62SVinod Koul #include <linux/of.h> 6a7c30e62SVinod Koul #include <linux/of_device.h> 7a7c30e62SVinod Koul #include <linux/platform_device.h> 8a7c30e62SVinod Koul #include <linux/phy.h> 9a7c30e62SVinod Koul #include "stmmac.h" 10a7c30e62SVinod Koul #include "stmmac_platform.h" 11a7c30e62SVinod Koul 12a7c30e62SVinod Koul #define RGMII_IO_MACRO_CONFIG 0x0 13a7c30e62SVinod Koul #define SDCC_HC_REG_DLL_CONFIG 0x4 14b6837619SAndrew Halaney #define SDCC_TEST_CTL 0x8 15a7c30e62SVinod Koul #define SDCC_HC_REG_DDR_CONFIG 0xC 16a7c30e62SVinod Koul #define SDCC_HC_REG_DLL_CONFIG2 0x10 17a7c30e62SVinod Koul #define SDC4_STATUS 0x14 18a7c30e62SVinod Koul #define SDCC_USR_CTL 0x18 19a7c30e62SVinod Koul #define RGMII_IO_MACRO_CONFIG2 0x1C 20a7c30e62SVinod Koul #define RGMII_IO_MACRO_DEBUG1 0x20 21a7c30e62SVinod Koul #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 22a7c30e62SVinod Koul 23a7c30e62SVinod Koul /* RGMII_IO_MACRO_CONFIG fields */ 24a7c30e62SVinod Koul #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) 25a7c30e62SVinod Koul #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) 26a7c30e62SVinod Koul #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) 27a7c30e62SVinod Koul #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) 28a7c30e62SVinod Koul #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) 29a7c30e62SVinod Koul #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) 30a7c30e62SVinod Koul #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) 31a7c30e62SVinod Koul #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) 32a7c30e62SVinod Koul #define RGMII_CONFIG_LOOPBACK_EN BIT(2) 33a7c30e62SVinod Koul #define RGMII_CONFIG_PROG_SWAP BIT(1) 34a7c30e62SVinod Koul #define RGMII_CONFIG_DDR_MODE BIT(0) 35a7c30e62SVinod Koul 36a7c30e62SVinod Koul /* SDCC_HC_REG_DLL_CONFIG fields */ 37a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_DLL_RST BIT(30) 38a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_PDN BIT(29) 39a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) 40a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) 41a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) 42a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) 43a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_CDR_EN BIT(17) 44a7c30e62SVinod Koul #define SDCC_DLL_CONFIG_DLL_EN BIT(16) 45a7c30e62SVinod Koul #define SDCC_DLL_MCLK_GATING_EN BIT(5) 46a7c30e62SVinod Koul #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) 47a7c30e62SVinod Koul 48a7c30e62SVinod Koul /* SDCC_HC_REG_DDR_CONFIG fields */ 49a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) 50a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) 51a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) 52a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) 53b6837619SAndrew Halaney #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9) 54a7c30e62SVinod Koul #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) 55a7c30e62SVinod Koul 56a7c30e62SVinod Koul /* SDCC_HC_REG_DLL_CONFIG2 fields */ 57a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) 58a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) 59a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) 60a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) 61a7c30e62SVinod Koul #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) 62a7c30e62SVinod Koul 63a7c30e62SVinod Koul /* SDC4_STATUS bits */ 64a7c30e62SVinod Koul #define SDC4_STATUS_DLL_LOCK BIT(7) 65a7c30e62SVinod Koul 66a7c30e62SVinod Koul /* RGMII_IO_MACRO_CONFIG2 fields */ 67a7c30e62SVinod Koul #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) 68a7c30e62SVinod Koul #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) 69a7c30e62SVinod Koul #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) 70a7c30e62SVinod Koul #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) 71a7c30e62SVinod Koul #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) 72a7c30e62SVinod Koul #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) 73a7c30e62SVinod Koul #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) 74a7c30e62SVinod Koul 75a7c30e62SVinod Koul struct ethqos_emac_por { 76a7c30e62SVinod Koul unsigned int offset; 77a7c30e62SVinod Koul unsigned int value; 78a7c30e62SVinod Koul }; 79a7c30e62SVinod Koul 80fd4a5177SVinod Koul struct ethqos_emac_driver_data { 81fd4a5177SVinod Koul const struct ethqos_emac_por *por; 82fd4a5177SVinod Koul unsigned int num_por; 83030f1d59SAndrew Halaney bool rgmii_config_loopback_en; 84b6837619SAndrew Halaney bool has_emac3; 85b6837619SAndrew Halaney struct dwmac4_addrs dwmac4_addrs; 86fd4a5177SVinod Koul }; 87fd4a5177SVinod Koul 88a7c30e62SVinod Koul struct qcom_ethqos { 89a7c30e62SVinod Koul struct platform_device *pdev; 90a7c30e62SVinod Koul void __iomem *rgmii_base; 91a7c30e62SVinod Koul 92a7c30e62SVinod Koul unsigned int rgmii_clk_rate; 93a7c30e62SVinod Koul struct clk *rgmii_clk; 94a7c30e62SVinod Koul unsigned int speed; 95a7c30e62SVinod Koul 96a7c30e62SVinod Koul const struct ethqos_emac_por *por; 97a7c30e62SVinod Koul unsigned int num_por; 98030f1d59SAndrew Halaney bool rgmii_config_loopback_en; 99b6837619SAndrew Halaney bool has_emac3; 100a7c30e62SVinod Koul }; 101a7c30e62SVinod Koul 102a7c30e62SVinod Koul static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) 103a7c30e62SVinod Koul { 104a7c30e62SVinod Koul return readl(ethqos->rgmii_base + offset); 105a7c30e62SVinod Koul } 106a7c30e62SVinod Koul 107a7c30e62SVinod Koul static void rgmii_writel(struct qcom_ethqos *ethqos, 108a7c30e62SVinod Koul int value, unsigned int offset) 109a7c30e62SVinod Koul { 110a7c30e62SVinod Koul writel(value, ethqos->rgmii_base + offset); 111a7c30e62SVinod Koul } 112a7c30e62SVinod Koul 113a7c30e62SVinod Koul static void rgmii_updatel(struct qcom_ethqos *ethqos, 114a7c30e62SVinod Koul int mask, int val, unsigned int offset) 115a7c30e62SVinod Koul { 116a7c30e62SVinod Koul unsigned int temp; 117a7c30e62SVinod Koul 118a7c30e62SVinod Koul temp = rgmii_readl(ethqos, offset); 119a7c30e62SVinod Koul temp = (temp & ~(mask)) | val; 120a7c30e62SVinod Koul rgmii_writel(ethqos, temp, offset); 121a7c30e62SVinod Koul } 122a7c30e62SVinod Koul 1234047b9dbSBhupesh Sharma static void rgmii_dump(void *priv) 124a7c30e62SVinod Koul { 1254047b9dbSBhupesh Sharma struct qcom_ethqos *ethqos = priv; 126*302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 1274047b9dbSBhupesh Sharma 128*302555a0SBartosz Golaszewski dev_dbg(dev, "Rgmii register dump\n"); 129*302555a0SBartosz Golaszewski dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n", 130a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG)); 131*302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n", 132a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG)); 133*302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n", 134a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG)); 135*302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n", 136a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2)); 137*302555a0SBartosz Golaszewski dev_dbg(dev, "SDC4_STATUS: %x\n", 138a7c30e62SVinod Koul rgmii_readl(ethqos, SDC4_STATUS)); 139*302555a0SBartosz Golaszewski dev_dbg(dev, "SDCC_USR_CTL: %x\n", 140a7c30e62SVinod Koul rgmii_readl(ethqos, SDCC_USR_CTL)); 141*302555a0SBartosz Golaszewski dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n", 142a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2)); 143*302555a0SBartosz Golaszewski dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n", 144a7c30e62SVinod Koul rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1)); 145*302555a0SBartosz Golaszewski dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n", 146a7c30e62SVinod Koul rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG)); 147a7c30e62SVinod Koul } 148a7c30e62SVinod Koul 149a7c30e62SVinod Koul /* Clock rates */ 150a7c30e62SVinod Koul #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) 151a7c30e62SVinod Koul #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) 152a7c30e62SVinod Koul #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) 153a7c30e62SVinod Koul 154a7c30e62SVinod Koul static void 155a7c30e62SVinod Koul ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed) 156a7c30e62SVinod Koul { 157a7c30e62SVinod Koul switch (speed) { 158a7c30e62SVinod Koul case SPEED_1000: 159a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ; 160a7c30e62SVinod Koul break; 161a7c30e62SVinod Koul 162a7c30e62SVinod Koul case SPEED_100: 163a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; 164a7c30e62SVinod Koul break; 165a7c30e62SVinod Koul 166a7c30e62SVinod Koul case SPEED_10: 167a7c30e62SVinod Koul ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; 168a7c30e62SVinod Koul break; 169a7c30e62SVinod Koul } 170a7c30e62SVinod Koul 171a7c30e62SVinod Koul clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate); 172a7c30e62SVinod Koul } 173a7c30e62SVinod Koul 174a7c30e62SVinod Koul static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) 175a7c30e62SVinod Koul { 176a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN, 177a7c30e62SVinod Koul RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); 178a7c30e62SVinod Koul } 179a7c30e62SVinod Koul 180a7c30e62SVinod Koul static const struct ethqos_emac_por emac_v2_3_0_por[] = { 181a7c30e62SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, 182a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 183a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 184a7c30e62SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 185a7c30e62SVinod Koul { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 186a7c30e62SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 187a7c30e62SVinod Koul }; 188a7c30e62SVinod Koul 189fd4a5177SVinod Koul static const struct ethqos_emac_driver_data emac_v2_3_0_data = { 190fd4a5177SVinod Koul .por = emac_v2_3_0_por, 191fd4a5177SVinod Koul .num_por = ARRAY_SIZE(emac_v2_3_0_por), 192030f1d59SAndrew Halaney .rgmii_config_loopback_en = true, 193b6837619SAndrew Halaney .has_emac3 = false, 194fd4a5177SVinod Koul }; 195fd4a5177SVinod Koul 196d90b3120SVinod Koul static const struct ethqos_emac_por emac_v2_1_0_por[] = { 197d90b3120SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 }, 198d90b3120SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, 199d90b3120SVinod Koul { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 }, 200d90b3120SVinod Koul { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 201d90b3120SVinod Koul { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 202d90b3120SVinod Koul { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 203d90b3120SVinod Koul }; 204d90b3120SVinod Koul 205d90b3120SVinod Koul static const struct ethqos_emac_driver_data emac_v2_1_0_data = { 206d90b3120SVinod Koul .por = emac_v2_1_0_por, 207d90b3120SVinod Koul .num_por = ARRAY_SIZE(emac_v2_1_0_por), 208030f1d59SAndrew Halaney .rgmii_config_loopback_en = false, 209b6837619SAndrew Halaney .has_emac3 = false, 210b6837619SAndrew Halaney }; 211b6837619SAndrew Halaney 212b6837619SAndrew Halaney static const struct ethqos_emac_por emac_v3_0_0_por[] = { 213b6837619SAndrew Halaney { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 }, 214b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c }, 215b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 }, 216b6837619SAndrew Halaney { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 }, 217b6837619SAndrew Halaney { .offset = SDCC_USR_CTL, .value = 0x00010800 }, 218b6837619SAndrew Halaney { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 }, 219b6837619SAndrew Halaney }; 220b6837619SAndrew Halaney 221b6837619SAndrew Halaney static const struct ethqos_emac_driver_data emac_v3_0_0_data = { 222b6837619SAndrew Halaney .por = emac_v3_0_0_por, 223b6837619SAndrew Halaney .num_por = ARRAY_SIZE(emac_v3_0_0_por), 224b6837619SAndrew Halaney .rgmii_config_loopback_en = false, 225b6837619SAndrew Halaney .has_emac3 = true, 226b6837619SAndrew Halaney .dwmac4_addrs = { 227b6837619SAndrew Halaney .dma_chan = 0x00008100, 228b6837619SAndrew Halaney .dma_chan_offset = 0x1000, 229b6837619SAndrew Halaney .mtl_chan = 0x00008000, 230b6837619SAndrew Halaney .mtl_chan_offset = 0x1000, 231b6837619SAndrew Halaney .mtl_ets_ctrl = 0x00008010, 232b6837619SAndrew Halaney .mtl_ets_ctrl_offset = 0x1000, 233b6837619SAndrew Halaney .mtl_txq_weight = 0x00008018, 234b6837619SAndrew Halaney .mtl_txq_weight_offset = 0x1000, 235b6837619SAndrew Halaney .mtl_send_slp_cred = 0x0000801c, 236b6837619SAndrew Halaney .mtl_send_slp_cred_offset = 0x1000, 237b6837619SAndrew Halaney .mtl_high_cred = 0x00008020, 238b6837619SAndrew Halaney .mtl_high_cred_offset = 0x1000, 239b6837619SAndrew Halaney .mtl_low_cred = 0x00008024, 240b6837619SAndrew Halaney .mtl_low_cred_offset = 0x1000, 241b6837619SAndrew Halaney }, 242d90b3120SVinod Koul }; 243d90b3120SVinod Koul 244a7c30e62SVinod Koul static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 245a7c30e62SVinod Koul { 246*302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 247a7c30e62SVinod Koul unsigned int val; 248a7c30e62SVinod Koul int retry = 1000; 249a7c30e62SVinod Koul 250a7c30e62SVinod Koul /* Set CDR_EN */ 251a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN, 252a7c30e62SVinod Koul SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG); 253a7c30e62SVinod Koul 254a7c30e62SVinod Koul /* Set CDR_EXT_EN */ 255a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN, 256a7c30e62SVinod Koul SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG); 257a7c30e62SVinod Koul 258a7c30e62SVinod Koul /* Clear CK_OUT_EN */ 259a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 260a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 261a7c30e62SVinod Koul 262a7c30e62SVinod Koul /* Set DLL_EN */ 263a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 264a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 265a7c30e62SVinod Koul 266b6837619SAndrew Halaney if (!ethqos->has_emac3) { 267a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN, 268a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 269a7c30e62SVinod Koul 270a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE, 271a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG); 272b6837619SAndrew Halaney } 273a7c30e62SVinod Koul 274a7c30e62SVinod Koul /* Wait for CK_OUT_EN clear */ 275a7c30e62SVinod Koul do { 276a7c30e62SVinod Koul val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 277a7c30e62SVinod Koul val &= SDCC_DLL_CONFIG_CK_OUT_EN; 278a7c30e62SVinod Koul if (!val) 279a7c30e62SVinod Koul break; 280a7c30e62SVinod Koul mdelay(1); 281a7c30e62SVinod Koul retry--; 282a7c30e62SVinod Koul } while (retry > 0); 283a7c30e62SVinod Koul if (!retry) 284*302555a0SBartosz Golaszewski dev_err(dev, "Clear CK_OUT_EN timedout\n"); 285a7c30e62SVinod Koul 286a7c30e62SVinod Koul /* Set CK_OUT_EN */ 287a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 288a7c30e62SVinod Koul SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG); 289a7c30e62SVinod Koul 290a7c30e62SVinod Koul /* Wait for CK_OUT_EN set */ 291a7c30e62SVinod Koul retry = 1000; 292a7c30e62SVinod Koul do { 293a7c30e62SVinod Koul val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG); 294a7c30e62SVinod Koul val &= SDCC_DLL_CONFIG_CK_OUT_EN; 295a7c30e62SVinod Koul if (val) 296a7c30e62SVinod Koul break; 297a7c30e62SVinod Koul mdelay(1); 298a7c30e62SVinod Koul retry--; 299a7c30e62SVinod Koul } while (retry > 0); 300a7c30e62SVinod Koul if (!retry) 301*302555a0SBartosz Golaszewski dev_err(dev, "Set CK_OUT_EN timedout\n"); 302a7c30e62SVinod Koul 303a7c30e62SVinod Koul /* Set DDR_CAL_EN */ 304a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, 305a7c30e62SVinod Koul SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); 306a7c30e62SVinod Koul 307b6837619SAndrew Halaney if (!ethqos->has_emac3) { 308a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, 309a7c30e62SVinod Koul 0, SDCC_HC_REG_DLL_CONFIG2); 310a7c30e62SVinod Koul 311a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 312a7c30e62SVinod Koul 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2); 313a7c30e62SVinod Koul 314a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, 315a7c30e62SVinod Koul BIT(2), SDCC_HC_REG_DLL_CONFIG2); 316a7c30e62SVinod Koul 317a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 318a7c30e62SVinod Koul SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW, 319a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG2); 320b6837619SAndrew Halaney } 321a7c30e62SVinod Koul 322a7c30e62SVinod Koul return 0; 323a7c30e62SVinod Koul } 324a7c30e62SVinod Koul 325a7c30e62SVinod Koul static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 326a7c30e62SVinod Koul { 327*302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 328164a9ebeSAndrew Halaney int phase_shift; 329164a9ebeSAndrew Halaney int phy_mode; 330030f1d59SAndrew Halaney int loopback; 331164a9ebeSAndrew Halaney 332164a9ebeSAndrew Halaney /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 333*302555a0SBartosz Golaszewski phy_mode = device_get_phy_mode(dev); 334164a9ebeSAndrew Halaney if (phy_mode == PHY_INTERFACE_MODE_RGMII_ID || 335164a9ebeSAndrew Halaney phy_mode == PHY_INTERFACE_MODE_RGMII_TXID) 336164a9ebeSAndrew Halaney phase_shift = 0; 337164a9ebeSAndrew Halaney else 338164a9ebeSAndrew Halaney phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 339164a9ebeSAndrew Halaney 340a7c30e62SVinod Koul /* Disable loopback mode */ 341a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 342a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 343a7c30e62SVinod Koul 344030f1d59SAndrew Halaney /* Determine if this platform wants loopback enabled after programming */ 345030f1d59SAndrew Halaney if (ethqos->rgmii_config_loopback_en) 346030f1d59SAndrew Halaney loopback = RGMII_CONFIG_LOOPBACK_EN; 347030f1d59SAndrew Halaney else 348030f1d59SAndrew Halaney loopback = 0; 349030f1d59SAndrew Halaney 350a7c30e62SVinod Koul /* Select RGMII, write 0 to interface select */ 351a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL, 352a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 353a7c30e62SVinod Koul 354a7c30e62SVinod Koul switch (ethqos->speed) { 355a7c30e62SVinod Koul case SPEED_1000: 356a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 357a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 358a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 359a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 360a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 361a7c30e62SVinod Koul RGMII_CONFIG_POS_NEG_DATA_SEL, 362a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 363a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 364a7c30e62SVinod Koul RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG); 365a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 366a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 367164a9ebeSAndrew Halaney 368a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 369164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 370a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 371a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 372a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 373a7c30e62SVinod Koul RGMII_CONFIG2_RX_PROG_SWAP, 374a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG2); 375a7c30e62SVinod Koul 376b6837619SAndrew Halaney /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 377b6837619SAndrew Halaney * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 378b6837619SAndrew Halaney */ 379b6837619SAndrew Halaney if (ethqos->has_emac3) { 380b6837619SAndrew Halaney /* 0.9 ns */ 381b6837619SAndrew Halaney rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 382b6837619SAndrew Halaney 115, SDCC_HC_REG_DDR_CONFIG); 383b6837619SAndrew Halaney } else { 384b6837619SAndrew Halaney /* 1.8 ns */ 385a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 386a7c30e62SVinod Koul 57, SDCC_HC_REG_DDR_CONFIG); 387b6837619SAndrew Halaney } 388a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 389a7c30e62SVinod Koul SDCC_DDR_CONFIG_PRG_DLY_EN, 390a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 391a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 392030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 393a7c30e62SVinod Koul break; 394a7c30e62SVinod Koul 395a7c30e62SVinod Koul case SPEED_100: 396a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 397a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 398a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 399a7c30e62SVinod Koul RGMII_CONFIG_BYPASS_TX_ID_EN, 400a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 401a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 402a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 403a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 404a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 405a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 406a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 407a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 408164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 409a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 410a7c30e62SVinod Koul BIT(6), RGMII_IO_MACRO_CONFIG); 411a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 412a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 413b6837619SAndrew Halaney 414b6837619SAndrew Halaney if (ethqos->has_emac3) 415b6837619SAndrew Halaney rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 416b6837619SAndrew Halaney RGMII_CONFIG2_RX_PROG_SWAP, 417b6837619SAndrew Halaney RGMII_IO_MACRO_CONFIG2); 418b6837619SAndrew Halaney else 419a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 420a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 421b6837619SAndrew Halaney 422a7c30e62SVinod Koul /* Write 0x5 to PRG_RCLK_DLY_CODE */ 423a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 424a7c30e62SVinod Koul (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 425a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 426a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 427a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 428a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 429a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 430a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 431a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 432030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 433a7c30e62SVinod Koul break; 434a7c30e62SVinod Koul 435a7c30e62SVinod Koul case SPEED_10: 436a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE, 437a7c30e62SVinod Koul RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 438a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 439a7c30e62SVinod Koul RGMII_CONFIG_BYPASS_TX_ID_EN, 440a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 441a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 442a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 443a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP, 444a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG); 445a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 446a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 447a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 448164a9ebeSAndrew Halaney phase_shift, RGMII_IO_MACRO_CONFIG2); 449a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 450a7c30e62SVinod Koul BIT(12) | GENMASK(9, 8), 451a7c30e62SVinod Koul RGMII_IO_MACRO_CONFIG); 452a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 453a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 454b6837619SAndrew Halaney if (ethqos->has_emac3) 455b6837619SAndrew Halaney rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 456b6837619SAndrew Halaney RGMII_CONFIG2_RX_PROG_SWAP, 457b6837619SAndrew Halaney RGMII_IO_MACRO_CONFIG2); 458b6837619SAndrew Halaney else 459a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 460a7c30e62SVinod Koul 0, RGMII_IO_MACRO_CONFIG2); 461a7c30e62SVinod Koul /* Write 0x5 to PRG_RCLK_DLY_CODE */ 462a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 463a7c30e62SVinod Koul (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG); 464a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 465a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 466a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 467a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 468a7c30e62SVinod Koul SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 469a7c30e62SVinod Koul SDCC_HC_REG_DDR_CONFIG); 470a7c30e62SVinod Koul rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 471030f1d59SAndrew Halaney loopback, RGMII_IO_MACRO_CONFIG); 472a7c30e62SVinod Koul break; 473a7c30e62SVinod Koul default: 474*302555a0SBartosz Golaszewski dev_err(dev, "Invalid speed %d\n", ethqos->speed); 475a7c30e62SVinod Koul return -EINVAL; 476a7c30e62SVinod Koul } 477a7c30e62SVinod Koul 478a7c30e62SVinod Koul return 0; 479a7c30e62SVinod Koul } 480a7c30e62SVinod Koul 481a7c30e62SVinod Koul static int ethqos_configure(struct qcom_ethqos *ethqos) 482a7c30e62SVinod Koul { 483*302555a0SBartosz Golaszewski struct device *dev = ðqos->pdev->dev; 484a7c30e62SVinod Koul volatile unsigned int dll_lock; 485a7c30e62SVinod Koul unsigned int i, retry = 1000; 486a7c30e62SVinod Koul 487a7c30e62SVinod Koul /* Reset to POR values and enable clk */ 488a7c30e62SVinod Koul for (i = 0; i < ethqos->num_por; i++) 489a7c30e62SVinod Koul rgmii_writel(ethqos, ethqos->por[i].value, 490a7c30e62SVinod Koul ethqos->por[i].offset); 491a7c30e62SVinod Koul ethqos_set_func_clk_en(ethqos); 492a7c30e62SVinod Koul 493a7c30e62SVinod Koul /* Initialize the DLL first */ 494a7c30e62SVinod Koul 495a7c30e62SVinod Koul /* Set DLL_RST */ 496a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 497a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG); 498a7c30e62SVinod Koul 499a7c30e62SVinod Koul /* Set PDN */ 500a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 501a7c30e62SVinod Koul SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); 502a7c30e62SVinod Koul 503b6837619SAndrew Halaney if (ethqos->has_emac3) { 504b6837619SAndrew Halaney if (ethqos->speed == SPEED_1000) { 505b6837619SAndrew Halaney rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); 506b6837619SAndrew Halaney rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); 507b6837619SAndrew Halaney rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 508b6837619SAndrew Halaney } else { 509b6837619SAndrew Halaney rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL); 510b6837619SAndrew Halaney rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2); 511b6837619SAndrew Halaney } 512b6837619SAndrew Halaney } 513b6837619SAndrew Halaney 514a7c30e62SVinod Koul /* Clear DLL_RST */ 515a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0, 516a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 517a7c30e62SVinod Koul 518a7c30e62SVinod Koul /* Clear PDN */ 519a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0, 520a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 521a7c30e62SVinod Koul 522a7c30e62SVinod Koul if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) { 523a7c30e62SVinod Koul /* Set DLL_EN */ 524a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN, 525a7c30e62SVinod Koul SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); 526a7c30e62SVinod Koul 527a7c30e62SVinod Koul /* Set CK_OUT_EN */ 528a7c30e62SVinod Koul rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN, 529a7c30e62SVinod Koul SDCC_DLL_CONFIG_CK_OUT_EN, 530a7c30e62SVinod Koul SDCC_HC_REG_DLL_CONFIG); 531a7c30e62SVinod Koul 532a7c30e62SVinod Koul /* Set USR_CTL bit 26 with mask of 3 bits */ 533b6837619SAndrew Halaney if (!ethqos->has_emac3) 534b6837619SAndrew Halaney rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), 535b6837619SAndrew Halaney SDCC_USR_CTL); 536a7c30e62SVinod Koul 537a7c30e62SVinod Koul /* wait for DLL LOCK */ 538a7c30e62SVinod Koul do { 539a7c30e62SVinod Koul mdelay(1); 540a7c30e62SVinod Koul dll_lock = rgmii_readl(ethqos, SDC4_STATUS); 541a7c30e62SVinod Koul if (dll_lock & SDC4_STATUS_DLL_LOCK) 542a7c30e62SVinod Koul break; 5437d10f077SDejin Zheng retry--; 544a7c30e62SVinod Koul } while (retry > 0); 545a7c30e62SVinod Koul if (!retry) 546*302555a0SBartosz Golaszewski dev_err(dev, "Timeout while waiting for DLL lock\n"); 547a7c30e62SVinod Koul } 548a7c30e62SVinod Koul 549a7c30e62SVinod Koul if (ethqos->speed == SPEED_1000) 550a7c30e62SVinod Koul ethqos_dll_configure(ethqos); 551a7c30e62SVinod Koul 552a7c30e62SVinod Koul ethqos_rgmii_macro_init(ethqos); 553a7c30e62SVinod Koul 554a7c30e62SVinod Koul return 0; 555a7c30e62SVinod Koul } 556a7c30e62SVinod Koul 557a7c30e62SVinod Koul static void ethqos_fix_mac_speed(void *priv, unsigned int speed) 558a7c30e62SVinod Koul { 559a7c30e62SVinod Koul struct qcom_ethqos *ethqos = priv; 560a7c30e62SVinod Koul 561a7c30e62SVinod Koul ethqos->speed = speed; 562a7c30e62SVinod Koul ethqos_update_rgmii_clk(ethqos, speed); 563a7c30e62SVinod Koul ethqos_configure(ethqos); 564a7c30e62SVinod Koul } 565a7c30e62SVinod Koul 5666c950ca7SBhupesh Sharma static int ethqos_clks_config(void *priv, bool enabled) 5676c950ca7SBhupesh Sharma { 5686c950ca7SBhupesh Sharma struct qcom_ethqos *ethqos = priv; 5696c950ca7SBhupesh Sharma int ret = 0; 5706c950ca7SBhupesh Sharma 5716c950ca7SBhupesh Sharma if (enabled) { 5726c950ca7SBhupesh Sharma ret = clk_prepare_enable(ethqos->rgmii_clk); 5736c950ca7SBhupesh Sharma if (ret) { 5746c950ca7SBhupesh Sharma dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n"); 5756c950ca7SBhupesh Sharma return ret; 5766c950ca7SBhupesh Sharma } 577ffba2123SBjorn Andersson 578ffba2123SBjorn Andersson /* Enable functional clock to prevent DMA reset to timeout due 579ffba2123SBjorn Andersson * to lacking PHY clock after the hardware block has been power 580ffba2123SBjorn Andersson * cycled. The actual configuration will be adjusted once 581ffba2123SBjorn Andersson * ethqos_fix_mac_speed() is invoked. 582ffba2123SBjorn Andersson */ 583ffba2123SBjorn Andersson ethqos_set_func_clk_en(ethqos); 5846c950ca7SBhupesh Sharma } else { 5856c950ca7SBhupesh Sharma clk_disable_unprepare(ethqos->rgmii_clk); 5866c950ca7SBhupesh Sharma } 5876c950ca7SBhupesh Sharma 5886c950ca7SBhupesh Sharma return ret; 5896c950ca7SBhupesh Sharma } 5906c950ca7SBhupesh Sharma 5919fc68f23SBartosz Golaszewski static void ethqos_clks_disable(void *data) 5929fc68f23SBartosz Golaszewski { 5939fc68f23SBartosz Golaszewski ethqos_clks_config(data, false); 5949fc68f23SBartosz Golaszewski } 5959fc68f23SBartosz Golaszewski 596a7c30e62SVinod Koul static int qcom_ethqos_probe(struct platform_device *pdev) 597a7c30e62SVinod Koul { 598a7c30e62SVinod Koul struct device_node *np = pdev->dev.of_node; 5997b5e64a9SBartosz Golaszewski const struct ethqos_emac_driver_data *data; 600a7c30e62SVinod Koul struct plat_stmmacenet_data *plat_dat; 601a7c30e62SVinod Koul struct stmmac_resources stmmac_res; 602*302555a0SBartosz Golaszewski struct device *dev = &pdev->dev; 603a7c30e62SVinod Koul struct qcom_ethqos *ethqos; 604a7c30e62SVinod Koul int ret; 605a7c30e62SVinod Koul 606a7c30e62SVinod Koul ret = stmmac_get_platform_resources(pdev, &stmmac_res); 607a7c30e62SVinod Koul if (ret) 608a7c30e62SVinod Koul return ret; 609a7c30e62SVinod Koul 61083216e39SMichael Walle plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); 611a7c30e62SVinod Koul if (IS_ERR(plat_dat)) { 612*302555a0SBartosz Golaszewski dev_err(dev, "dt configuration failed\n"); 613a7c30e62SVinod Koul return PTR_ERR(plat_dat); 614a7c30e62SVinod Koul } 615a7c30e62SVinod Koul 6166c950ca7SBhupesh Sharma plat_dat->clks_config = ethqos_clks_config; 6176c950ca7SBhupesh Sharma 618*302555a0SBartosz Golaszewski ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); 619a7c30e62SVinod Koul if (!ethqos) { 620a7c30e62SVinod Koul ret = -ENOMEM; 6219bc58060SBartosz Golaszewski goto out_config_dt; 622a7c30e62SVinod Koul } 623a7c30e62SVinod Koul 624a7c30e62SVinod Koul ethqos->pdev = pdev; 6253a5a32b5SYang Yingliang ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); 626a7c30e62SVinod Koul if (IS_ERR(ethqos->rgmii_base)) { 627a7c30e62SVinod Koul ret = PTR_ERR(ethqos->rgmii_base); 6289bc58060SBartosz Golaszewski goto out_config_dt; 629a7c30e62SVinod Koul } 630a7c30e62SVinod Koul 631*302555a0SBartosz Golaszewski data = of_device_get_match_data(dev); 632fd4a5177SVinod Koul ethqos->por = data->por; 633fd4a5177SVinod Koul ethqos->num_por = data->num_por; 634030f1d59SAndrew Halaney ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; 635b6837619SAndrew Halaney ethqos->has_emac3 = data->has_emac3; 636a7c30e62SVinod Koul 637*302555a0SBartosz Golaszewski ethqos->rgmii_clk = devm_clk_get(dev, "rgmii"); 6388f4ebaaaSWei Yongjun if (IS_ERR(ethqos->rgmii_clk)) { 6398f4ebaaaSWei Yongjun ret = PTR_ERR(ethqos->rgmii_clk); 6409bc58060SBartosz Golaszewski goto out_config_dt; 641a7c30e62SVinod Koul } 642a7c30e62SVinod Koul 6436c950ca7SBhupesh Sharma ret = ethqos_clks_config(ethqos, true); 644a7c30e62SVinod Koul if (ret) 6459bc58060SBartosz Golaszewski goto out_config_dt; 646a7c30e62SVinod Koul 647*302555a0SBartosz Golaszewski ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); 6489fc68f23SBartosz Golaszewski if (ret) 6499bc58060SBartosz Golaszewski goto out_config_dt; 6509fc68f23SBartosz Golaszewski 651a7c30e62SVinod Koul ethqos->speed = SPEED_1000; 652a7c30e62SVinod Koul ethqos_update_rgmii_clk(ethqos, SPEED_1000); 653a7c30e62SVinod Koul ethqos_set_func_clk_en(ethqos); 654a7c30e62SVinod Koul 655a7c30e62SVinod Koul plat_dat->bsp_priv = ethqos; 656a7c30e62SVinod Koul plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 6574047b9dbSBhupesh Sharma plat_dat->dump_debug_regs = rgmii_dump; 658a7c30e62SVinod Koul plat_dat->has_gmac4 = 1; 6599bc00973SBartosz Golaszewski if (ethqos->has_emac3) 660b6837619SAndrew Halaney plat_dat->dwmac4_addrs = &data->dwmac4_addrs; 661a7c30e62SVinod Koul plat_dat->pmt = 1; 662a7c30e62SVinod Koul plat_dat->tso_en = of_property_read_bool(np, "snps,tso"); 66354aa39a5SAndrey Konovalov if (of_device_is_compatible(np, "qcom,qcs404-ethqos")) 66454aa39a5SAndrey Konovalov plat_dat->rx_clk_runs_in_lpi = 1; 665a7c30e62SVinod Koul 666*302555a0SBartosz Golaszewski ret = stmmac_dvr_probe(dev, plat_dat, &stmmac_res); 667a7c30e62SVinod Koul if (ret) 6689bc58060SBartosz Golaszewski goto out_config_dt; 669a7c30e62SVinod Koul 670a7c30e62SVinod Koul return ret; 671a7c30e62SVinod Koul 6729bc58060SBartosz Golaszewski out_config_dt: 673a7c30e62SVinod Koul stmmac_remove_config_dt(pdev, plat_dat); 674a7c30e62SVinod Koul 675a7c30e62SVinod Koul return ret; 676a7c30e62SVinod Koul } 677a7c30e62SVinod Koul 678a7c30e62SVinod Koul static const struct of_device_id qcom_ethqos_match[] = { 679fd4a5177SVinod Koul { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, 680b6837619SAndrew Halaney { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, 681d90b3120SVinod Koul { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, 682a7c30e62SVinod Koul { } 683a7c30e62SVinod Koul }; 684a7c30e62SVinod Koul MODULE_DEVICE_TABLE(of, qcom_ethqos_match); 685a7c30e62SVinod Koul 686a7c30e62SVinod Koul static struct platform_driver qcom_ethqos_driver = { 687a7c30e62SVinod Koul .probe = qcom_ethqos_probe, 6889fc68f23SBartosz Golaszewski .remove_new = stmmac_pltfr_remove, 689a7c30e62SVinod Koul .driver = { 690a7c30e62SVinod Koul .name = "qcom-ethqos", 691a7c30e62SVinod Koul .pm = &stmmac_pltfr_pm_ops, 692dc54e450SKrzysztof Kozlowski .of_match_table = qcom_ethqos_match, 693a7c30e62SVinod Koul }, 694a7c30e62SVinod Koul }; 695a7c30e62SVinod Koul module_platform_driver(qcom_ethqos_driver); 696a7c30e62SVinod Koul 697a7c30e62SVinod Koul MODULE_DESCRIPTION("Qualcomm ETHQOS driver"); 698a7c30e62SVinod Koul MODULE_LICENSE("GPL v2"); 699