1 /* 2 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer 3 * 4 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/device.h> 17 #include <linux/ethtool.h> 18 #include <linux/io.h> 19 #include <linux/ioport.h> 20 #include <linux/module.h> 21 #include <linux/of_net.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/platform_device.h> 24 #include <linux/stmmac.h> 25 26 #include "stmmac_platform.h" 27 28 #define PRG_ETH0 0x0 29 30 #define PRG_ETH0_RGMII_MODE BIT(0) 31 32 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ 33 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 34 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) 35 36 #define PRG_ETH0_TXDLY_SHIFT 5 37 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) 38 39 /* divider for the result of m250_sel */ 40 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7 41 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3 42 43 #define PRG_ETH0_RGMII_TX_CLK_EN 10 44 45 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) 46 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) 47 48 #define MUX_CLK_NUM_PARENTS 2 49 50 struct meson8b_dwmac { 51 struct device *dev; 52 void __iomem *regs; 53 phy_interface_t phy_mode; 54 struct clk *rgmii_tx_clk; 55 u32 tx_delay_ns; 56 }; 57 58 struct meson8b_dwmac_clk_configs { 59 struct clk_mux m250_mux; 60 struct clk_divider m250_div; 61 struct clk_fixed_factor fixed_div2; 62 struct clk_gate rgmii_tx_en; 63 }; 64 65 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, 66 u32 mask, u32 value) 67 { 68 u32 data; 69 70 data = readl(dwmac->regs + reg); 71 data &= ~mask; 72 data |= (value & mask); 73 74 writel(data, dwmac->regs + reg); 75 } 76 77 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, 78 const char *name_suffix, 79 const char **parent_names, 80 int num_parents, 81 const struct clk_ops *ops, 82 struct clk_hw *hw) 83 { 84 struct clk_init_data init; 85 char clk_name[32]; 86 87 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), 88 name_suffix); 89 90 init.name = clk_name; 91 init.ops = ops; 92 init.flags = CLK_SET_RATE_PARENT; 93 init.parent_names = parent_names; 94 init.num_parents = num_parents; 95 96 hw->init = &init; 97 98 return devm_clk_register(dwmac->dev, hw); 99 } 100 101 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) 102 { 103 int i, ret; 104 struct clk *clk; 105 struct device *dev = dwmac->dev; 106 const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS]; 107 struct meson8b_dwmac_clk_configs *clk_configs; 108 109 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL); 110 if (!clk_configs) 111 return -ENOMEM; 112 113 /* get the mux parents from DT */ 114 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 115 char name[16]; 116 117 snprintf(name, sizeof(name), "clkin%d", i); 118 clk = devm_clk_get(dev, name); 119 if (IS_ERR(clk)) { 120 ret = PTR_ERR(clk); 121 if (ret != -EPROBE_DEFER) 122 dev_err(dev, "Missing clock %s\n", name); 123 return ret; 124 } 125 126 mux_parent_names[i] = __clk_get_name(clk); 127 } 128 129 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0; 130 clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; 131 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; 132 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names, 133 MUX_CLK_NUM_PARENTS, &clk_mux_ops, 134 &clk_configs->m250_mux.hw); 135 if (WARN_ON(IS_ERR(clk))) 136 return PTR_ERR(clk); 137 138 parent_name = __clk_get_name(clk); 139 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0; 140 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; 141 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; 142 clk_configs->m250_div.flags = CLK_DIVIDER_ONE_BASED | 143 CLK_DIVIDER_ALLOW_ZERO | 144 CLK_DIVIDER_ROUND_CLOSEST; 145 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1, 146 &clk_divider_ops, 147 &clk_configs->m250_div.hw); 148 if (WARN_ON(IS_ERR(clk))) 149 return PTR_ERR(clk); 150 151 parent_name = __clk_get_name(clk); 152 clk_configs->fixed_div2.mult = 1; 153 clk_configs->fixed_div2.div = 2; 154 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1, 155 &clk_fixed_factor_ops, 156 &clk_configs->fixed_div2.hw); 157 if (WARN_ON(IS_ERR(clk))) 158 return PTR_ERR(clk); 159 160 parent_name = __clk_get_name(clk); 161 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0; 162 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN; 163 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1, 164 &clk_gate_ops, 165 &clk_configs->rgmii_tx_en.hw); 166 if (WARN_ON(IS_ERR(clk))) 167 return PTR_ERR(clk); 168 169 dwmac->rgmii_tx_clk = clk; 170 171 return 0; 172 } 173 174 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) 175 { 176 int ret; 177 u8 tx_dly_val = 0; 178 179 switch (dwmac->phy_mode) { 180 case PHY_INTERFACE_MODE_RGMII: 181 case PHY_INTERFACE_MODE_RGMII_RXID: 182 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 183 * 8ns are exactly one cycle of the 125MHz RGMII TX clock): 184 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 185 */ 186 tx_dly_val = dwmac->tx_delay_ns >> 1; 187 /* fall through */ 188 189 case PHY_INTERFACE_MODE_RGMII_ID: 190 case PHY_INTERFACE_MODE_RGMII_TXID: 191 /* enable RGMII mode */ 192 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, 193 PRG_ETH0_RGMII_MODE); 194 195 /* only relevant for RMII mode -> disable in RGMII mode */ 196 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 197 PRG_ETH0_INVERTED_RMII_CLK, 0); 198 199 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, 200 tx_dly_val << PRG_ETH0_TXDLY_SHIFT); 201 202 /* Configure the 125MHz RGMII TX clock, the IP block changes 203 * the output automatically (= without us having to configure 204 * a register) based on the line-speed (125MHz for Gbit speeds, 205 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). 206 */ 207 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); 208 if (ret) { 209 dev_err(dwmac->dev, 210 "failed to set RGMII TX clock\n"); 211 return ret; 212 } 213 214 ret = clk_prepare_enable(dwmac->rgmii_tx_clk); 215 if (ret) { 216 dev_err(dwmac->dev, 217 "failed to enable the RGMII TX clock\n"); 218 return ret; 219 } 220 221 devm_add_action_or_reset(dwmac->dev, 222 (void(*)(void *))clk_disable_unprepare, 223 dwmac->rgmii_tx_clk); 224 break; 225 226 case PHY_INTERFACE_MODE_RMII: 227 /* disable RGMII mode -> enables RMII mode */ 228 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, 229 0); 230 231 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ 232 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 233 PRG_ETH0_INVERTED_RMII_CLK, 234 PRG_ETH0_INVERTED_RMII_CLK); 235 236 /* TX clock delay cannot be configured in RMII mode */ 237 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, 238 0); 239 240 break; 241 242 default: 243 dev_err(dwmac->dev, "unsupported phy-mode %s\n", 244 phy_modes(dwmac->phy_mode)); 245 return -EINVAL; 246 } 247 248 /* enable TX_CLK and PHY_REF_CLK generator */ 249 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, 250 PRG_ETH0_TX_AND_PHY_REF_CLK); 251 252 return 0; 253 } 254 255 static int meson8b_dwmac_probe(struct platform_device *pdev) 256 { 257 struct plat_stmmacenet_data *plat_dat; 258 struct stmmac_resources stmmac_res; 259 struct resource *res; 260 struct meson8b_dwmac *dwmac; 261 int ret; 262 263 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 264 if (ret) 265 return ret; 266 267 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 268 if (IS_ERR(plat_dat)) 269 return PTR_ERR(plat_dat); 270 271 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 272 if (!dwmac) { 273 ret = -ENOMEM; 274 goto err_remove_config_dt; 275 } 276 277 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 278 dwmac->regs = devm_ioremap_resource(&pdev->dev, res); 279 if (IS_ERR(dwmac->regs)) { 280 ret = PTR_ERR(dwmac->regs); 281 goto err_remove_config_dt; 282 } 283 284 dwmac->dev = &pdev->dev; 285 dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node); 286 if (dwmac->phy_mode < 0) { 287 dev_err(&pdev->dev, "missing phy-mode property\n"); 288 ret = -EINVAL; 289 goto err_remove_config_dt; 290 } 291 292 /* use 2ns as fallback since this value was previously hardcoded */ 293 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns", 294 &dwmac->tx_delay_ns)) 295 dwmac->tx_delay_ns = 2; 296 297 ret = meson8b_init_rgmii_tx_clk(dwmac); 298 if (ret) 299 goto err_remove_config_dt; 300 301 ret = meson8b_init_prg_eth(dwmac); 302 if (ret) 303 goto err_remove_config_dt; 304 305 plat_dat->bsp_priv = dwmac; 306 307 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 308 if (ret) 309 goto err_remove_config_dt; 310 311 return 0; 312 313 err_remove_config_dt: 314 stmmac_remove_config_dt(pdev, plat_dat); 315 316 return ret; 317 } 318 319 static const struct of_device_id meson8b_dwmac_match[] = { 320 { .compatible = "amlogic,meson8b-dwmac" }, 321 { .compatible = "amlogic,meson8m2-dwmac" }, 322 { .compatible = "amlogic,meson-gxbb-dwmac" }, 323 { } 324 }; 325 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); 326 327 static struct platform_driver meson8b_dwmac_driver = { 328 .probe = meson8b_dwmac_probe, 329 .remove = stmmac_pltfr_remove, 330 .driver = { 331 .name = "meson8b-dwmac", 332 .pm = &stmmac_pltfr_pm_ops, 333 .of_match_table = meson8b_dwmac_match, 334 }, 335 }; 336 module_platform_driver(meson8b_dwmac_driver); 337 338 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 339 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer"); 340 MODULE_LICENSE("GPL v2"); 341