1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer 4 * 5 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/device.h> 11 #include <linux/ethtool.h> 12 #include <linux/io.h> 13 #include <linux/ioport.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/of_net.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/platform_device.h> 19 #include <linux/stmmac.h> 20 21 #include "stmmac_platform.h" 22 23 #define PRG_ETH0 0x0 24 25 #define PRG_ETH0_RGMII_MODE BIT(0) 26 27 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) 28 #define PRG_ETH0_EXT_RGMII_MODE 1 29 #define PRG_ETH0_EXT_RMII_MODE 4 30 31 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ 32 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) 34 35 #define PRG_ETH0_TXDLY_SHIFT 5 36 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) 37 38 /* divider for the result of m250_sel */ 39 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7 40 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3 41 42 #define PRG_ETH0_RGMII_TX_CLK_EN 10 43 44 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) 45 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) 46 47 #define MUX_CLK_NUM_PARENTS 2 48 49 struct meson8b_dwmac; 50 51 struct meson8b_dwmac_data { 52 int (*set_phy_mode)(struct meson8b_dwmac *dwmac); 53 }; 54 55 struct meson8b_dwmac { 56 struct device *dev; 57 void __iomem *regs; 58 59 const struct meson8b_dwmac_data *data; 60 phy_interface_t phy_mode; 61 struct clk *rgmii_tx_clk; 62 u32 tx_delay_ns; 63 }; 64 65 struct meson8b_dwmac_clk_configs { 66 struct clk_mux m250_mux; 67 struct clk_divider m250_div; 68 struct clk_fixed_factor fixed_div2; 69 struct clk_gate rgmii_tx_en; 70 }; 71 72 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, 73 u32 mask, u32 value) 74 { 75 u32 data; 76 77 data = readl(dwmac->regs + reg); 78 data &= ~mask; 79 data |= (value & mask); 80 81 writel(data, dwmac->regs + reg); 82 } 83 84 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, 85 const char *name_suffix, 86 const char **parent_names, 87 int num_parents, 88 const struct clk_ops *ops, 89 struct clk_hw *hw) 90 { 91 struct clk_init_data init; 92 char clk_name[32]; 93 94 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), 95 name_suffix); 96 97 init.name = clk_name; 98 init.ops = ops; 99 init.flags = CLK_SET_RATE_PARENT; 100 init.parent_names = parent_names; 101 init.num_parents = num_parents; 102 103 hw->init = &init; 104 105 return devm_clk_register(dwmac->dev, hw); 106 } 107 108 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) 109 { 110 int i, ret; 111 struct clk *clk; 112 struct device *dev = dwmac->dev; 113 const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS]; 114 struct meson8b_dwmac_clk_configs *clk_configs; 115 116 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL); 117 if (!clk_configs) 118 return -ENOMEM; 119 120 /* get the mux parents from DT */ 121 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 122 char name[16]; 123 124 snprintf(name, sizeof(name), "clkin%d", i); 125 clk = devm_clk_get(dev, name); 126 if (IS_ERR(clk)) { 127 ret = PTR_ERR(clk); 128 if (ret != -EPROBE_DEFER) 129 dev_err(dev, "Missing clock %s\n", name); 130 return ret; 131 } 132 133 mux_parent_names[i] = __clk_get_name(clk); 134 } 135 136 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0; 137 clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; 138 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; 139 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names, 140 MUX_CLK_NUM_PARENTS, &clk_mux_ops, 141 &clk_configs->m250_mux.hw); 142 if (WARN_ON(IS_ERR(clk))) 143 return PTR_ERR(clk); 144 145 parent_name = __clk_get_name(clk); 146 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0; 147 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; 148 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; 149 clk_configs->m250_div.flags = CLK_DIVIDER_ONE_BASED | 150 CLK_DIVIDER_ALLOW_ZERO | 151 CLK_DIVIDER_ROUND_CLOSEST; 152 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1, 153 &clk_divider_ops, 154 &clk_configs->m250_div.hw); 155 if (WARN_ON(IS_ERR(clk))) 156 return PTR_ERR(clk); 157 158 parent_name = __clk_get_name(clk); 159 clk_configs->fixed_div2.mult = 1; 160 clk_configs->fixed_div2.div = 2; 161 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1, 162 &clk_fixed_factor_ops, 163 &clk_configs->fixed_div2.hw); 164 if (WARN_ON(IS_ERR(clk))) 165 return PTR_ERR(clk); 166 167 parent_name = __clk_get_name(clk); 168 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0; 169 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN; 170 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1, 171 &clk_gate_ops, 172 &clk_configs->rgmii_tx_en.hw); 173 if (WARN_ON(IS_ERR(clk))) 174 return PTR_ERR(clk); 175 176 dwmac->rgmii_tx_clk = clk; 177 178 return 0; 179 } 180 181 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac) 182 { 183 switch (dwmac->phy_mode) { 184 case PHY_INTERFACE_MODE_RGMII: 185 case PHY_INTERFACE_MODE_RGMII_RXID: 186 case PHY_INTERFACE_MODE_RGMII_ID: 187 case PHY_INTERFACE_MODE_RGMII_TXID: 188 /* enable RGMII mode */ 189 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 190 PRG_ETH0_RGMII_MODE, 191 PRG_ETH0_RGMII_MODE); 192 break; 193 case PHY_INTERFACE_MODE_RMII: 194 /* disable RGMII mode -> enables RMII mode */ 195 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 196 PRG_ETH0_RGMII_MODE, 0); 197 break; 198 default: 199 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 200 phy_modes(dwmac->phy_mode)); 201 return -EINVAL; 202 } 203 204 return 0; 205 } 206 207 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) 208 { 209 switch (dwmac->phy_mode) { 210 case PHY_INTERFACE_MODE_RGMII: 211 case PHY_INTERFACE_MODE_RGMII_RXID: 212 case PHY_INTERFACE_MODE_RGMII_ID: 213 case PHY_INTERFACE_MODE_RGMII_TXID: 214 /* enable RGMII mode */ 215 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 216 PRG_ETH0_EXT_PHY_MODE_MASK, 217 PRG_ETH0_EXT_RGMII_MODE); 218 break; 219 case PHY_INTERFACE_MODE_RMII: 220 /* disable RGMII mode -> enables RMII mode */ 221 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 222 PRG_ETH0_EXT_PHY_MODE_MASK, 223 PRG_ETH0_EXT_RMII_MODE); 224 break; 225 default: 226 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 227 phy_modes(dwmac->phy_mode)); 228 return -EINVAL; 229 } 230 231 return 0; 232 } 233 234 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) 235 { 236 int ret; 237 u8 tx_dly_val = 0; 238 239 switch (dwmac->phy_mode) { 240 case PHY_INTERFACE_MODE_RGMII: 241 case PHY_INTERFACE_MODE_RGMII_RXID: 242 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 243 * 8ns are exactly one cycle of the 125MHz RGMII TX clock): 244 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 245 */ 246 tx_dly_val = dwmac->tx_delay_ns >> 1; 247 /* fall through */ 248 249 case PHY_INTERFACE_MODE_RGMII_ID: 250 case PHY_INTERFACE_MODE_RGMII_TXID: 251 /* only relevant for RMII mode -> disable in RGMII mode */ 252 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 253 PRG_ETH0_INVERTED_RMII_CLK, 0); 254 255 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, 256 tx_dly_val << PRG_ETH0_TXDLY_SHIFT); 257 258 /* Configure the 125MHz RGMII TX clock, the IP block changes 259 * the output automatically (= without us having to configure 260 * a register) based on the line-speed (125MHz for Gbit speeds, 261 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). 262 */ 263 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); 264 if (ret) { 265 dev_err(dwmac->dev, 266 "failed to set RGMII TX clock\n"); 267 return ret; 268 } 269 270 ret = clk_prepare_enable(dwmac->rgmii_tx_clk); 271 if (ret) { 272 dev_err(dwmac->dev, 273 "failed to enable the RGMII TX clock\n"); 274 return ret; 275 } 276 277 devm_add_action_or_reset(dwmac->dev, 278 (void(*)(void *))clk_disable_unprepare, 279 dwmac->rgmii_tx_clk); 280 break; 281 282 case PHY_INTERFACE_MODE_RMII: 283 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ 284 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 285 PRG_ETH0_INVERTED_RMII_CLK, 286 PRG_ETH0_INVERTED_RMII_CLK); 287 288 /* TX clock delay cannot be configured in RMII mode */ 289 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, 290 0); 291 292 break; 293 294 default: 295 dev_err(dwmac->dev, "unsupported phy-mode %s\n", 296 phy_modes(dwmac->phy_mode)); 297 return -EINVAL; 298 } 299 300 /* enable TX_CLK and PHY_REF_CLK generator */ 301 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, 302 PRG_ETH0_TX_AND_PHY_REF_CLK); 303 304 return 0; 305 } 306 307 static int meson8b_dwmac_probe(struct platform_device *pdev) 308 { 309 struct plat_stmmacenet_data *plat_dat; 310 struct stmmac_resources stmmac_res; 311 struct resource *res; 312 struct meson8b_dwmac *dwmac; 313 int ret; 314 315 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 316 if (ret) 317 return ret; 318 319 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 320 if (IS_ERR(plat_dat)) 321 return PTR_ERR(plat_dat); 322 323 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 324 if (!dwmac) { 325 ret = -ENOMEM; 326 goto err_remove_config_dt; 327 } 328 329 dwmac->data = (const struct meson8b_dwmac_data *) 330 of_device_get_match_data(&pdev->dev); 331 if (!dwmac->data) { 332 ret = -EINVAL; 333 goto err_remove_config_dt; 334 } 335 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 336 dwmac->regs = devm_ioremap_resource(&pdev->dev, res); 337 if (IS_ERR(dwmac->regs)) { 338 ret = PTR_ERR(dwmac->regs); 339 goto err_remove_config_dt; 340 } 341 342 dwmac->dev = &pdev->dev; 343 dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node); 344 if (dwmac->phy_mode < 0) { 345 dev_err(&pdev->dev, "missing phy-mode property\n"); 346 ret = -EINVAL; 347 goto err_remove_config_dt; 348 } 349 350 /* use 2ns as fallback since this value was previously hardcoded */ 351 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns", 352 &dwmac->tx_delay_ns)) 353 dwmac->tx_delay_ns = 2; 354 355 ret = meson8b_init_rgmii_tx_clk(dwmac); 356 if (ret) 357 goto err_remove_config_dt; 358 359 ret = dwmac->data->set_phy_mode(dwmac); 360 if (ret) 361 goto err_remove_config_dt; 362 363 ret = meson8b_init_prg_eth(dwmac); 364 if (ret) 365 goto err_remove_config_dt; 366 367 plat_dat->bsp_priv = dwmac; 368 369 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 370 if (ret) 371 goto err_remove_config_dt; 372 373 return 0; 374 375 err_remove_config_dt: 376 stmmac_remove_config_dt(pdev, plat_dat); 377 378 return ret; 379 } 380 381 static const struct meson8b_dwmac_data meson8b_dwmac_data = { 382 .set_phy_mode = meson8b_set_phy_mode, 383 }; 384 385 static const struct meson8b_dwmac_data meson_axg_dwmac_data = { 386 .set_phy_mode = meson_axg_set_phy_mode, 387 }; 388 389 static const struct of_device_id meson8b_dwmac_match[] = { 390 { 391 .compatible = "amlogic,meson8b-dwmac", 392 .data = &meson8b_dwmac_data, 393 }, 394 { 395 .compatible = "amlogic,meson8m2-dwmac", 396 .data = &meson8b_dwmac_data, 397 }, 398 { 399 .compatible = "amlogic,meson-gxbb-dwmac", 400 .data = &meson8b_dwmac_data, 401 }, 402 { 403 .compatible = "amlogic,meson-axg-dwmac", 404 .data = &meson_axg_dwmac_data, 405 }, 406 { } 407 }; 408 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); 409 410 static struct platform_driver meson8b_dwmac_driver = { 411 .probe = meson8b_dwmac_probe, 412 .remove = stmmac_pltfr_remove, 413 .driver = { 414 .name = "meson8b-dwmac", 415 .pm = &stmmac_pltfr_pm_ops, 416 .of_match_table = meson8b_dwmac_match, 417 }, 418 }; 419 module_platform_driver(meson8b_dwmac_driver); 420 421 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 422 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer"); 423 MODULE_LICENSE("GPL v2"); 424