1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer 4 * 5 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/device.h> 11 #include <linux/ethtool.h> 12 #include <linux/io.h> 13 #include <linux/ioport.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/of_net.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/platform_device.h> 19 #include <linux/stmmac.h> 20 21 #include "stmmac_platform.h" 22 23 #define PRG_ETH0 0x0 24 25 #define PRG_ETH0_RGMII_MODE BIT(0) 26 27 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0) 28 #define PRG_ETH0_EXT_RGMII_MODE 1 29 #define PRG_ETH0_EXT_RMII_MODE 4 30 31 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ 32 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) 34 35 #define PRG_ETH0_TXDLY_SHIFT 5 36 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) 37 38 /* divider for the result of m250_sel */ 39 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7 40 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3 41 42 #define PRG_ETH0_RGMII_TX_CLK_EN 10 43 44 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) 45 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) 46 47 #define MUX_CLK_NUM_PARENTS 2 48 49 struct meson8b_dwmac; 50 51 struct meson8b_dwmac_data { 52 int (*set_phy_mode)(struct meson8b_dwmac *dwmac); 53 }; 54 55 struct meson8b_dwmac { 56 struct device *dev; 57 void __iomem *regs; 58 59 const struct meson8b_dwmac_data *data; 60 phy_interface_t phy_mode; 61 struct clk *rgmii_tx_clk; 62 u32 tx_delay_ns; 63 }; 64 65 struct meson8b_dwmac_clk_configs { 66 struct clk_mux m250_mux; 67 struct clk_divider m250_div; 68 struct clk_fixed_factor fixed_div2; 69 struct clk_gate rgmii_tx_en; 70 }; 71 72 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, 73 u32 mask, u32 value) 74 { 75 u32 data; 76 77 data = readl(dwmac->regs + reg); 78 data &= ~mask; 79 data |= (value & mask); 80 81 writel(data, dwmac->regs + reg); 82 } 83 84 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, 85 const char *name_suffix, 86 const char **parent_names, 87 int num_parents, 88 const struct clk_ops *ops, 89 struct clk_hw *hw) 90 { 91 struct clk_init_data init; 92 char clk_name[32]; 93 94 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), 95 name_suffix); 96 97 init.name = clk_name; 98 init.ops = ops; 99 init.flags = CLK_SET_RATE_PARENT; 100 init.parent_names = parent_names; 101 init.num_parents = num_parents; 102 103 hw->init = &init; 104 105 return devm_clk_register(dwmac->dev, hw); 106 } 107 108 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) 109 { 110 int i, ret; 111 struct clk *clk; 112 struct device *dev = dwmac->dev; 113 const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS]; 114 struct meson8b_dwmac_clk_configs *clk_configs; 115 static const struct clk_div_table div_table[] = { 116 { .div = 2, .val = 2, }, 117 { .div = 3, .val = 3, }, 118 { .div = 4, .val = 4, }, 119 { .div = 5, .val = 5, }, 120 { .div = 6, .val = 6, }, 121 { .div = 7, .val = 7, }, 122 }; 123 124 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL); 125 if (!clk_configs) 126 return -ENOMEM; 127 128 /* get the mux parents from DT */ 129 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 130 char name[16]; 131 132 snprintf(name, sizeof(name), "clkin%d", i); 133 clk = devm_clk_get(dev, name); 134 if (IS_ERR(clk)) { 135 ret = PTR_ERR(clk); 136 if (ret != -EPROBE_DEFER) 137 dev_err(dev, "Missing clock %s\n", name); 138 return ret; 139 } 140 141 mux_parent_names[i] = __clk_get_name(clk); 142 } 143 144 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0; 145 clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; 146 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; 147 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names, 148 MUX_CLK_NUM_PARENTS, &clk_mux_ops, 149 &clk_configs->m250_mux.hw); 150 if (WARN_ON(IS_ERR(clk))) 151 return PTR_ERR(clk); 152 153 parent_name = __clk_get_name(clk); 154 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0; 155 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; 156 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; 157 clk_configs->m250_div.table = div_table; 158 clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO | 159 CLK_DIVIDER_ROUND_CLOSEST; 160 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1, 161 &clk_divider_ops, 162 &clk_configs->m250_div.hw); 163 if (WARN_ON(IS_ERR(clk))) 164 return PTR_ERR(clk); 165 166 parent_name = __clk_get_name(clk); 167 clk_configs->fixed_div2.mult = 1; 168 clk_configs->fixed_div2.div = 2; 169 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1, 170 &clk_fixed_factor_ops, 171 &clk_configs->fixed_div2.hw); 172 if (WARN_ON(IS_ERR(clk))) 173 return PTR_ERR(clk); 174 175 parent_name = __clk_get_name(clk); 176 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0; 177 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN; 178 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1, 179 &clk_gate_ops, 180 &clk_configs->rgmii_tx_en.hw); 181 if (WARN_ON(IS_ERR(clk))) 182 return PTR_ERR(clk); 183 184 dwmac->rgmii_tx_clk = clk; 185 186 return 0; 187 } 188 189 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac) 190 { 191 switch (dwmac->phy_mode) { 192 case PHY_INTERFACE_MODE_RGMII: 193 case PHY_INTERFACE_MODE_RGMII_RXID: 194 case PHY_INTERFACE_MODE_RGMII_ID: 195 case PHY_INTERFACE_MODE_RGMII_TXID: 196 /* enable RGMII mode */ 197 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 198 PRG_ETH0_RGMII_MODE, 199 PRG_ETH0_RGMII_MODE); 200 break; 201 case PHY_INTERFACE_MODE_RMII: 202 /* disable RGMII mode -> enables RMII mode */ 203 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 204 PRG_ETH0_RGMII_MODE, 0); 205 break; 206 default: 207 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 208 phy_modes(dwmac->phy_mode)); 209 return -EINVAL; 210 } 211 212 return 0; 213 } 214 215 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) 216 { 217 switch (dwmac->phy_mode) { 218 case PHY_INTERFACE_MODE_RGMII: 219 case PHY_INTERFACE_MODE_RGMII_RXID: 220 case PHY_INTERFACE_MODE_RGMII_ID: 221 case PHY_INTERFACE_MODE_RGMII_TXID: 222 /* enable RGMII mode */ 223 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 224 PRG_ETH0_EXT_PHY_MODE_MASK, 225 PRG_ETH0_EXT_RGMII_MODE); 226 break; 227 case PHY_INTERFACE_MODE_RMII: 228 /* disable RGMII mode -> enables RMII mode */ 229 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 230 PRG_ETH0_EXT_PHY_MODE_MASK, 231 PRG_ETH0_EXT_RMII_MODE); 232 break; 233 default: 234 dev_err(dwmac->dev, "fail to set phy-mode %s\n", 235 phy_modes(dwmac->phy_mode)); 236 return -EINVAL; 237 } 238 239 return 0; 240 } 241 242 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) 243 { 244 int ret; 245 u8 tx_dly_val = 0; 246 247 switch (dwmac->phy_mode) { 248 case PHY_INTERFACE_MODE_RGMII: 249 case PHY_INTERFACE_MODE_RGMII_RXID: 250 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 251 * 8ns are exactly one cycle of the 125MHz RGMII TX clock): 252 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 253 */ 254 tx_dly_val = dwmac->tx_delay_ns >> 1; 255 /* fall through */ 256 257 case PHY_INTERFACE_MODE_RGMII_ID: 258 case PHY_INTERFACE_MODE_RGMII_TXID: 259 /* only relevant for RMII mode -> disable in RGMII mode */ 260 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 261 PRG_ETH0_INVERTED_RMII_CLK, 0); 262 263 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, 264 tx_dly_val << PRG_ETH0_TXDLY_SHIFT); 265 266 /* Configure the 125MHz RGMII TX clock, the IP block changes 267 * the output automatically (= without us having to configure 268 * a register) based on the line-speed (125MHz for Gbit speeds, 269 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). 270 */ 271 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); 272 if (ret) { 273 dev_err(dwmac->dev, 274 "failed to set RGMII TX clock\n"); 275 return ret; 276 } 277 278 ret = clk_prepare_enable(dwmac->rgmii_tx_clk); 279 if (ret) { 280 dev_err(dwmac->dev, 281 "failed to enable the RGMII TX clock\n"); 282 return ret; 283 } 284 285 devm_add_action_or_reset(dwmac->dev, 286 (void(*)(void *))clk_disable_unprepare, 287 dwmac->rgmii_tx_clk); 288 break; 289 290 case PHY_INTERFACE_MODE_RMII: 291 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ 292 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, 293 PRG_ETH0_INVERTED_RMII_CLK, 294 PRG_ETH0_INVERTED_RMII_CLK); 295 296 /* TX clock delay cannot be configured in RMII mode */ 297 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, 298 0); 299 300 break; 301 302 default: 303 dev_err(dwmac->dev, "unsupported phy-mode %s\n", 304 phy_modes(dwmac->phy_mode)); 305 return -EINVAL; 306 } 307 308 /* enable TX_CLK and PHY_REF_CLK generator */ 309 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, 310 PRG_ETH0_TX_AND_PHY_REF_CLK); 311 312 return 0; 313 } 314 315 static int meson8b_dwmac_probe(struct platform_device *pdev) 316 { 317 struct plat_stmmacenet_data *plat_dat; 318 struct stmmac_resources stmmac_res; 319 struct meson8b_dwmac *dwmac; 320 int ret; 321 322 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 323 if (ret) 324 return ret; 325 326 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 327 if (IS_ERR(plat_dat)) 328 return PTR_ERR(plat_dat); 329 330 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 331 if (!dwmac) { 332 ret = -ENOMEM; 333 goto err_remove_config_dt; 334 } 335 336 dwmac->data = (const struct meson8b_dwmac_data *) 337 of_device_get_match_data(&pdev->dev); 338 if (!dwmac->data) { 339 ret = -EINVAL; 340 goto err_remove_config_dt; 341 } 342 dwmac->regs = devm_platform_ioremap_resource(pdev, 1); 343 if (IS_ERR(dwmac->regs)) { 344 ret = PTR_ERR(dwmac->regs); 345 goto err_remove_config_dt; 346 } 347 348 dwmac->dev = &pdev->dev; 349 ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode); 350 if (ret) { 351 dev_err(&pdev->dev, "missing phy-mode property\n"); 352 goto err_remove_config_dt; 353 } 354 355 /* use 2ns as fallback since this value was previously hardcoded */ 356 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns", 357 &dwmac->tx_delay_ns)) 358 dwmac->tx_delay_ns = 2; 359 360 ret = meson8b_init_rgmii_tx_clk(dwmac); 361 if (ret) 362 goto err_remove_config_dt; 363 364 ret = dwmac->data->set_phy_mode(dwmac); 365 if (ret) 366 goto err_remove_config_dt; 367 368 ret = meson8b_init_prg_eth(dwmac); 369 if (ret) 370 goto err_remove_config_dt; 371 372 plat_dat->bsp_priv = dwmac; 373 374 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 375 if (ret) 376 goto err_remove_config_dt; 377 378 return 0; 379 380 err_remove_config_dt: 381 stmmac_remove_config_dt(pdev, plat_dat); 382 383 return ret; 384 } 385 386 static const struct meson8b_dwmac_data meson8b_dwmac_data = { 387 .set_phy_mode = meson8b_set_phy_mode, 388 }; 389 390 static const struct meson8b_dwmac_data meson_axg_dwmac_data = { 391 .set_phy_mode = meson_axg_set_phy_mode, 392 }; 393 394 static const struct of_device_id meson8b_dwmac_match[] = { 395 { 396 .compatible = "amlogic,meson8b-dwmac", 397 .data = &meson8b_dwmac_data, 398 }, 399 { 400 .compatible = "amlogic,meson8m2-dwmac", 401 .data = &meson8b_dwmac_data, 402 }, 403 { 404 .compatible = "amlogic,meson-gxbb-dwmac", 405 .data = &meson8b_dwmac_data, 406 }, 407 { 408 .compatible = "amlogic,meson-axg-dwmac", 409 .data = &meson_axg_dwmac_data, 410 }, 411 { } 412 }; 413 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); 414 415 static struct platform_driver meson8b_dwmac_driver = { 416 .probe = meson8b_dwmac_probe, 417 .remove = stmmac_pltfr_remove, 418 .driver = { 419 .name = "meson8b-dwmac", 420 .pm = &stmmac_pltfr_pm_ops, 421 .of_match_table = meson8b_dwmac_match, 422 }, 423 }; 424 module_platform_driver(meson8b_dwmac_driver); 425 426 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 427 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer"); 428 MODULE_LICENSE("GPL v2"); 429