1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 MediaTek Inc. 4 */ 5 #include <linux/bitfield.h> 6 #include <linux/io.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/of_net.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/stmmac.h> 15 16 #include "stmmac.h" 17 #include "stmmac_platform.h" 18 19 /* Peri Configuration register for mt2712 */ 20 #define PERI_ETH_PHY_INTF_SEL 0x418 21 #define PHY_INTF_MII 0 22 #define PHY_INTF_RGMII 1 23 #define PHY_INTF_RMII 4 24 #define RMII_CLK_SRC_RXC BIT(4) 25 #define RMII_CLK_SRC_INTERNAL BIT(5) 26 27 #define PERI_ETH_DLY 0x428 28 #define ETH_DLY_GTXC_INV BIT(6) 29 #define ETH_DLY_GTXC_ENABLE BIT(5) 30 #define ETH_DLY_GTXC_STAGES GENMASK(4, 0) 31 #define ETH_DLY_TXC_INV BIT(20) 32 #define ETH_DLY_TXC_ENABLE BIT(19) 33 #define ETH_DLY_TXC_STAGES GENMASK(18, 14) 34 #define ETH_DLY_RXC_INV BIT(13) 35 #define ETH_DLY_RXC_ENABLE BIT(12) 36 #define ETH_DLY_RXC_STAGES GENMASK(11, 7) 37 38 #define PERI_ETH_DLY_FINE 0x800 39 #define ETH_RMII_DLY_TX_INV BIT(2) 40 #define ETH_FINE_DLY_GTXC BIT(1) 41 #define ETH_FINE_DLY_RXC BIT(0) 42 43 struct mac_delay_struct { 44 u32 tx_delay; 45 u32 rx_delay; 46 bool tx_inv; 47 bool rx_inv; 48 }; 49 50 struct mediatek_dwmac_plat_data { 51 const struct mediatek_dwmac_variant *variant; 52 struct mac_delay_struct mac_delay; 53 struct clk_bulk_data *clks; 54 struct device_node *np; 55 struct regmap *peri_regmap; 56 struct device *dev; 57 phy_interface_t phy_mode; 58 bool rmii_rxc; 59 }; 60 61 struct mediatek_dwmac_variant { 62 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat); 63 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat); 64 65 /* clock ids to be requested */ 66 const char * const *clk_list; 67 int num_clks; 68 69 u32 dma_bit_mask; 70 u32 rx_delay_max; 71 u32 tx_delay_max; 72 }; 73 74 /* list of clocks required for mac */ 75 static const char * const mt2712_dwmac_clk_l[] = { 76 "axi", "apb", "mac_main", "ptp_ref" 77 }; 78 79 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat) 80 { 81 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; 82 u32 intf_val = 0; 83 84 /* select phy interface in top control domain */ 85 switch (plat->phy_mode) { 86 case PHY_INTERFACE_MODE_MII: 87 intf_val |= PHY_INTF_MII; 88 break; 89 case PHY_INTERFACE_MODE_RMII: 90 intf_val |= (PHY_INTF_RMII | rmii_rxc); 91 break; 92 case PHY_INTERFACE_MODE_RGMII: 93 case PHY_INTERFACE_MODE_RGMII_TXID: 94 case PHY_INTERFACE_MODE_RGMII_RXID: 95 case PHY_INTERFACE_MODE_RGMII_ID: 96 intf_val |= PHY_INTF_RGMII; 97 break; 98 default: 99 dev_err(plat->dev, "phy interface not supported\n"); 100 return -EINVAL; 101 } 102 103 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); 104 105 return 0; 106 } 107 108 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) 109 { 110 struct mac_delay_struct *mac_delay = &plat->mac_delay; 111 112 switch (plat->phy_mode) { 113 case PHY_INTERFACE_MODE_MII: 114 case PHY_INTERFACE_MODE_RMII: 115 /* 550ps per stage for MII/RMII */ 116 mac_delay->tx_delay /= 550; 117 mac_delay->rx_delay /= 550; 118 break; 119 case PHY_INTERFACE_MODE_RGMII: 120 case PHY_INTERFACE_MODE_RGMII_TXID: 121 case PHY_INTERFACE_MODE_RGMII_RXID: 122 case PHY_INTERFACE_MODE_RGMII_ID: 123 /* 170ps per stage for RGMII */ 124 mac_delay->tx_delay /= 170; 125 mac_delay->rx_delay /= 170; 126 break; 127 default: 128 dev_err(plat->dev, "phy interface not supported\n"); 129 break; 130 } 131 } 132 133 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) 134 { 135 struct mac_delay_struct *mac_delay = &plat->mac_delay; 136 137 switch (plat->phy_mode) { 138 case PHY_INTERFACE_MODE_MII: 139 case PHY_INTERFACE_MODE_RMII: 140 /* 550ps per stage for MII/RMII */ 141 mac_delay->tx_delay *= 550; 142 mac_delay->rx_delay *= 550; 143 break; 144 case PHY_INTERFACE_MODE_RGMII: 145 case PHY_INTERFACE_MODE_RGMII_TXID: 146 case PHY_INTERFACE_MODE_RGMII_RXID: 147 case PHY_INTERFACE_MODE_RGMII_ID: 148 /* 170ps per stage for RGMII */ 149 mac_delay->tx_delay *= 170; 150 mac_delay->rx_delay *= 170; 151 break; 152 default: 153 dev_err(plat->dev, "phy interface not supported\n"); 154 break; 155 } 156 } 157 158 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) 159 { 160 struct mac_delay_struct *mac_delay = &plat->mac_delay; 161 u32 delay_val = 0, fine_val = 0; 162 163 mt2712_delay_ps2stage(plat); 164 165 switch (plat->phy_mode) { 166 case PHY_INTERFACE_MODE_MII: 167 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); 168 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); 169 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); 170 171 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 172 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 173 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 174 break; 175 case PHY_INTERFACE_MODE_RMII: 176 /* the rmii reference clock is from external phy, 177 * and the property "rmii_rxc" indicates which pin(TXC/RXC) 178 * the reference clk is connected to. The reference clock is a 179 * received signal, so rx_delay/rx_inv are used to indicate 180 * the reference clock timing adjustment 181 */ 182 if (plat->rmii_rxc) { 183 /* the rmii reference clock from outside is connected 184 * to RXC pin, the reference clock will be adjusted 185 * by RXC delay macro circuit. 186 */ 187 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 188 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 189 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 190 } else { 191 /* the rmii reference clock from outside is connected 192 * to TXC pin, the reference clock will be adjusted 193 * by TXC delay macro circuit. 194 */ 195 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); 196 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); 197 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); 198 } 199 /* tx_inv will inverse the tx clock inside mac relateive to 200 * reference clock from external phy, 201 * and this bit is located in the same register with fine-tune 202 */ 203 if (mac_delay->tx_inv) 204 fine_val = ETH_RMII_DLY_TX_INV; 205 break; 206 case PHY_INTERFACE_MODE_RGMII: 207 case PHY_INTERFACE_MODE_RGMII_TXID: 208 case PHY_INTERFACE_MODE_RGMII_RXID: 209 case PHY_INTERFACE_MODE_RGMII_ID: 210 fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC; 211 212 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); 213 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); 214 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); 215 216 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 217 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 218 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 219 break; 220 default: 221 dev_err(plat->dev, "phy interface not supported\n"); 222 return -EINVAL; 223 } 224 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); 225 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); 226 227 mt2712_delay_stage2ps(plat); 228 229 return 0; 230 } 231 232 static const struct mediatek_dwmac_variant mt2712_gmac_variant = { 233 .dwmac_set_phy_interface = mt2712_set_interface, 234 .dwmac_set_delay = mt2712_set_delay, 235 .clk_list = mt2712_dwmac_clk_l, 236 .num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l), 237 .dma_bit_mask = 33, 238 .rx_delay_max = 17600, 239 .tx_delay_max = 17600, 240 }; 241 242 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) 243 { 244 struct mac_delay_struct *mac_delay = &plat->mac_delay; 245 u32 tx_delay_ps, rx_delay_ps; 246 int err; 247 248 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg"); 249 if (IS_ERR(plat->peri_regmap)) { 250 dev_err(plat->dev, "Failed to get pericfg syscon\n"); 251 return PTR_ERR(plat->peri_regmap); 252 } 253 254 err = of_get_phy_mode(plat->np, &plat->phy_mode); 255 if (err) { 256 dev_err(plat->dev, "not find phy-mode\n"); 257 return err; 258 } 259 260 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) { 261 if (tx_delay_ps < plat->variant->tx_delay_max) { 262 mac_delay->tx_delay = tx_delay_ps; 263 } else { 264 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); 265 return -EINVAL; 266 } 267 } 268 269 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) { 270 if (rx_delay_ps < plat->variant->rx_delay_max) { 271 mac_delay->rx_delay = rx_delay_ps; 272 } else { 273 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); 274 return -EINVAL; 275 } 276 } 277 278 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); 279 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); 280 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); 281 282 return 0; 283 } 284 285 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat) 286 { 287 const struct mediatek_dwmac_variant *variant = plat->variant; 288 int i, num = variant->num_clks; 289 290 plat->clks = devm_kcalloc(plat->dev, num, sizeof(*plat->clks), GFP_KERNEL); 291 if (!plat->clks) 292 return -ENOMEM; 293 294 for (i = 0; i < num; i++) 295 plat->clks[i].id = variant->clk_list[i]; 296 297 return devm_clk_bulk_get(plat->dev, num, plat->clks); 298 } 299 300 static int mediatek_dwmac_init(struct platform_device *pdev, void *priv) 301 { 302 struct mediatek_dwmac_plat_data *plat = priv; 303 const struct mediatek_dwmac_variant *variant = plat->variant; 304 int ret; 305 306 ret = dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bit_mask)); 307 if (ret) { 308 dev_err(plat->dev, "No suitable DMA available, err = %d\n", ret); 309 return ret; 310 } 311 312 ret = variant->dwmac_set_phy_interface(plat); 313 if (ret) { 314 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret); 315 return ret; 316 } 317 318 ret = variant->dwmac_set_delay(plat); 319 if (ret) { 320 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret); 321 return ret; 322 } 323 324 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks); 325 if (ret) { 326 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); 327 return ret; 328 } 329 330 pm_runtime_enable(&pdev->dev); 331 pm_runtime_get_sync(&pdev->dev); 332 333 return 0; 334 } 335 336 static void mediatek_dwmac_exit(struct platform_device *pdev, void *priv) 337 { 338 struct mediatek_dwmac_plat_data *plat = priv; 339 const struct mediatek_dwmac_variant *variant = plat->variant; 340 341 clk_bulk_disable_unprepare(variant->num_clks, plat->clks); 342 343 pm_runtime_put_sync(&pdev->dev); 344 pm_runtime_disable(&pdev->dev); 345 } 346 347 static int mediatek_dwmac_probe(struct platform_device *pdev) 348 { 349 struct mediatek_dwmac_plat_data *priv_plat; 350 struct plat_stmmacenet_data *plat_dat; 351 struct stmmac_resources stmmac_res; 352 int ret; 353 354 priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL); 355 if (!priv_plat) 356 return -ENOMEM; 357 358 priv_plat->variant = of_device_get_match_data(&pdev->dev); 359 if (!priv_plat->variant) { 360 dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n"); 361 return -EINVAL; 362 } 363 364 priv_plat->dev = &pdev->dev; 365 priv_plat->np = pdev->dev.of_node; 366 367 ret = mediatek_dwmac_config_dt(priv_plat); 368 if (ret) 369 return ret; 370 371 ret = mediatek_dwmac_clk_init(priv_plat); 372 if (ret) 373 return ret; 374 375 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 376 if (ret) 377 return ret; 378 379 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 380 if (IS_ERR(plat_dat)) 381 return PTR_ERR(plat_dat); 382 383 plat_dat->interface = priv_plat->phy_mode; 384 plat_dat->has_gmac4 = 1; 385 plat_dat->has_gmac = 0; 386 plat_dat->pmt = 0; 387 plat_dat->riwt_off = 1; 388 plat_dat->maxmtu = ETH_DATA_LEN; 389 plat_dat->bsp_priv = priv_plat; 390 plat_dat->init = mediatek_dwmac_init; 391 plat_dat->exit = mediatek_dwmac_exit; 392 mediatek_dwmac_init(pdev, priv_plat); 393 394 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 395 if (ret) { 396 stmmac_remove_config_dt(pdev, plat_dat); 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static const struct of_device_id mediatek_dwmac_match[] = { 404 { .compatible = "mediatek,mt2712-gmac", 405 .data = &mt2712_gmac_variant }, 406 { } 407 }; 408 409 MODULE_DEVICE_TABLE(of, mediatek_dwmac_match); 410 411 static struct platform_driver mediatek_dwmac_driver = { 412 .probe = mediatek_dwmac_probe, 413 .remove = stmmac_pltfr_remove, 414 .driver = { 415 .name = "dwmac-mediatek", 416 .pm = &stmmac_pltfr_pm_ops, 417 .of_match_table = mediatek_dwmac_match, 418 }, 419 }; 420 module_platform_driver(mediatek_dwmac_driver); 421 422 MODULE_AUTHOR("Biao Huang <biao.huang@mediatek.com>"); 423 MODULE_DESCRIPTION("MediaTek DWMAC specific glue layer"); 424 MODULE_LICENSE("GPL v2"); 425