1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018 MediaTek Inc.
4  */
5 #include <linux/bitfield.h>
6 #include <linux/io.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/of_net.h>
12 #include <linux/regmap.h>
13 #include <linux/stmmac.h>
14 
15 #include "stmmac.h"
16 #include "stmmac_platform.h"
17 
18 /* Peri Configuration register for mt2712 */
19 #define PERI_ETH_PHY_INTF_SEL	0x418
20 #define PHY_INTF_MII		0
21 #define PHY_INTF_RGMII		1
22 #define PHY_INTF_RMII		4
23 #define RMII_CLK_SRC_RXC	BIT(4)
24 #define RMII_CLK_SRC_INTERNAL	BIT(5)
25 
26 #define PERI_ETH_DLY	0x428
27 #define ETH_DLY_GTXC_INV	BIT(6)
28 #define ETH_DLY_GTXC_ENABLE	BIT(5)
29 #define ETH_DLY_GTXC_STAGES	GENMASK(4, 0)
30 #define ETH_DLY_TXC_INV		BIT(20)
31 #define ETH_DLY_TXC_ENABLE	BIT(19)
32 #define ETH_DLY_TXC_STAGES	GENMASK(18, 14)
33 #define ETH_DLY_RXC_INV		BIT(13)
34 #define ETH_DLY_RXC_ENABLE	BIT(12)
35 #define ETH_DLY_RXC_STAGES	GENMASK(11, 7)
36 
37 #define PERI_ETH_DLY_FINE	0x800
38 #define ETH_RMII_DLY_TX_INV	BIT(2)
39 #define ETH_FINE_DLY_GTXC	BIT(1)
40 #define ETH_FINE_DLY_RXC	BIT(0)
41 
42 /* Peri Configuration register for mt8195 */
43 #define MT8195_PERI_ETH_CTRL0		0xFD0
44 #define MT8195_RMII_CLK_SRC_INTERNAL	BIT(28)
45 #define MT8195_RMII_CLK_SRC_RXC		BIT(27)
46 #define MT8195_ETH_INTF_SEL		GENMASK(26, 24)
47 #define MT8195_RGMII_TXC_PHASE_CTRL	BIT(22)
48 #define MT8195_EXT_PHY_MODE		BIT(21)
49 #define MT8195_DLY_GTXC_INV		BIT(12)
50 #define MT8195_DLY_GTXC_ENABLE		BIT(5)
51 #define MT8195_DLY_GTXC_STAGES		GENMASK(4, 0)
52 
53 #define MT8195_PERI_ETH_CTRL1		0xFD4
54 #define MT8195_DLY_RXC_INV		BIT(25)
55 #define MT8195_DLY_RXC_ENABLE		BIT(18)
56 #define MT8195_DLY_RXC_STAGES		GENMASK(17, 13)
57 #define MT8195_DLY_TXC_INV		BIT(12)
58 #define MT8195_DLY_TXC_ENABLE		BIT(5)
59 #define MT8195_DLY_TXC_STAGES		GENMASK(4, 0)
60 
61 #define MT8195_PERI_ETH_CTRL2		0xFD8
62 #define MT8195_DLY_RMII_RXC_INV		BIT(25)
63 #define MT8195_DLY_RMII_RXC_ENABLE	BIT(18)
64 #define MT8195_DLY_RMII_RXC_STAGES	GENMASK(17, 13)
65 #define MT8195_DLY_RMII_TXC_INV		BIT(12)
66 #define MT8195_DLY_RMII_TXC_ENABLE	BIT(5)
67 #define MT8195_DLY_RMII_TXC_STAGES	GENMASK(4, 0)
68 
69 struct mac_delay_struct {
70 	u32 tx_delay;
71 	u32 rx_delay;
72 	bool tx_inv;
73 	bool rx_inv;
74 };
75 
76 struct mediatek_dwmac_plat_data {
77 	const struct mediatek_dwmac_variant *variant;
78 	struct mac_delay_struct mac_delay;
79 	struct clk *rmii_internal_clk;
80 	struct clk_bulk_data *clks;
81 	struct regmap *peri_regmap;
82 	struct device_node *np;
83 	struct device *dev;
84 	phy_interface_t phy_mode;
85 	bool rmii_clk_from_mac;
86 	bool rmii_rxc;
87 	bool mac_wol;
88 };
89 
90 struct mediatek_dwmac_variant {
91 	int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
92 	int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
93 	void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed);
94 
95 	/* clock ids to be requested */
96 	const char * const *clk_list;
97 	int num_clks;
98 
99 	u32 dma_bit_mask;
100 	u32 rx_delay_max;
101 	u32 tx_delay_max;
102 };
103 
104 /* list of clocks required for mac */
105 static const char * const mt2712_dwmac_clk_l[] = {
106 	"axi", "apb", "mac_main", "ptp_ref"
107 };
108 
109 static const char * const mt8195_dwmac_clk_l[] = {
110 	"axi", "apb", "mac_cg", "mac_main", "ptp_ref"
111 };
112 
113 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
114 {
115 	int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
116 	int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
117 	u32 intf_val = 0;
118 
119 	/* select phy interface in top control domain */
120 	switch (plat->phy_mode) {
121 	case PHY_INTERFACE_MODE_MII:
122 		intf_val |= PHY_INTF_MII;
123 		break;
124 	case PHY_INTERFACE_MODE_RMII:
125 		intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
126 		break;
127 	case PHY_INTERFACE_MODE_RGMII:
128 	case PHY_INTERFACE_MODE_RGMII_TXID:
129 	case PHY_INTERFACE_MODE_RGMII_RXID:
130 	case PHY_INTERFACE_MODE_RGMII_ID:
131 		intf_val |= PHY_INTF_RGMII;
132 		break;
133 	default:
134 		dev_err(plat->dev, "phy interface not supported\n");
135 		return -EINVAL;
136 	}
137 
138 	regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
139 
140 	return 0;
141 }
142 
143 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
144 {
145 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
146 
147 	switch (plat->phy_mode) {
148 	case PHY_INTERFACE_MODE_MII:
149 	case PHY_INTERFACE_MODE_RMII:
150 		/* 550ps per stage for MII/RMII */
151 		mac_delay->tx_delay /= 550;
152 		mac_delay->rx_delay /= 550;
153 		break;
154 	case PHY_INTERFACE_MODE_RGMII:
155 	case PHY_INTERFACE_MODE_RGMII_TXID:
156 	case PHY_INTERFACE_MODE_RGMII_RXID:
157 	case PHY_INTERFACE_MODE_RGMII_ID:
158 		/* 170ps per stage for RGMII */
159 		mac_delay->tx_delay /= 170;
160 		mac_delay->rx_delay /= 170;
161 		break;
162 	default:
163 		dev_err(plat->dev, "phy interface not supported\n");
164 		break;
165 	}
166 }
167 
168 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
169 {
170 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
171 
172 	switch (plat->phy_mode) {
173 	case PHY_INTERFACE_MODE_MII:
174 	case PHY_INTERFACE_MODE_RMII:
175 		/* 550ps per stage for MII/RMII */
176 		mac_delay->tx_delay *= 550;
177 		mac_delay->rx_delay *= 550;
178 		break;
179 	case PHY_INTERFACE_MODE_RGMII:
180 	case PHY_INTERFACE_MODE_RGMII_TXID:
181 	case PHY_INTERFACE_MODE_RGMII_RXID:
182 	case PHY_INTERFACE_MODE_RGMII_ID:
183 		/* 170ps per stage for RGMII */
184 		mac_delay->tx_delay *= 170;
185 		mac_delay->rx_delay *= 170;
186 		break;
187 	default:
188 		dev_err(plat->dev, "phy interface not supported\n");
189 		break;
190 	}
191 }
192 
193 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
194 {
195 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
196 	u32 delay_val = 0, fine_val = 0;
197 
198 	mt2712_delay_ps2stage(plat);
199 
200 	switch (plat->phy_mode) {
201 	case PHY_INTERFACE_MODE_MII:
202 		delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
203 		delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay);
204 		delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv);
205 
206 		delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
207 		delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
208 		delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
209 		break;
210 	case PHY_INTERFACE_MODE_RMII:
211 		if (plat->rmii_clk_from_mac) {
212 			/* case 1: mac provides the rmii reference clock,
213 			 * and the clock output to TXC pin.
214 			 * The egress timing can be adjusted by GTXC delay macro circuit.
215 			 * The ingress timing can be adjusted by TXC delay macro circuit.
216 			 */
217 			delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
218 			delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
219 			delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
220 
221 			delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
222 			delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
223 			delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
224 		} else {
225 			/* case 2: the rmii reference clock is from external phy,
226 			 * and the property "rmii_rxc" indicates which pin(TXC/RXC)
227 			 * the reference clk is connected to. The reference clock is a
228 			 * received signal, so rx_delay/rx_inv are used to indicate
229 			 * the reference clock timing adjustment
230 			 */
231 			if (plat->rmii_rxc) {
232 				/* the rmii reference clock from outside is connected
233 				 * to RXC pin, the reference clock will be adjusted
234 				 * by RXC delay macro circuit.
235 				 */
236 				delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
237 				delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
238 				delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
239 			} else {
240 				/* the rmii reference clock from outside is connected
241 				 * to TXC pin, the reference clock will be adjusted
242 				 * by TXC delay macro circuit.
243 				 */
244 				delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
245 				delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
246 				delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
247 			}
248 			/* tx_inv will inverse the tx clock inside mac relateive to
249 			 * reference clock from external phy,
250 			 * and this bit is located in the same register with fine-tune
251 			 */
252 			if (mac_delay->tx_inv)
253 				fine_val = ETH_RMII_DLY_TX_INV;
254 		}
255 		break;
256 	case PHY_INTERFACE_MODE_RGMII:
257 	case PHY_INTERFACE_MODE_RGMII_TXID:
258 	case PHY_INTERFACE_MODE_RGMII_RXID:
259 	case PHY_INTERFACE_MODE_RGMII_ID:
260 		fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC;
261 
262 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
263 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
264 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
265 
266 		delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
267 		delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
268 		delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
269 		break;
270 	default:
271 		dev_err(plat->dev, "phy interface not supported\n");
272 		return -EINVAL;
273 	}
274 	regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
275 	regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
276 
277 	mt2712_delay_stage2ps(plat);
278 
279 	return 0;
280 }
281 
282 static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
283 		.dwmac_set_phy_interface = mt2712_set_interface,
284 		.dwmac_set_delay = mt2712_set_delay,
285 		.clk_list = mt2712_dwmac_clk_l,
286 		.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
287 		.dma_bit_mask = 33,
288 		.rx_delay_max = 17600,
289 		.tx_delay_max = 17600,
290 };
291 
292 static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
293 {
294 	int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
295 	int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
296 	u32 intf_val = 0;
297 
298 	/* select phy interface in top control domain */
299 	switch (plat->phy_mode) {
300 	case PHY_INTERFACE_MODE_MII:
301 		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII);
302 		break;
303 	case PHY_INTERFACE_MODE_RMII:
304 		intf_val |= (rmii_rxc | rmii_clk_from_mac);
305 		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII);
306 		break;
307 	case PHY_INTERFACE_MODE_RGMII:
308 	case PHY_INTERFACE_MODE_RGMII_TXID:
309 	case PHY_INTERFACE_MODE_RGMII_RXID:
310 	case PHY_INTERFACE_MODE_RGMII_ID:
311 		intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII);
312 		break;
313 	default:
314 		dev_err(plat->dev, "phy interface not supported\n");
315 		return -EINVAL;
316 	}
317 
318 	/* MT8195 only support external PHY */
319 	intf_val |= MT8195_EXT_PHY_MODE;
320 
321 	regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val);
322 
323 	return 0;
324 }
325 
326 static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
327 {
328 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
329 
330 	/* 290ps per stage */
331 	mac_delay->tx_delay /= 290;
332 	mac_delay->rx_delay /= 290;
333 }
334 
335 static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
336 {
337 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
338 
339 	/* 290ps per stage */
340 	mac_delay->tx_delay *= 290;
341 	mac_delay->rx_delay *= 290;
342 }
343 
344 static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
345 {
346 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
347 	u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;
348 
349 	mt8195_delay_ps2stage(plat);
350 
351 	switch (plat->phy_mode) {
352 	case PHY_INTERFACE_MODE_MII:
353 		delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
354 		delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay);
355 		delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv);
356 
357 		delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
358 		delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
359 		delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
360 		break;
361 	case PHY_INTERFACE_MODE_RMII:
362 		if (plat->rmii_clk_from_mac) {
363 			/* case 1: mac provides the rmii reference clock,
364 			 * and the clock output to TXC pin.
365 			 * The egress timing can be adjusted by RMII_TXC delay macro circuit.
366 			 * The ingress timing can be adjusted by RMII_RXC delay macro circuit.
367 			 */
368 			rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE,
369 						     !!mac_delay->tx_delay);
370 			rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES,
371 						     mac_delay->tx_delay);
372 			rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_INV,
373 						     mac_delay->tx_inv);
374 
375 			rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE,
376 						     !!mac_delay->rx_delay);
377 			rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_STAGES,
378 						     mac_delay->rx_delay);
379 			rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_INV,
380 						     mac_delay->rx_inv);
381 		} else {
382 			/* case 2: the rmii reference clock is from external phy,
383 			 * and the property "rmii_rxc" indicates which pin(TXC/RXC)
384 			 * the reference clk is connected to. The reference clock is a
385 			 * received signal, so rx_delay/rx_inv are used to indicate
386 			 * the reference clock timing adjustment
387 			 */
388 			if (plat->rmii_rxc) {
389 				/* the rmii reference clock from outside is connected
390 				 * to RXC pin, the reference clock will be adjusted
391 				 * by RXC delay macro circuit.
392 				 */
393 				delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE,
394 							!!mac_delay->rx_delay);
395 				delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES,
396 							mac_delay->rx_delay);
397 				delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV,
398 							mac_delay->rx_inv);
399 			} else {
400 				/* the rmii reference clock from outside is connected
401 				 * to TXC pin, the reference clock will be adjusted
402 				 * by TXC delay macro circuit.
403 				 */
404 				delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE,
405 							!!mac_delay->rx_delay);
406 				delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES,
407 							mac_delay->rx_delay);
408 				delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV,
409 							mac_delay->rx_inv);
410 			}
411 		}
412 		break;
413 	case PHY_INTERFACE_MODE_RGMII:
414 	case PHY_INTERFACE_MODE_RGMII_TXID:
415 	case PHY_INTERFACE_MODE_RGMII_RXID:
416 	case PHY_INTERFACE_MODE_RGMII_ID:
417 		gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
418 		gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay);
419 		gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv);
420 
421 		delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
422 		delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
423 		delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
424 
425 		break;
426 	default:
427 		dev_err(plat->dev, "phy interface not supported\n");
428 		return -EINVAL;
429 	}
430 
431 	regmap_update_bits(plat->peri_regmap,
432 			   MT8195_PERI_ETH_CTRL0,
433 			   MT8195_RGMII_TXC_PHASE_CTRL |
434 			   MT8195_DLY_GTXC_INV |
435 			   MT8195_DLY_GTXC_ENABLE |
436 			   MT8195_DLY_GTXC_STAGES,
437 			   gtxc_delay_val);
438 	regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val);
439 	regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);
440 
441 	mt8195_delay_stage2ps(plat);
442 
443 	return 0;
444 }
445 
446 static void mt8195_fix_mac_speed(void *priv, unsigned int speed)
447 {
448 	struct mediatek_dwmac_plat_data *priv_plat = priv;
449 
450 	if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) {
451 		/* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL,
452 		 * when link speed is 1Gbps with RGMII interface,
453 		 * Fall back to delay macro circuit for 10/100Mbps link speed.
454 		 */
455 		if (speed == SPEED_1000)
456 			regmap_update_bits(priv_plat->peri_regmap,
457 					   MT8195_PERI_ETH_CTRL0,
458 					   MT8195_RGMII_TXC_PHASE_CTRL |
459 					   MT8195_DLY_GTXC_ENABLE |
460 					   MT8195_DLY_GTXC_INV |
461 					   MT8195_DLY_GTXC_STAGES,
462 					   MT8195_RGMII_TXC_PHASE_CTRL);
463 		else
464 			mt8195_set_delay(priv_plat);
465 	}
466 }
467 
468 static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
469 	.dwmac_set_phy_interface = mt8195_set_interface,
470 	.dwmac_set_delay = mt8195_set_delay,
471 	.dwmac_fix_mac_speed = mt8195_fix_mac_speed,
472 	.clk_list = mt8195_dwmac_clk_l,
473 	.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
474 	.dma_bit_mask = 35,
475 	.rx_delay_max = 9280,
476 	.tx_delay_max = 9280,
477 };
478 
479 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
480 {
481 	struct mac_delay_struct *mac_delay = &plat->mac_delay;
482 	u32 tx_delay_ps, rx_delay_ps;
483 	int err;
484 
485 	plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");
486 	if (IS_ERR(plat->peri_regmap)) {
487 		dev_err(plat->dev, "Failed to get pericfg syscon\n");
488 		return PTR_ERR(plat->peri_regmap);
489 	}
490 
491 	err = of_get_phy_mode(plat->np, &plat->phy_mode);
492 	if (err) {
493 		dev_err(plat->dev, "not find phy-mode\n");
494 		return err;
495 	}
496 
497 	if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {
498 		if (tx_delay_ps < plat->variant->tx_delay_max) {
499 			mac_delay->tx_delay = tx_delay_ps;
500 		} else {
501 			dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
502 			return -EINVAL;
503 		}
504 	}
505 
506 	if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {
507 		if (rx_delay_ps < plat->variant->rx_delay_max) {
508 			mac_delay->rx_delay = rx_delay_ps;
509 		} else {
510 			dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
511 			return -EINVAL;
512 		}
513 	}
514 
515 	mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
516 	mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
517 	plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
518 	plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
519 	plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol");
520 
521 	return 0;
522 }
523 
524 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
525 {
526 	const struct mediatek_dwmac_variant *variant = plat->variant;
527 	int i, ret;
528 
529 	plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL);
530 	if (!plat->clks)
531 		return -ENOMEM;
532 
533 	for (i = 0; i < variant->num_clks; i++)
534 		plat->clks[i].id = variant->clk_list[i];
535 
536 	ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks);
537 	if (ret)
538 		return ret;
539 
540 	/* The clock labeled as "rmii_internal" is needed only in RMII(when
541 	 * MAC provides the reference clock), and useless for RGMII/MII or
542 	 * RMII(when PHY provides the reference clock).
543 	 * So, "rmii_internal" clock is got and configured only when
544 	 * reference clock of RMII is from MAC.
545 	 */
546 	if (plat->rmii_clk_from_mac) {
547 		plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal");
548 		if (IS_ERR(plat->rmii_internal_clk))
549 			ret = PTR_ERR(plat->rmii_internal_clk);
550 	} else {
551 		plat->rmii_internal_clk = NULL;
552 	}
553 
554 	return ret;
555 }
556 
557 static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
558 {
559 	struct mediatek_dwmac_plat_data *plat = priv;
560 	const struct mediatek_dwmac_variant *variant = plat->variant;
561 	int ret;
562 
563 	if (variant->dwmac_set_phy_interface) {
564 		ret = variant->dwmac_set_phy_interface(plat);
565 		if (ret) {
566 			dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
567 			return ret;
568 		}
569 	}
570 
571 	if (variant->dwmac_set_delay) {
572 		ret = variant->dwmac_set_delay(plat);
573 		if (ret) {
574 			dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
575 			return ret;
576 		}
577 	}
578 
579 	return 0;
580 }
581 
582 static int mediatek_dwmac_clks_config(void *priv, bool enabled)
583 {
584 	struct mediatek_dwmac_plat_data *plat = priv;
585 	const struct mediatek_dwmac_variant *variant = plat->variant;
586 	int ret = 0;
587 
588 	if (enabled) {
589 		ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
590 		if (ret) {
591 			dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
592 			return ret;
593 		}
594 
595 		ret = clk_prepare_enable(plat->rmii_internal_clk);
596 		if (ret) {
597 			dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret);
598 			return ret;
599 		}
600 	} else {
601 		clk_disable_unprepare(plat->rmii_internal_clk);
602 		clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
603 	}
604 
605 	return ret;
606 }
607 
608 static int mediatek_dwmac_common_data(struct platform_device *pdev,
609 				      struct plat_stmmacenet_data *plat,
610 				      struct mediatek_dwmac_plat_data *priv_plat)
611 {
612 	int i;
613 
614 	plat->interface = priv_plat->phy_mode;
615 	plat->use_phy_wol = priv_plat->mac_wol ? 0 : 1;
616 	plat->riwt_off = 1;
617 	plat->maxmtu = ETH_DATA_LEN;
618 	plat->addr64 = priv_plat->variant->dma_bit_mask;
619 	plat->bsp_priv = priv_plat;
620 	plat->init = mediatek_dwmac_init;
621 	plat->clks_config = mediatek_dwmac_clks_config;
622 	if (priv_plat->variant->dwmac_fix_mac_speed)
623 		plat->fix_mac_speed = priv_plat->variant->dwmac_fix_mac_speed;
624 
625 	plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
626 					     sizeof(*plat->safety_feat_cfg),
627 					     GFP_KERNEL);
628 	if (!plat->safety_feat_cfg)
629 		return -ENOMEM;
630 
631 	plat->safety_feat_cfg->tsoee = 1;
632 	plat->safety_feat_cfg->mrxpee = 0;
633 	plat->safety_feat_cfg->mestee = 1;
634 	plat->safety_feat_cfg->mrxee = 1;
635 	plat->safety_feat_cfg->mtxee = 1;
636 	plat->safety_feat_cfg->epsi = 0;
637 	plat->safety_feat_cfg->edpp = 1;
638 	plat->safety_feat_cfg->prtyen = 1;
639 	plat->safety_feat_cfg->tmouten = 1;
640 
641 	for (i = 0; i < plat->tx_queues_to_use; i++) {
642 		/* Default TX Q0 to use TSO and rest TXQ for TBS */
643 		if (i > 0)
644 			plat->tx_queues_cfg[i].tbs_en = 1;
645 	}
646 
647 	return 0;
648 }
649 
650 static int mediatek_dwmac_probe(struct platform_device *pdev)
651 {
652 	struct mediatek_dwmac_plat_data *priv_plat;
653 	struct plat_stmmacenet_data *plat_dat;
654 	struct stmmac_resources stmmac_res;
655 	int ret;
656 
657 	priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);
658 	if (!priv_plat)
659 		return -ENOMEM;
660 
661 	priv_plat->variant = of_device_get_match_data(&pdev->dev);
662 	if (!priv_plat->variant) {
663 		dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n");
664 		return -EINVAL;
665 	}
666 
667 	priv_plat->dev = &pdev->dev;
668 	priv_plat->np = pdev->dev.of_node;
669 
670 	ret = mediatek_dwmac_config_dt(priv_plat);
671 	if (ret)
672 		return ret;
673 
674 	ret = mediatek_dwmac_clk_init(priv_plat);
675 	if (ret)
676 		return ret;
677 
678 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
679 	if (ret)
680 		return ret;
681 
682 	plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
683 	if (IS_ERR(plat_dat))
684 		return PTR_ERR(plat_dat);
685 
686 	mediatek_dwmac_common_data(pdev, plat_dat, priv_plat);
687 	mediatek_dwmac_init(pdev, priv_plat);
688 
689 	ret = mediatek_dwmac_clks_config(priv_plat, true);
690 	if (ret)
691 		goto err_remove_config_dt;
692 
693 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
694 	if (ret)
695 		goto err_drv_probe;
696 
697 	return 0;
698 
699 err_drv_probe:
700 	mediatek_dwmac_clks_config(priv_plat, false);
701 err_remove_config_dt:
702 	stmmac_remove_config_dt(pdev, plat_dat);
703 
704 	return ret;
705 }
706 
707 static int mediatek_dwmac_remove(struct platform_device *pdev)
708 {
709 	struct mediatek_dwmac_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev);
710 	int ret;
711 
712 	ret = stmmac_pltfr_remove(pdev);
713 	mediatek_dwmac_clks_config(priv_plat, false);
714 
715 	return ret;
716 }
717 
718 static const struct of_device_id mediatek_dwmac_match[] = {
719 	{ .compatible = "mediatek,mt2712-gmac",
720 	  .data = &mt2712_gmac_variant },
721 	{ .compatible = "mediatek,mt8195-gmac",
722 	  .data = &mt8195_gmac_variant },
723 	{ }
724 };
725 
726 MODULE_DEVICE_TABLE(of, mediatek_dwmac_match);
727 
728 static struct platform_driver mediatek_dwmac_driver = {
729 	.probe  = mediatek_dwmac_probe,
730 	.remove = mediatek_dwmac_remove,
731 	.driver = {
732 		.name           = "dwmac-mediatek",
733 		.pm		= &stmmac_pltfr_pm_ops,
734 		.of_match_table = mediatek_dwmac_match,
735 	},
736 };
737 module_platform_driver(mediatek_dwmac_driver);
738 
739 MODULE_AUTHOR("Biao Huang <biao.huang@mediatek.com>");
740 MODULE_DESCRIPTION("MediaTek DWMAC specific glue layer");
741 MODULE_LICENSE("GPL v2");
742