1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 12 struct intel_priv_data { 13 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 14 }; 15 16 /* This struct is used to associate PCI Function of MAC controller on a board, 17 * discovered via DMI, with the address of PHY connected to the MAC. The 18 * negative value of the address means that MAC controller is not connected 19 * with PHY. 20 */ 21 struct stmmac_pci_func_data { 22 unsigned int func; 23 int phy_addr; 24 }; 25 26 struct stmmac_pci_dmi_data { 27 const struct stmmac_pci_func_data *func; 28 size_t nfuncs; 29 }; 30 31 struct stmmac_pci_info { 32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 33 }; 34 35 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 36 const struct dmi_system_id *dmi_list) 37 { 38 const struct stmmac_pci_func_data *func_data; 39 const struct stmmac_pci_dmi_data *dmi_data; 40 const struct dmi_system_id *dmi_id; 41 int func = PCI_FUNC(pdev->devfn); 42 size_t n; 43 44 dmi_id = dmi_first_match(dmi_list); 45 if (!dmi_id) 46 return -ENODEV; 47 48 dmi_data = dmi_id->driver_data; 49 func_data = dmi_data->func; 50 51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 52 if (func_data->func == func) 53 return func_data->phy_addr; 54 55 return -ENODEV; 56 } 57 58 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 59 int phyreg, u32 mask, u32 val) 60 { 61 unsigned int retries = 10; 62 int val_rd; 63 64 do { 65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 66 if ((val_rd & mask) == (val & mask)) 67 return 0; 68 udelay(POLL_DELAY_US); 69 } while (--retries); 70 71 return -ETIMEDOUT; 72 } 73 74 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 75 { 76 struct intel_priv_data *intel_priv = priv_data; 77 struct stmmac_priv *priv = netdev_priv(ndev); 78 int serdes_phy_addr = 0; 79 u32 data = 0; 80 81 if (!intel_priv->mdio_adhoc_addr) 82 return 0; 83 84 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 85 86 /* assert clk_req */ 87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 88 data |= SERDES_PLL_CLK; 89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 90 91 /* check for clk_ack assertion */ 92 data = serdes_status_poll(priv, serdes_phy_addr, 93 SERDES_GSR0, 94 SERDES_PLL_CLK, 95 SERDES_PLL_CLK); 96 97 if (data) { 98 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 99 return data; 100 } 101 102 /* assert lane reset */ 103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 104 data |= SERDES_RST; 105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 106 107 /* check for assert lane reset reflection */ 108 data = serdes_status_poll(priv, serdes_phy_addr, 109 SERDES_GSR0, 110 SERDES_RST, 111 SERDES_RST); 112 113 if (data) { 114 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 115 return data; 116 } 117 118 /* move power state to P0 */ 119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 120 121 data &= ~SERDES_PWR_ST_MASK; 122 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 123 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* Check for P0 state */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_PWR_ST_MASK, 130 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 131 132 if (data) { 133 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 134 return data; 135 } 136 137 return 0; 138 } 139 140 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 141 { 142 struct intel_priv_data *intel_priv = intel_data; 143 struct stmmac_priv *priv = netdev_priv(ndev); 144 int serdes_phy_addr = 0; 145 u32 data = 0; 146 147 if (!intel_priv->mdio_adhoc_addr) 148 return; 149 150 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 151 152 /* move power state to P3 */ 153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 154 155 data &= ~SERDES_PWR_ST_MASK; 156 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 157 158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 159 160 /* Check for P3 state */ 161 data = serdes_status_poll(priv, serdes_phy_addr, 162 SERDES_GSR0, 163 SERDES_PWR_ST_MASK, 164 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 165 166 if (data) { 167 dev_err(priv->device, "Serdes power state P3 timeout\n"); 168 return; 169 } 170 171 /* de-assert clk_req */ 172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 173 data &= ~SERDES_PLL_CLK; 174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 175 176 /* check for clk_ack de-assert */ 177 data = serdes_status_poll(priv, serdes_phy_addr, 178 SERDES_GSR0, 179 SERDES_PLL_CLK, 180 (u32)~SERDES_PLL_CLK); 181 182 if (data) { 183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 184 return; 185 } 186 187 /* de-assert lane reset */ 188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 189 data &= ~SERDES_RST; 190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 191 192 /* check for de-assert lane reset reflection */ 193 data = serdes_status_poll(priv, serdes_phy_addr, 194 SERDES_GSR0, 195 SERDES_RST, 196 (u32)~SERDES_RST); 197 198 if (data) { 199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 200 return; 201 } 202 } 203 204 static void common_default_data(struct plat_stmmacenet_data *plat) 205 { 206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 207 plat->has_gmac = 1; 208 plat->force_sf_dma_mode = 1; 209 210 plat->mdio_bus_data->needs_reset = true; 211 212 /* Set default value for multicast hash bins */ 213 plat->multicast_filter_bins = HASH_TABLE_SIZE; 214 215 /* Set default value for unicast filter entries */ 216 plat->unicast_filter_entries = 1; 217 218 /* Set the maxmtu to a default of JUMBO_LEN */ 219 plat->maxmtu = JUMBO_LEN; 220 221 /* Set default number of RX and TX queues to use */ 222 plat->tx_queues_to_use = 1; 223 plat->rx_queues_to_use = 1; 224 225 /* Disable Priority config by default */ 226 plat->tx_queues_cfg[0].use_prio = false; 227 plat->rx_queues_cfg[0].use_prio = false; 228 229 /* Disable RX queues routing by default */ 230 plat->rx_queues_cfg[0].pkt_route = 0x0; 231 } 232 233 static int intel_mgbe_common_data(struct pci_dev *pdev, 234 struct plat_stmmacenet_data *plat) 235 { 236 int ret; 237 int i; 238 239 plat->clk_csr = 5; 240 plat->has_gmac = 0; 241 plat->has_gmac4 = 1; 242 plat->force_sf_dma_mode = 0; 243 plat->tso_en = 1; 244 245 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 246 247 for (i = 0; i < plat->rx_queues_to_use; i++) { 248 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 249 plat->rx_queues_cfg[i].chan = i; 250 251 /* Disable Priority config by default */ 252 plat->rx_queues_cfg[i].use_prio = false; 253 254 /* Disable RX queues routing by default */ 255 plat->rx_queues_cfg[i].pkt_route = 0x0; 256 } 257 258 for (i = 0; i < plat->tx_queues_to_use; i++) { 259 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 260 261 /* Disable Priority config by default */ 262 plat->tx_queues_cfg[i].use_prio = false; 263 } 264 265 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 266 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 267 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 268 269 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 270 plat->tx_queues_cfg[0].weight = 0x09; 271 plat->tx_queues_cfg[1].weight = 0x0A; 272 plat->tx_queues_cfg[2].weight = 0x0B; 273 plat->tx_queues_cfg[3].weight = 0x0C; 274 plat->tx_queues_cfg[4].weight = 0x0D; 275 plat->tx_queues_cfg[5].weight = 0x0E; 276 plat->tx_queues_cfg[6].weight = 0x0F; 277 plat->tx_queues_cfg[7].weight = 0x10; 278 279 plat->dma_cfg->pbl = 32; 280 plat->dma_cfg->pblx8 = true; 281 plat->dma_cfg->fixed_burst = 0; 282 plat->dma_cfg->mixed_burst = 0; 283 plat->dma_cfg->aal = 0; 284 285 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 286 GFP_KERNEL); 287 if (!plat->axi) 288 return -ENOMEM; 289 290 plat->axi->axi_lpi_en = 0; 291 plat->axi->axi_xit_frm = 0; 292 plat->axi->axi_wr_osr_lmt = 1; 293 plat->axi->axi_rd_osr_lmt = 1; 294 plat->axi->axi_blen[0] = 4; 295 plat->axi->axi_blen[1] = 8; 296 plat->axi->axi_blen[2] = 16; 297 298 plat->ptp_max_adj = plat->clk_ptp_rate; 299 plat->eee_usecs_rate = plat->clk_ptp_rate; 300 301 /* Set system clock */ 302 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 303 "stmmac-clk", NULL, 0, 304 plat->clk_ptp_rate); 305 306 if (IS_ERR(plat->stmmac_clk)) { 307 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 308 plat->stmmac_clk = NULL; 309 } 310 311 ret = clk_prepare_enable(plat->stmmac_clk); 312 if (ret) { 313 clk_unregister_fixed_rate(plat->stmmac_clk); 314 return ret; 315 } 316 317 /* Set default value for multicast hash bins */ 318 plat->multicast_filter_bins = HASH_TABLE_SIZE; 319 320 /* Set default value for unicast filter entries */ 321 plat->unicast_filter_entries = 1; 322 323 /* Set the maxmtu to a default of JUMBO_LEN */ 324 plat->maxmtu = JUMBO_LEN; 325 326 plat->vlan_fail_q_en = true; 327 328 /* Use the last Rx queue */ 329 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 330 331 return 0; 332 } 333 334 static int ehl_common_data(struct pci_dev *pdev, 335 struct plat_stmmacenet_data *plat) 336 { 337 plat->rx_queues_to_use = 8; 338 plat->tx_queues_to_use = 8; 339 plat->clk_ptp_rate = 200000000; 340 341 return intel_mgbe_common_data(pdev, plat); 342 } 343 344 static int ehl_sgmii_data(struct pci_dev *pdev, 345 struct plat_stmmacenet_data *plat) 346 { 347 plat->bus_id = 1; 348 plat->phy_addr = 0; 349 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 350 351 plat->serdes_powerup = intel_serdes_powerup; 352 plat->serdes_powerdown = intel_serdes_powerdown; 353 354 return ehl_common_data(pdev, plat); 355 } 356 357 static struct stmmac_pci_info ehl_sgmii1g_info = { 358 .setup = ehl_sgmii_data, 359 }; 360 361 static int ehl_rgmii_data(struct pci_dev *pdev, 362 struct plat_stmmacenet_data *plat) 363 { 364 plat->bus_id = 1; 365 plat->phy_addr = 0; 366 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 367 368 return ehl_common_data(pdev, plat); 369 } 370 371 static struct stmmac_pci_info ehl_rgmii1g_info = { 372 .setup = ehl_rgmii_data, 373 }; 374 375 static int ehl_pse0_common_data(struct pci_dev *pdev, 376 struct plat_stmmacenet_data *plat) 377 { 378 plat->bus_id = 2; 379 plat->phy_addr = 1; 380 return ehl_common_data(pdev, plat); 381 } 382 383 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 384 struct plat_stmmacenet_data *plat) 385 { 386 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 387 return ehl_pse0_common_data(pdev, plat); 388 } 389 390 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 391 .setup = ehl_pse0_rgmii1g_data, 392 }; 393 394 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 395 struct plat_stmmacenet_data *plat) 396 { 397 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 398 plat->serdes_powerup = intel_serdes_powerup; 399 plat->serdes_powerdown = intel_serdes_powerdown; 400 return ehl_pse0_common_data(pdev, plat); 401 } 402 403 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 404 .setup = ehl_pse0_sgmii1g_data, 405 }; 406 407 static int ehl_pse1_common_data(struct pci_dev *pdev, 408 struct plat_stmmacenet_data *plat) 409 { 410 plat->bus_id = 3; 411 plat->phy_addr = 1; 412 return ehl_common_data(pdev, plat); 413 } 414 415 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 416 struct plat_stmmacenet_data *plat) 417 { 418 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 419 return ehl_pse1_common_data(pdev, plat); 420 } 421 422 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 423 .setup = ehl_pse1_rgmii1g_data, 424 }; 425 426 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 427 struct plat_stmmacenet_data *plat) 428 { 429 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 430 plat->serdes_powerup = intel_serdes_powerup; 431 plat->serdes_powerdown = intel_serdes_powerdown; 432 return ehl_pse1_common_data(pdev, plat); 433 } 434 435 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 436 .setup = ehl_pse1_sgmii1g_data, 437 }; 438 439 static int tgl_common_data(struct pci_dev *pdev, 440 struct plat_stmmacenet_data *plat) 441 { 442 plat->rx_queues_to_use = 6; 443 plat->tx_queues_to_use = 4; 444 plat->clk_ptp_rate = 200000000; 445 446 return intel_mgbe_common_data(pdev, plat); 447 } 448 449 static int tgl_sgmii_data(struct pci_dev *pdev, 450 struct plat_stmmacenet_data *plat) 451 { 452 plat->bus_id = 1; 453 plat->phy_addr = 0; 454 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 455 plat->serdes_powerup = intel_serdes_powerup; 456 plat->serdes_powerdown = intel_serdes_powerdown; 457 return tgl_common_data(pdev, plat); 458 } 459 460 static struct stmmac_pci_info tgl_sgmii1g_info = { 461 .setup = tgl_sgmii_data, 462 }; 463 464 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 465 { 466 .func = 6, 467 .phy_addr = 1, 468 }, 469 }; 470 471 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 472 .func = galileo_stmmac_func_data, 473 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 474 }; 475 476 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 477 { 478 .func = 6, 479 .phy_addr = 1, 480 }, 481 { 482 .func = 7, 483 .phy_addr = 1, 484 }, 485 }; 486 487 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 488 .func = iot2040_stmmac_func_data, 489 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 490 }; 491 492 static const struct dmi_system_id quark_pci_dmi[] = { 493 { 494 .matches = { 495 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 496 }, 497 .driver_data = (void *)&galileo_stmmac_dmi_data, 498 }, 499 { 500 .matches = { 501 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 502 }, 503 .driver_data = (void *)&galileo_stmmac_dmi_data, 504 }, 505 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 506 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 507 * has only one pci network device while other asset tags are 508 * for IOT2040 which has two. 509 */ 510 { 511 .matches = { 512 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 513 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 514 "6ES7647-0AA00-0YA2"), 515 }, 516 .driver_data = (void *)&galileo_stmmac_dmi_data, 517 }, 518 { 519 .matches = { 520 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 521 }, 522 .driver_data = (void *)&iot2040_stmmac_dmi_data, 523 }, 524 {} 525 }; 526 527 static int quark_default_data(struct pci_dev *pdev, 528 struct plat_stmmacenet_data *plat) 529 { 530 int ret; 531 532 /* Set common default data first */ 533 common_default_data(plat); 534 535 /* Refuse to load the driver and register net device if MAC controller 536 * does not connect to any PHY interface. 537 */ 538 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 539 if (ret < 0) { 540 /* Return error to the caller on DMI enabled boards. */ 541 if (dmi_get_system_info(DMI_BOARD_NAME)) 542 return ret; 543 544 /* Galileo boards with old firmware don't support DMI. We always 545 * use 1 here as PHY address, so at least the first found MAC 546 * controller would be probed. 547 */ 548 ret = 1; 549 } 550 551 plat->bus_id = pci_dev_id(pdev); 552 plat->phy_addr = ret; 553 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 554 555 plat->dma_cfg->pbl = 16; 556 plat->dma_cfg->pblx8 = true; 557 plat->dma_cfg->fixed_burst = 1; 558 /* AXI (TODO) */ 559 560 return 0; 561 } 562 563 static const struct stmmac_pci_info quark_info = { 564 .setup = quark_default_data, 565 }; 566 567 /** 568 * intel_eth_pci_probe 569 * 570 * @pdev: pci device pointer 571 * @id: pointer to table of device id/id's. 572 * 573 * Description: This probing function gets called for all PCI devices which 574 * match the ID table and are not "owned" by other driver yet. This function 575 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 576 * matches the device. The probe functions returns zero when the driver choose 577 * to take "ownership" of the device or an error code(-ve no) otherwise. 578 */ 579 static int intel_eth_pci_probe(struct pci_dev *pdev, 580 const struct pci_device_id *id) 581 { 582 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 583 struct intel_priv_data *intel_priv; 584 struct plat_stmmacenet_data *plat; 585 struct stmmac_resources res; 586 int ret; 587 588 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 589 if (!intel_priv) 590 return -ENOMEM; 591 592 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 593 if (!plat) 594 return -ENOMEM; 595 596 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 597 sizeof(*plat->mdio_bus_data), 598 GFP_KERNEL); 599 if (!plat->mdio_bus_data) 600 return -ENOMEM; 601 602 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 603 GFP_KERNEL); 604 if (!plat->dma_cfg) 605 return -ENOMEM; 606 607 /* Enable pci device */ 608 ret = pci_enable_device(pdev); 609 if (ret) { 610 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 611 __func__); 612 return ret; 613 } 614 615 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 616 if (ret) 617 return ret; 618 619 pci_set_master(pdev); 620 621 plat->bsp_priv = intel_priv; 622 intel_priv->mdio_adhoc_addr = 0x15; 623 624 ret = info->setup(pdev, plat); 625 if (ret) 626 return ret; 627 628 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 629 if (ret < 0) 630 return ret; 631 632 memset(&res, 0, sizeof(res)); 633 res.addr = pcim_iomap_table(pdev)[0]; 634 res.wol_irq = pci_irq_vector(pdev, 0); 635 res.irq = pci_irq_vector(pdev, 0); 636 637 if (plat->eee_usecs_rate > 0) { 638 u32 tx_lpi_usec; 639 640 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 641 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 642 } 643 644 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 645 if (ret) { 646 pci_free_irq_vectors(pdev); 647 clk_disable_unprepare(plat->stmmac_clk); 648 clk_unregister_fixed_rate(plat->stmmac_clk); 649 } 650 651 return ret; 652 } 653 654 /** 655 * intel_eth_pci_remove 656 * 657 * @pdev: platform device pointer 658 * Description: this function calls the main to free the net resources 659 * and releases the PCI resources. 660 */ 661 static void intel_eth_pci_remove(struct pci_dev *pdev) 662 { 663 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 664 struct stmmac_priv *priv = netdev_priv(ndev); 665 666 stmmac_dvr_remove(&pdev->dev); 667 668 pci_free_irq_vectors(pdev); 669 670 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 671 672 pcim_iounmap_regions(pdev, BIT(0)); 673 674 pci_disable_device(pdev); 675 } 676 677 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 678 { 679 struct pci_dev *pdev = to_pci_dev(dev); 680 int ret; 681 682 ret = stmmac_suspend(dev); 683 if (ret) 684 return ret; 685 686 ret = pci_save_state(pdev); 687 if (ret) 688 return ret; 689 690 pci_disable_device(pdev); 691 pci_wake_from_d3(pdev, true); 692 return 0; 693 } 694 695 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 696 { 697 struct pci_dev *pdev = to_pci_dev(dev); 698 int ret; 699 700 pci_restore_state(pdev); 701 pci_set_power_state(pdev, PCI_D0); 702 703 ret = pci_enable_device(pdev); 704 if (ret) 705 return ret; 706 707 pci_set_master(pdev); 708 709 return stmmac_resume(dev); 710 } 711 712 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 713 intel_eth_pci_resume); 714 715 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 716 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 717 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 718 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 719 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 720 * which are named PSE0 and PSE1 721 */ 722 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 723 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 724 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 725 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 726 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 727 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 728 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 729 730 static const struct pci_device_id intel_eth_pci_id_table[] = { 731 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, 732 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, 733 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, 734 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, 735 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, 736 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, 737 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, 738 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, 739 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, 740 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, 741 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) }, 742 {} 743 }; 744 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 745 746 static struct pci_driver intel_eth_pci_driver = { 747 .name = "intel-eth-pci", 748 .id_table = intel_eth_pci_id_table, 749 .probe = intel_eth_pci_probe, 750 .remove = intel_eth_pci_remove, 751 .driver = { 752 .pm = &intel_eth_pm_ops, 753 }, 754 }; 755 756 module_pci_driver(intel_eth_pci_driver); 757 758 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 759 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 760 MODULE_LICENSE("GPL v2"); 761