1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 12 #define INTEL_MGBE_ADHOC_ADDR 0x15 13 #define INTEL_MGBE_XPCS_ADDR 0x16 14 15 struct intel_priv_data { 16 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 17 }; 18 19 /* This struct is used to associate PCI Function of MAC controller on a board, 20 * discovered via DMI, with the address of PHY connected to the MAC. The 21 * negative value of the address means that MAC controller is not connected 22 * with PHY. 23 */ 24 struct stmmac_pci_func_data { 25 unsigned int func; 26 int phy_addr; 27 }; 28 29 struct stmmac_pci_dmi_data { 30 const struct stmmac_pci_func_data *func; 31 size_t nfuncs; 32 }; 33 34 struct stmmac_pci_info { 35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 36 }; 37 38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 39 const struct dmi_system_id *dmi_list) 40 { 41 const struct stmmac_pci_func_data *func_data; 42 const struct stmmac_pci_dmi_data *dmi_data; 43 const struct dmi_system_id *dmi_id; 44 int func = PCI_FUNC(pdev->devfn); 45 size_t n; 46 47 dmi_id = dmi_first_match(dmi_list); 48 if (!dmi_id) 49 return -ENODEV; 50 51 dmi_data = dmi_id->driver_data; 52 func_data = dmi_data->func; 53 54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 55 if (func_data->func == func) 56 return func_data->phy_addr; 57 58 return -ENODEV; 59 } 60 61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 62 int phyreg, u32 mask, u32 val) 63 { 64 unsigned int retries = 10; 65 int val_rd; 66 67 do { 68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 69 if ((val_rd & mask) == (val & mask)) 70 return 0; 71 udelay(POLL_DELAY_US); 72 } while (--retries); 73 74 return -ETIMEDOUT; 75 } 76 77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 78 { 79 struct intel_priv_data *intel_priv = priv_data; 80 struct stmmac_priv *priv = netdev_priv(ndev); 81 int serdes_phy_addr = 0; 82 u32 data = 0; 83 84 if (!intel_priv->mdio_adhoc_addr) 85 return 0; 86 87 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 88 89 /* assert clk_req */ 90 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 91 data |= SERDES_PLL_CLK; 92 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 93 94 /* check for clk_ack assertion */ 95 data = serdes_status_poll(priv, serdes_phy_addr, 96 SERDES_GSR0, 97 SERDES_PLL_CLK, 98 SERDES_PLL_CLK); 99 100 if (data) { 101 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 102 return data; 103 } 104 105 /* assert lane reset */ 106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 107 data |= SERDES_RST; 108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 109 110 /* check for assert lane reset reflection */ 111 data = serdes_status_poll(priv, serdes_phy_addr, 112 SERDES_GSR0, 113 SERDES_RST, 114 SERDES_RST); 115 116 if (data) { 117 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 118 return data; 119 } 120 121 /* move power state to P0 */ 122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 123 124 data &= ~SERDES_PWR_ST_MASK; 125 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 126 127 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 128 129 /* Check for P0 state */ 130 data = serdes_status_poll(priv, serdes_phy_addr, 131 SERDES_GSR0, 132 SERDES_PWR_ST_MASK, 133 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 134 135 if (data) { 136 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 137 return data; 138 } 139 140 return 0; 141 } 142 143 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 144 { 145 struct intel_priv_data *intel_priv = intel_data; 146 struct stmmac_priv *priv = netdev_priv(ndev); 147 int serdes_phy_addr = 0; 148 u32 data = 0; 149 150 if (!intel_priv->mdio_adhoc_addr) 151 return; 152 153 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 154 155 /* move power state to P3 */ 156 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 157 158 data &= ~SERDES_PWR_ST_MASK; 159 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 160 161 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 162 163 /* Check for P3 state */ 164 data = serdes_status_poll(priv, serdes_phy_addr, 165 SERDES_GSR0, 166 SERDES_PWR_ST_MASK, 167 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 168 169 if (data) { 170 dev_err(priv->device, "Serdes power state P3 timeout\n"); 171 return; 172 } 173 174 /* de-assert clk_req */ 175 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 176 data &= ~SERDES_PLL_CLK; 177 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 178 179 /* check for clk_ack de-assert */ 180 data = serdes_status_poll(priv, serdes_phy_addr, 181 SERDES_GSR0, 182 SERDES_PLL_CLK, 183 (u32)~SERDES_PLL_CLK); 184 185 if (data) { 186 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 187 return; 188 } 189 190 /* de-assert lane reset */ 191 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 192 data &= ~SERDES_RST; 193 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 194 195 /* check for de-assert lane reset reflection */ 196 data = serdes_status_poll(priv, serdes_phy_addr, 197 SERDES_GSR0, 198 SERDES_RST, 199 (u32)~SERDES_RST); 200 201 if (data) { 202 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 203 return; 204 } 205 } 206 207 static void common_default_data(struct plat_stmmacenet_data *plat) 208 { 209 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 210 plat->has_gmac = 1; 211 plat->force_sf_dma_mode = 1; 212 213 plat->mdio_bus_data->needs_reset = true; 214 215 /* Set default value for multicast hash bins */ 216 plat->multicast_filter_bins = HASH_TABLE_SIZE; 217 218 /* Set default value for unicast filter entries */ 219 plat->unicast_filter_entries = 1; 220 221 /* Set the maxmtu to a default of JUMBO_LEN */ 222 plat->maxmtu = JUMBO_LEN; 223 224 /* Set default number of RX and TX queues to use */ 225 plat->tx_queues_to_use = 1; 226 plat->rx_queues_to_use = 1; 227 228 /* Disable Priority config by default */ 229 plat->tx_queues_cfg[0].use_prio = false; 230 plat->rx_queues_cfg[0].use_prio = false; 231 232 /* Disable RX queues routing by default */ 233 plat->rx_queues_cfg[0].pkt_route = 0x0; 234 } 235 236 static int intel_mgbe_common_data(struct pci_dev *pdev, 237 struct plat_stmmacenet_data *plat) 238 { 239 char clk_name[20]; 240 int ret; 241 int i; 242 243 plat->pdev = pdev; 244 plat->phy_addr = -1; 245 plat->clk_csr = 5; 246 plat->has_gmac = 0; 247 plat->has_gmac4 = 1; 248 plat->force_sf_dma_mode = 0; 249 plat->tso_en = 1; 250 251 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 252 253 for (i = 0; i < plat->rx_queues_to_use; i++) { 254 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 255 plat->rx_queues_cfg[i].chan = i; 256 257 /* Disable Priority config by default */ 258 plat->rx_queues_cfg[i].use_prio = false; 259 260 /* Disable RX queues routing by default */ 261 plat->rx_queues_cfg[i].pkt_route = 0x0; 262 } 263 264 for (i = 0; i < plat->tx_queues_to_use; i++) { 265 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 266 267 /* Disable Priority config by default */ 268 plat->tx_queues_cfg[i].use_prio = false; 269 } 270 271 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 272 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 273 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 274 275 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 276 plat->tx_queues_cfg[0].weight = 0x09; 277 plat->tx_queues_cfg[1].weight = 0x0A; 278 plat->tx_queues_cfg[2].weight = 0x0B; 279 plat->tx_queues_cfg[3].weight = 0x0C; 280 plat->tx_queues_cfg[4].weight = 0x0D; 281 plat->tx_queues_cfg[5].weight = 0x0E; 282 plat->tx_queues_cfg[6].weight = 0x0F; 283 plat->tx_queues_cfg[7].weight = 0x10; 284 285 plat->dma_cfg->pbl = 32; 286 plat->dma_cfg->pblx8 = true; 287 plat->dma_cfg->fixed_burst = 0; 288 plat->dma_cfg->mixed_burst = 0; 289 plat->dma_cfg->aal = 0; 290 291 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 292 GFP_KERNEL); 293 if (!plat->axi) 294 return -ENOMEM; 295 296 plat->axi->axi_lpi_en = 0; 297 plat->axi->axi_xit_frm = 0; 298 plat->axi->axi_wr_osr_lmt = 1; 299 plat->axi->axi_rd_osr_lmt = 1; 300 plat->axi->axi_blen[0] = 4; 301 plat->axi->axi_blen[1] = 8; 302 plat->axi->axi_blen[2] = 16; 303 304 plat->ptp_max_adj = plat->clk_ptp_rate; 305 plat->eee_usecs_rate = plat->clk_ptp_rate; 306 307 /* Set system clock */ 308 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); 309 310 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 311 clk_name, NULL, 0, 312 plat->clk_ptp_rate); 313 314 if (IS_ERR(plat->stmmac_clk)) { 315 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 316 plat->stmmac_clk = NULL; 317 } 318 319 ret = clk_prepare_enable(plat->stmmac_clk); 320 if (ret) { 321 clk_unregister_fixed_rate(plat->stmmac_clk); 322 return ret; 323 } 324 325 /* Set default value for multicast hash bins */ 326 plat->multicast_filter_bins = HASH_TABLE_SIZE; 327 328 /* Set default value for unicast filter entries */ 329 plat->unicast_filter_entries = 1; 330 331 /* Set the maxmtu to a default of JUMBO_LEN */ 332 plat->maxmtu = JUMBO_LEN; 333 334 plat->vlan_fail_q_en = true; 335 336 /* Use the last Rx queue */ 337 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 338 339 /* Intel mgbe SGMII interface uses pcs-xcps */ 340 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII) { 341 plat->mdio_bus_data->has_xpcs = true; 342 plat->mdio_bus_data->xpcs_an_inband = true; 343 } 344 345 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ 346 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; 347 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; 348 349 return 0; 350 } 351 352 static int ehl_common_data(struct pci_dev *pdev, 353 struct plat_stmmacenet_data *plat) 354 { 355 plat->rx_queues_to_use = 8; 356 plat->tx_queues_to_use = 8; 357 plat->clk_ptp_rate = 200000000; 358 359 return intel_mgbe_common_data(pdev, plat); 360 } 361 362 static int ehl_sgmii_data(struct pci_dev *pdev, 363 struct plat_stmmacenet_data *plat) 364 { 365 plat->bus_id = 1; 366 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 367 368 plat->serdes_powerup = intel_serdes_powerup; 369 plat->serdes_powerdown = intel_serdes_powerdown; 370 371 return ehl_common_data(pdev, plat); 372 } 373 374 static struct stmmac_pci_info ehl_sgmii1g_info = { 375 .setup = ehl_sgmii_data, 376 }; 377 378 static int ehl_rgmii_data(struct pci_dev *pdev, 379 struct plat_stmmacenet_data *plat) 380 { 381 plat->bus_id = 1; 382 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 383 384 return ehl_common_data(pdev, plat); 385 } 386 387 static struct stmmac_pci_info ehl_rgmii1g_info = { 388 .setup = ehl_rgmii_data, 389 }; 390 391 static int ehl_pse0_common_data(struct pci_dev *pdev, 392 struct plat_stmmacenet_data *plat) 393 { 394 plat->bus_id = 2; 395 plat->addr64 = 32; 396 return ehl_common_data(pdev, plat); 397 } 398 399 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 400 struct plat_stmmacenet_data *plat) 401 { 402 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 403 return ehl_pse0_common_data(pdev, plat); 404 } 405 406 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 407 .setup = ehl_pse0_rgmii1g_data, 408 }; 409 410 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 411 struct plat_stmmacenet_data *plat) 412 { 413 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 414 plat->serdes_powerup = intel_serdes_powerup; 415 plat->serdes_powerdown = intel_serdes_powerdown; 416 return ehl_pse0_common_data(pdev, plat); 417 } 418 419 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 420 .setup = ehl_pse0_sgmii1g_data, 421 }; 422 423 static int ehl_pse1_common_data(struct pci_dev *pdev, 424 struct plat_stmmacenet_data *plat) 425 { 426 plat->bus_id = 3; 427 plat->addr64 = 32; 428 return ehl_common_data(pdev, plat); 429 } 430 431 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 432 struct plat_stmmacenet_data *plat) 433 { 434 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 435 return ehl_pse1_common_data(pdev, plat); 436 } 437 438 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 439 .setup = ehl_pse1_rgmii1g_data, 440 }; 441 442 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 443 struct plat_stmmacenet_data *plat) 444 { 445 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 446 plat->serdes_powerup = intel_serdes_powerup; 447 plat->serdes_powerdown = intel_serdes_powerdown; 448 return ehl_pse1_common_data(pdev, plat); 449 } 450 451 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 452 .setup = ehl_pse1_sgmii1g_data, 453 }; 454 455 static int tgl_common_data(struct pci_dev *pdev, 456 struct plat_stmmacenet_data *plat) 457 { 458 plat->rx_queues_to_use = 6; 459 plat->tx_queues_to_use = 4; 460 plat->clk_ptp_rate = 200000000; 461 462 return intel_mgbe_common_data(pdev, plat); 463 } 464 465 static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 466 struct plat_stmmacenet_data *plat) 467 { 468 plat->bus_id = 1; 469 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 470 plat->serdes_powerup = intel_serdes_powerup; 471 plat->serdes_powerdown = intel_serdes_powerdown; 472 return tgl_common_data(pdev, plat); 473 } 474 475 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = { 476 .setup = tgl_sgmii_phy0_data, 477 }; 478 479 static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 480 struct plat_stmmacenet_data *plat) 481 { 482 plat->bus_id = 2; 483 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 484 plat->serdes_powerup = intel_serdes_powerup; 485 plat->serdes_powerdown = intel_serdes_powerdown; 486 return tgl_common_data(pdev, plat); 487 } 488 489 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = { 490 .setup = tgl_sgmii_phy1_data, 491 }; 492 493 static int adls_sgmii_phy0_data(struct pci_dev *pdev, 494 struct plat_stmmacenet_data *plat) 495 { 496 plat->bus_id = 1; 497 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 498 499 /* SerDes power up and power down are done in BIOS for ADL */ 500 501 return tgl_common_data(pdev, plat); 502 } 503 504 static struct stmmac_pci_info adls_sgmii1g_phy0_info = { 505 .setup = adls_sgmii_phy0_data, 506 }; 507 508 static int adls_sgmii_phy1_data(struct pci_dev *pdev, 509 struct plat_stmmacenet_data *plat) 510 { 511 plat->bus_id = 2; 512 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 513 514 /* SerDes power up and power down are done in BIOS for ADL */ 515 516 return tgl_common_data(pdev, plat); 517 } 518 519 static struct stmmac_pci_info adls_sgmii1g_phy1_info = { 520 .setup = adls_sgmii_phy1_data, 521 }; 522 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 523 { 524 .func = 6, 525 .phy_addr = 1, 526 }, 527 }; 528 529 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 530 .func = galileo_stmmac_func_data, 531 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 532 }; 533 534 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 535 { 536 .func = 6, 537 .phy_addr = 1, 538 }, 539 { 540 .func = 7, 541 .phy_addr = 1, 542 }, 543 }; 544 545 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 546 .func = iot2040_stmmac_func_data, 547 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 548 }; 549 550 static const struct dmi_system_id quark_pci_dmi[] = { 551 { 552 .matches = { 553 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 554 }, 555 .driver_data = (void *)&galileo_stmmac_dmi_data, 556 }, 557 { 558 .matches = { 559 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 560 }, 561 .driver_data = (void *)&galileo_stmmac_dmi_data, 562 }, 563 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 564 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 565 * has only one pci network device while other asset tags are 566 * for IOT2040 which has two. 567 */ 568 { 569 .matches = { 570 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 571 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 572 "6ES7647-0AA00-0YA2"), 573 }, 574 .driver_data = (void *)&galileo_stmmac_dmi_data, 575 }, 576 { 577 .matches = { 578 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 579 }, 580 .driver_data = (void *)&iot2040_stmmac_dmi_data, 581 }, 582 {} 583 }; 584 585 static int quark_default_data(struct pci_dev *pdev, 586 struct plat_stmmacenet_data *plat) 587 { 588 int ret; 589 590 /* Set common default data first */ 591 common_default_data(plat); 592 593 /* Refuse to load the driver and register net device if MAC controller 594 * does not connect to any PHY interface. 595 */ 596 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 597 if (ret < 0) { 598 /* Return error to the caller on DMI enabled boards. */ 599 if (dmi_get_system_info(DMI_BOARD_NAME)) 600 return ret; 601 602 /* Galileo boards with old firmware don't support DMI. We always 603 * use 1 here as PHY address, so at least the first found MAC 604 * controller would be probed. 605 */ 606 ret = 1; 607 } 608 609 plat->bus_id = pci_dev_id(pdev); 610 plat->phy_addr = ret; 611 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 612 613 plat->dma_cfg->pbl = 16; 614 plat->dma_cfg->pblx8 = true; 615 plat->dma_cfg->fixed_burst = 1; 616 /* AXI (TODO) */ 617 618 return 0; 619 } 620 621 static const struct stmmac_pci_info quark_info = { 622 .setup = quark_default_data, 623 }; 624 625 /** 626 * intel_eth_pci_probe 627 * 628 * @pdev: pci device pointer 629 * @id: pointer to table of device id/id's. 630 * 631 * Description: This probing function gets called for all PCI devices which 632 * match the ID table and are not "owned" by other driver yet. This function 633 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 634 * matches the device. The probe functions returns zero when the driver choose 635 * to take "ownership" of the device or an error code(-ve no) otherwise. 636 */ 637 static int intel_eth_pci_probe(struct pci_dev *pdev, 638 const struct pci_device_id *id) 639 { 640 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 641 struct intel_priv_data *intel_priv; 642 struct plat_stmmacenet_data *plat; 643 struct stmmac_resources res; 644 int ret; 645 646 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 647 if (!intel_priv) 648 return -ENOMEM; 649 650 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 651 if (!plat) 652 return -ENOMEM; 653 654 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 655 sizeof(*plat->mdio_bus_data), 656 GFP_KERNEL); 657 if (!plat->mdio_bus_data) 658 return -ENOMEM; 659 660 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 661 GFP_KERNEL); 662 if (!plat->dma_cfg) 663 return -ENOMEM; 664 665 /* Enable pci device */ 666 ret = pci_enable_device(pdev); 667 if (ret) { 668 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 669 __func__); 670 return ret; 671 } 672 673 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 674 if (ret) 675 return ret; 676 677 pci_set_master(pdev); 678 679 plat->bsp_priv = intel_priv; 680 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; 681 682 ret = info->setup(pdev, plat); 683 if (ret) 684 return ret; 685 686 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 687 if (ret < 0) 688 return ret; 689 690 memset(&res, 0, sizeof(res)); 691 res.addr = pcim_iomap_table(pdev)[0]; 692 res.wol_irq = pci_irq_vector(pdev, 0); 693 res.irq = pci_irq_vector(pdev, 0); 694 695 if (plat->eee_usecs_rate > 0) { 696 u32 tx_lpi_usec; 697 698 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 699 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 700 } 701 702 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 703 if (ret) { 704 pci_free_irq_vectors(pdev); 705 clk_disable_unprepare(plat->stmmac_clk); 706 clk_unregister_fixed_rate(plat->stmmac_clk); 707 } 708 709 return ret; 710 } 711 712 /** 713 * intel_eth_pci_remove 714 * 715 * @pdev: platform device pointer 716 * Description: this function calls the main to free the net resources 717 * and releases the PCI resources. 718 */ 719 static void intel_eth_pci_remove(struct pci_dev *pdev) 720 { 721 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 722 struct stmmac_priv *priv = netdev_priv(ndev); 723 724 stmmac_dvr_remove(&pdev->dev); 725 726 pci_free_irq_vectors(pdev); 727 728 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 729 730 pcim_iounmap_regions(pdev, BIT(0)); 731 732 pci_disable_device(pdev); 733 } 734 735 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 736 { 737 struct pci_dev *pdev = to_pci_dev(dev); 738 int ret; 739 740 ret = stmmac_suspend(dev); 741 if (ret) 742 return ret; 743 744 ret = pci_save_state(pdev); 745 if (ret) 746 return ret; 747 748 pci_disable_device(pdev); 749 pci_wake_from_d3(pdev, true); 750 return 0; 751 } 752 753 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 754 { 755 struct pci_dev *pdev = to_pci_dev(dev); 756 int ret; 757 758 pci_restore_state(pdev); 759 pci_set_power_state(pdev, PCI_D0); 760 761 ret = pci_enable_device(pdev); 762 if (ret) 763 return ret; 764 765 pci_set_master(pdev); 766 767 return stmmac_resume(dev); 768 } 769 770 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 771 intel_eth_pci_resume); 772 773 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 774 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 775 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 776 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 777 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 778 * which are named PSE0 and PSE1 779 */ 780 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 781 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 782 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 783 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 784 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 785 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 786 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac 787 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2 788 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 789 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac 790 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad 791 792 static const struct pci_device_id intel_eth_pci_id_table[] = { 793 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, 794 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, 795 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, 796 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, 797 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, 798 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, 799 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, 800 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, 801 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, 802 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, 803 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_phy0_info) }, 804 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_phy0_info) }, 805 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_phy1_info) }, 806 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_phy0_info) }, 807 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_phy1_info) }, 808 {} 809 }; 810 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 811 812 static struct pci_driver intel_eth_pci_driver = { 813 .name = "intel-eth-pci", 814 .id_table = intel_eth_pci_id_table, 815 .probe = intel_eth_pci_probe, 816 .remove = intel_eth_pci_remove, 817 .driver = { 818 .pm = &intel_eth_pm_ops, 819 }, 820 }; 821 822 module_pci_driver(intel_eth_pci_driver); 823 824 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 825 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 826 MODULE_LICENSE("GPL v2"); 827