1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "stmmac.h" 10 11 struct intel_priv_data { 12 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 13 }; 14 15 /* This struct is used to associate PCI Function of MAC controller on a board, 16 * discovered via DMI, with the address of PHY connected to the MAC. The 17 * negative value of the address means that MAC controller is not connected 18 * with PHY. 19 */ 20 struct stmmac_pci_func_data { 21 unsigned int func; 22 int phy_addr; 23 }; 24 25 struct stmmac_pci_dmi_data { 26 const struct stmmac_pci_func_data *func; 27 size_t nfuncs; 28 }; 29 30 struct stmmac_pci_info { 31 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 32 }; 33 34 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 35 const struct dmi_system_id *dmi_list) 36 { 37 const struct stmmac_pci_func_data *func_data; 38 const struct stmmac_pci_dmi_data *dmi_data; 39 const struct dmi_system_id *dmi_id; 40 int func = PCI_FUNC(pdev->devfn); 41 size_t n; 42 43 dmi_id = dmi_first_match(dmi_list); 44 if (!dmi_id) 45 return -ENODEV; 46 47 dmi_data = dmi_id->driver_data; 48 func_data = dmi_data->func; 49 50 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 51 if (func_data->func == func) 52 return func_data->phy_addr; 53 54 return -ENODEV; 55 } 56 57 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 58 int phyreg, u32 mask, u32 val) 59 { 60 unsigned int retries = 10; 61 int val_rd; 62 63 do { 64 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 65 if ((val_rd & mask) == (val & mask)) 66 return 0; 67 udelay(POLL_DELAY_US); 68 } while (--retries); 69 70 return -ETIMEDOUT; 71 } 72 73 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 74 { 75 struct intel_priv_data *intel_priv = priv_data; 76 struct stmmac_priv *priv = netdev_priv(ndev); 77 int serdes_phy_addr = 0; 78 u32 data = 0; 79 80 if (!intel_priv->mdio_adhoc_addr) 81 return 0; 82 83 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 84 85 /* assert clk_req */ 86 data = mdiobus_read(priv->mii, serdes_phy_addr, 87 SERDES_GCR0); 88 89 data |= SERDES_PLL_CLK; 90 91 mdiobus_write(priv->mii, serdes_phy_addr, 92 SERDES_GCR0, data); 93 94 /* check for clk_ack assertion */ 95 data = serdes_status_poll(priv, serdes_phy_addr, 96 SERDES_GSR0, 97 SERDES_PLL_CLK, 98 SERDES_PLL_CLK); 99 100 if (data) { 101 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 102 return data; 103 } 104 105 /* assert lane reset */ 106 data = mdiobus_read(priv->mii, serdes_phy_addr, 107 SERDES_GCR0); 108 109 data |= SERDES_RST; 110 111 mdiobus_write(priv->mii, serdes_phy_addr, 112 SERDES_GCR0, data); 113 114 /* check for assert lane reset reflection */ 115 data = serdes_status_poll(priv, serdes_phy_addr, 116 SERDES_GSR0, 117 SERDES_RST, 118 SERDES_RST); 119 120 if (data) { 121 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 122 return data; 123 } 124 125 /* move power state to P0 */ 126 data = mdiobus_read(priv->mii, serdes_phy_addr, 127 SERDES_GCR0); 128 129 data &= ~SERDES_PWR_ST_MASK; 130 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 131 132 mdiobus_write(priv->mii, serdes_phy_addr, 133 SERDES_GCR0, data); 134 135 /* Check for P0 state */ 136 data = serdes_status_poll(priv, serdes_phy_addr, 137 SERDES_GSR0, 138 SERDES_PWR_ST_MASK, 139 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 140 141 if (data) { 142 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 143 return data; 144 } 145 146 return 0; 147 } 148 149 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 150 { 151 struct intel_priv_data *intel_priv = intel_data; 152 struct stmmac_priv *priv = netdev_priv(ndev); 153 int serdes_phy_addr = 0; 154 u32 data = 0; 155 156 if (!intel_priv->mdio_adhoc_addr) 157 return; 158 159 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 160 161 /* move power state to P3 */ 162 data = mdiobus_read(priv->mii, serdes_phy_addr, 163 SERDES_GCR0); 164 165 data &= ~SERDES_PWR_ST_MASK; 166 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 167 168 mdiobus_write(priv->mii, serdes_phy_addr, 169 SERDES_GCR0, data); 170 171 /* Check for P3 state */ 172 data = serdes_status_poll(priv, serdes_phy_addr, 173 SERDES_GSR0, 174 SERDES_PWR_ST_MASK, 175 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 176 177 if (data) { 178 dev_err(priv->device, "Serdes power state P3 timeout\n"); 179 return; 180 } 181 182 /* de-assert clk_req */ 183 data = mdiobus_read(priv->mii, serdes_phy_addr, 184 SERDES_GCR0); 185 186 data &= ~SERDES_PLL_CLK; 187 188 mdiobus_write(priv->mii, serdes_phy_addr, 189 SERDES_GCR0, data); 190 191 /* check for clk_ack de-assert */ 192 data = serdes_status_poll(priv, serdes_phy_addr, 193 SERDES_GSR0, 194 SERDES_PLL_CLK, 195 (u32)~SERDES_PLL_CLK); 196 197 if (data) { 198 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 199 return; 200 } 201 202 /* de-assert lane reset */ 203 data = mdiobus_read(priv->mii, serdes_phy_addr, 204 SERDES_GCR0); 205 206 data &= ~SERDES_RST; 207 208 mdiobus_write(priv->mii, serdes_phy_addr, 209 SERDES_GCR0, data); 210 211 /* check for de-assert lane reset reflection */ 212 data = serdes_status_poll(priv, serdes_phy_addr, 213 SERDES_GSR0, 214 SERDES_RST, 215 (u32)~SERDES_RST); 216 217 if (data) { 218 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 219 return; 220 } 221 } 222 223 static void common_default_data(struct plat_stmmacenet_data *plat) 224 { 225 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 226 plat->has_gmac = 1; 227 plat->force_sf_dma_mode = 1; 228 229 plat->mdio_bus_data->needs_reset = true; 230 231 /* Set default value for multicast hash bins */ 232 plat->multicast_filter_bins = HASH_TABLE_SIZE; 233 234 /* Set default value for unicast filter entries */ 235 plat->unicast_filter_entries = 1; 236 237 /* Set the maxmtu to a default of JUMBO_LEN */ 238 plat->maxmtu = JUMBO_LEN; 239 240 /* Set default number of RX and TX queues to use */ 241 plat->tx_queues_to_use = 1; 242 plat->rx_queues_to_use = 1; 243 244 /* Disable Priority config by default */ 245 plat->tx_queues_cfg[0].use_prio = false; 246 plat->rx_queues_cfg[0].use_prio = false; 247 248 /* Disable RX queues routing by default */ 249 plat->rx_queues_cfg[0].pkt_route = 0x0; 250 } 251 252 static int intel_mgbe_common_data(struct pci_dev *pdev, 253 struct plat_stmmacenet_data *plat) 254 { 255 int i; 256 257 plat->clk_csr = 5; 258 plat->has_gmac = 0; 259 plat->has_gmac4 = 1; 260 plat->force_sf_dma_mode = 0; 261 plat->tso_en = 1; 262 263 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 264 265 for (i = 0; i < plat->rx_queues_to_use; i++) { 266 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 267 plat->rx_queues_cfg[i].chan = i; 268 269 /* Disable Priority config by default */ 270 plat->rx_queues_cfg[i].use_prio = false; 271 272 /* Disable RX queues routing by default */ 273 plat->rx_queues_cfg[i].pkt_route = 0x0; 274 } 275 276 for (i = 0; i < plat->tx_queues_to_use; i++) { 277 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 278 279 /* Disable Priority config by default */ 280 plat->tx_queues_cfg[i].use_prio = false; 281 } 282 283 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 284 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 285 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 286 287 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 288 plat->tx_queues_cfg[0].weight = 0x09; 289 plat->tx_queues_cfg[1].weight = 0x0A; 290 plat->tx_queues_cfg[2].weight = 0x0B; 291 plat->tx_queues_cfg[3].weight = 0x0C; 292 plat->tx_queues_cfg[4].weight = 0x0D; 293 plat->tx_queues_cfg[5].weight = 0x0E; 294 plat->tx_queues_cfg[6].weight = 0x0F; 295 plat->tx_queues_cfg[7].weight = 0x10; 296 297 plat->dma_cfg->pbl = 32; 298 plat->dma_cfg->pblx8 = true; 299 plat->dma_cfg->fixed_burst = 0; 300 plat->dma_cfg->mixed_burst = 0; 301 plat->dma_cfg->aal = 0; 302 303 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 304 GFP_KERNEL); 305 if (!plat->axi) 306 return -ENOMEM; 307 308 plat->axi->axi_lpi_en = 0; 309 plat->axi->axi_xit_frm = 0; 310 plat->axi->axi_wr_osr_lmt = 1; 311 plat->axi->axi_rd_osr_lmt = 1; 312 plat->axi->axi_blen[0] = 4; 313 plat->axi->axi_blen[1] = 8; 314 plat->axi->axi_blen[2] = 16; 315 316 plat->ptp_max_adj = plat->clk_ptp_rate; 317 318 /* Set system clock */ 319 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 320 "stmmac-clk", NULL, 0, 321 plat->clk_ptp_rate); 322 323 if (IS_ERR(plat->stmmac_clk)) { 324 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 325 plat->stmmac_clk = NULL; 326 } 327 clk_prepare_enable(plat->stmmac_clk); 328 329 /* Set default value for multicast hash bins */ 330 plat->multicast_filter_bins = HASH_TABLE_SIZE; 331 332 /* Set default value for unicast filter entries */ 333 plat->unicast_filter_entries = 1; 334 335 /* Set the maxmtu to a default of JUMBO_LEN */ 336 plat->maxmtu = JUMBO_LEN; 337 338 return 0; 339 } 340 341 static int ehl_common_data(struct pci_dev *pdev, 342 struct plat_stmmacenet_data *plat) 343 { 344 int ret; 345 346 plat->rx_queues_to_use = 8; 347 plat->tx_queues_to_use = 8; 348 plat->clk_ptp_rate = 200000000; 349 ret = intel_mgbe_common_data(pdev, plat); 350 if (ret) 351 return ret; 352 353 return 0; 354 } 355 356 static int ehl_sgmii_data(struct pci_dev *pdev, 357 struct plat_stmmacenet_data *plat) 358 { 359 plat->bus_id = 1; 360 plat->phy_addr = 0; 361 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 362 363 plat->serdes_powerup = intel_serdes_powerup; 364 plat->serdes_powerdown = intel_serdes_powerdown; 365 366 return ehl_common_data(pdev, plat); 367 } 368 369 static struct stmmac_pci_info ehl_sgmii1g_pci_info = { 370 .setup = ehl_sgmii_data, 371 }; 372 373 static int ehl_rgmii_data(struct pci_dev *pdev, 374 struct plat_stmmacenet_data *plat) 375 { 376 plat->bus_id = 1; 377 plat->phy_addr = 0; 378 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 379 380 return ehl_common_data(pdev, plat); 381 } 382 383 static struct stmmac_pci_info ehl_rgmii1g_pci_info = { 384 .setup = ehl_rgmii_data, 385 }; 386 387 static int ehl_pse0_common_data(struct pci_dev *pdev, 388 struct plat_stmmacenet_data *plat) 389 { 390 plat->bus_id = 2; 391 plat->phy_addr = 1; 392 return ehl_common_data(pdev, plat); 393 } 394 395 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 396 struct plat_stmmacenet_data *plat) 397 { 398 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 399 return ehl_pse0_common_data(pdev, plat); 400 } 401 402 static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = { 403 .setup = ehl_pse0_rgmii1g_data, 404 }; 405 406 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 407 struct plat_stmmacenet_data *plat) 408 { 409 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 410 plat->serdes_powerup = intel_serdes_powerup; 411 plat->serdes_powerdown = intel_serdes_powerdown; 412 return ehl_pse0_common_data(pdev, plat); 413 } 414 415 static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = { 416 .setup = ehl_pse0_sgmii1g_data, 417 }; 418 419 static int ehl_pse1_common_data(struct pci_dev *pdev, 420 struct plat_stmmacenet_data *plat) 421 { 422 plat->bus_id = 3; 423 plat->phy_addr = 1; 424 return ehl_common_data(pdev, plat); 425 } 426 427 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 428 struct plat_stmmacenet_data *plat) 429 { 430 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 431 return ehl_pse1_common_data(pdev, plat); 432 } 433 434 static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = { 435 .setup = ehl_pse1_rgmii1g_data, 436 }; 437 438 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 439 struct plat_stmmacenet_data *plat) 440 { 441 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 442 plat->serdes_powerup = intel_serdes_powerup; 443 plat->serdes_powerdown = intel_serdes_powerdown; 444 return ehl_pse1_common_data(pdev, plat); 445 } 446 447 static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = { 448 .setup = ehl_pse1_sgmii1g_data, 449 }; 450 451 static int tgl_common_data(struct pci_dev *pdev, 452 struct plat_stmmacenet_data *plat) 453 { 454 int ret; 455 456 plat->rx_queues_to_use = 6; 457 plat->tx_queues_to_use = 4; 458 plat->clk_ptp_rate = 200000000; 459 ret = intel_mgbe_common_data(pdev, plat); 460 if (ret) 461 return ret; 462 463 return 0; 464 } 465 466 static int tgl_sgmii_data(struct pci_dev *pdev, 467 struct plat_stmmacenet_data *plat) 468 { 469 plat->bus_id = 1; 470 plat->phy_addr = 0; 471 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 472 plat->serdes_powerup = intel_serdes_powerup; 473 plat->serdes_powerdown = intel_serdes_powerdown; 474 return tgl_common_data(pdev, plat); 475 } 476 477 static struct stmmac_pci_info tgl_sgmii1g_pci_info = { 478 .setup = tgl_sgmii_data, 479 }; 480 481 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 482 { 483 .func = 6, 484 .phy_addr = 1, 485 }, 486 }; 487 488 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 489 .func = galileo_stmmac_func_data, 490 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 491 }; 492 493 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 494 { 495 .func = 6, 496 .phy_addr = 1, 497 }, 498 { 499 .func = 7, 500 .phy_addr = 1, 501 }, 502 }; 503 504 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 505 .func = iot2040_stmmac_func_data, 506 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 507 }; 508 509 static const struct dmi_system_id quark_pci_dmi[] = { 510 { 511 .matches = { 512 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 513 }, 514 .driver_data = (void *)&galileo_stmmac_dmi_data, 515 }, 516 { 517 .matches = { 518 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 519 }, 520 .driver_data = (void *)&galileo_stmmac_dmi_data, 521 }, 522 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 523 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 524 * has only one pci network device while other asset tags are 525 * for IOT2040 which has two. 526 */ 527 { 528 .matches = { 529 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 530 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 531 "6ES7647-0AA00-0YA2"), 532 }, 533 .driver_data = (void *)&galileo_stmmac_dmi_data, 534 }, 535 { 536 .matches = { 537 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 538 }, 539 .driver_data = (void *)&iot2040_stmmac_dmi_data, 540 }, 541 {} 542 }; 543 544 static int quark_default_data(struct pci_dev *pdev, 545 struct plat_stmmacenet_data *plat) 546 { 547 int ret; 548 549 /* Set common default data first */ 550 common_default_data(plat); 551 552 /* Refuse to load the driver and register net device if MAC controller 553 * does not connect to any PHY interface. 554 */ 555 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 556 if (ret < 0) { 557 /* Return error to the caller on DMI enabled boards. */ 558 if (dmi_get_system_info(DMI_BOARD_NAME)) 559 return ret; 560 561 /* Galileo boards with old firmware don't support DMI. We always 562 * use 1 here as PHY address, so at least the first found MAC 563 * controller would be probed. 564 */ 565 ret = 1; 566 } 567 568 plat->bus_id = pci_dev_id(pdev); 569 plat->phy_addr = ret; 570 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 571 572 plat->dma_cfg->pbl = 16; 573 plat->dma_cfg->pblx8 = true; 574 plat->dma_cfg->fixed_burst = 1; 575 /* AXI (TODO) */ 576 577 return 0; 578 } 579 580 static const struct stmmac_pci_info quark_pci_info = { 581 .setup = quark_default_data, 582 }; 583 584 /** 585 * intel_eth_pci_probe 586 * 587 * @pdev: pci device pointer 588 * @id: pointer to table of device id/id's. 589 * 590 * Description: This probing function gets called for all PCI devices which 591 * match the ID table and are not "owned" by other driver yet. This function 592 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 593 * matches the device. The probe functions returns zero when the driver choose 594 * to take "ownership" of the device or an error code(-ve no) otherwise. 595 */ 596 static int intel_eth_pci_probe(struct pci_dev *pdev, 597 const struct pci_device_id *id) 598 { 599 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 600 struct intel_priv_data *intel_priv; 601 struct plat_stmmacenet_data *plat; 602 struct stmmac_resources res; 603 int i; 604 int ret; 605 606 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), 607 GFP_KERNEL); 608 if (!intel_priv) 609 return -ENOMEM; 610 611 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 612 if (!plat) 613 return -ENOMEM; 614 615 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 616 sizeof(*plat->mdio_bus_data), 617 GFP_KERNEL); 618 if (!plat->mdio_bus_data) 619 return -ENOMEM; 620 621 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 622 GFP_KERNEL); 623 if (!plat->dma_cfg) 624 return -ENOMEM; 625 626 /* Enable pci device */ 627 ret = pci_enable_device(pdev); 628 if (ret) { 629 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 630 __func__); 631 return ret; 632 } 633 634 /* Get the base address of device */ 635 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 636 if (pci_resource_len(pdev, i) == 0) 637 continue; 638 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev)); 639 if (ret) 640 return ret; 641 break; 642 } 643 644 pci_set_master(pdev); 645 646 plat->bsp_priv = intel_priv; 647 intel_priv->mdio_adhoc_addr = 0x15; 648 649 ret = info->setup(pdev, plat); 650 if (ret) 651 return ret; 652 653 pci_enable_msi(pdev); 654 655 memset(&res, 0, sizeof(res)); 656 res.addr = pcim_iomap_table(pdev)[i]; 657 res.wol_irq = pdev->irq; 658 res.irq = pdev->irq; 659 660 return stmmac_dvr_probe(&pdev->dev, plat, &res); 661 } 662 663 /** 664 * intel_eth_pci_remove 665 * 666 * @pdev: platform device pointer 667 * Description: this function calls the main to free the net resources 668 * and releases the PCI resources. 669 */ 670 static void intel_eth_pci_remove(struct pci_dev *pdev) 671 { 672 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 673 struct stmmac_priv *priv = netdev_priv(ndev); 674 int i; 675 676 stmmac_dvr_remove(&pdev->dev); 677 678 if (priv->plat->stmmac_clk) 679 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 680 681 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 682 if (pci_resource_len(pdev, i) == 0) 683 continue; 684 pcim_iounmap_regions(pdev, BIT(i)); 685 break; 686 } 687 688 pci_disable_device(pdev); 689 } 690 691 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 692 { 693 struct pci_dev *pdev = to_pci_dev(dev); 694 int ret; 695 696 ret = stmmac_suspend(dev); 697 if (ret) 698 return ret; 699 700 ret = pci_save_state(pdev); 701 if (ret) 702 return ret; 703 704 pci_disable_device(pdev); 705 pci_wake_from_d3(pdev, true); 706 return 0; 707 } 708 709 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 710 { 711 struct pci_dev *pdev = to_pci_dev(dev); 712 int ret; 713 714 pci_restore_state(pdev); 715 pci_set_power_state(pdev, PCI_D0); 716 717 ret = pci_enable_device(pdev); 718 if (ret) 719 return ret; 720 721 pci_set_master(pdev); 722 723 return stmmac_resume(dev); 724 } 725 726 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 727 intel_eth_pci_resume); 728 729 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 730 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 731 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 732 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 733 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 734 * which are named PSE0 and PSE1 735 */ 736 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 737 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 738 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 739 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 740 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 741 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 742 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 743 744 static const struct pci_device_id intel_eth_pci_id_table[] = { 745 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) }, 746 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) }, 747 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) }, 748 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) }, 749 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, 750 &ehl_pse0_rgmii1g_pci_info) }, 751 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, 752 &ehl_pse0_sgmii1g_pci_info) }, 753 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, 754 &ehl_pse0_sgmii1g_pci_info) }, 755 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, 756 &ehl_pse1_rgmii1g_pci_info) }, 757 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, 758 &ehl_pse1_sgmii1g_pci_info) }, 759 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, 760 &ehl_pse1_sgmii1g_pci_info) }, 761 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) }, 762 {} 763 }; 764 765 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 766 767 static struct pci_driver intel_eth_pci_driver = { 768 .name = "intel-eth-pci", 769 .id_table = intel_eth_pci_id_table, 770 .probe = intel_eth_pci_probe, 771 .remove = intel_eth_pci_remove, 772 .driver = { 773 .pm = &intel_eth_pm_ops, 774 }, 775 }; 776 777 module_pci_driver(intel_eth_pci_driver); 778 779 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 780 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 781 MODULE_LICENSE("GPL v2"); 782