1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 12 struct intel_priv_data { 13 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 14 }; 15 16 /* This struct is used to associate PCI Function of MAC controller on a board, 17 * discovered via DMI, with the address of PHY connected to the MAC. The 18 * negative value of the address means that MAC controller is not connected 19 * with PHY. 20 */ 21 struct stmmac_pci_func_data { 22 unsigned int func; 23 int phy_addr; 24 }; 25 26 struct stmmac_pci_dmi_data { 27 const struct stmmac_pci_func_data *func; 28 size_t nfuncs; 29 }; 30 31 struct stmmac_pci_info { 32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 33 }; 34 35 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 36 const struct dmi_system_id *dmi_list) 37 { 38 const struct stmmac_pci_func_data *func_data; 39 const struct stmmac_pci_dmi_data *dmi_data; 40 const struct dmi_system_id *dmi_id; 41 int func = PCI_FUNC(pdev->devfn); 42 size_t n; 43 44 dmi_id = dmi_first_match(dmi_list); 45 if (!dmi_id) 46 return -ENODEV; 47 48 dmi_data = dmi_id->driver_data; 49 func_data = dmi_data->func; 50 51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 52 if (func_data->func == func) 53 return func_data->phy_addr; 54 55 return -ENODEV; 56 } 57 58 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 59 int phyreg, u32 mask, u32 val) 60 { 61 unsigned int retries = 10; 62 int val_rd; 63 64 do { 65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 66 if ((val_rd & mask) == (val & mask)) 67 return 0; 68 udelay(POLL_DELAY_US); 69 } while (--retries); 70 71 return -ETIMEDOUT; 72 } 73 74 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 75 { 76 struct intel_priv_data *intel_priv = priv_data; 77 struct stmmac_priv *priv = netdev_priv(ndev); 78 int serdes_phy_addr = 0; 79 u32 data = 0; 80 81 if (!intel_priv->mdio_adhoc_addr) 82 return 0; 83 84 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 85 86 /* assert clk_req */ 87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 88 data |= SERDES_PLL_CLK; 89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 90 91 /* check for clk_ack assertion */ 92 data = serdes_status_poll(priv, serdes_phy_addr, 93 SERDES_GSR0, 94 SERDES_PLL_CLK, 95 SERDES_PLL_CLK); 96 97 if (data) { 98 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 99 return data; 100 } 101 102 /* assert lane reset */ 103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 104 data |= SERDES_RST; 105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 106 107 /* check for assert lane reset reflection */ 108 data = serdes_status_poll(priv, serdes_phy_addr, 109 SERDES_GSR0, 110 SERDES_RST, 111 SERDES_RST); 112 113 if (data) { 114 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 115 return data; 116 } 117 118 /* move power state to P0 */ 119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 120 121 data &= ~SERDES_PWR_ST_MASK; 122 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 123 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* Check for P0 state */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_PWR_ST_MASK, 130 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 131 132 if (data) { 133 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 134 return data; 135 } 136 137 return 0; 138 } 139 140 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 141 { 142 struct intel_priv_data *intel_priv = intel_data; 143 struct stmmac_priv *priv = netdev_priv(ndev); 144 int serdes_phy_addr = 0; 145 u32 data = 0; 146 147 if (!intel_priv->mdio_adhoc_addr) 148 return; 149 150 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 151 152 /* move power state to P3 */ 153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 154 155 data &= ~SERDES_PWR_ST_MASK; 156 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 157 158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 159 160 /* Check for P3 state */ 161 data = serdes_status_poll(priv, serdes_phy_addr, 162 SERDES_GSR0, 163 SERDES_PWR_ST_MASK, 164 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 165 166 if (data) { 167 dev_err(priv->device, "Serdes power state P3 timeout\n"); 168 return; 169 } 170 171 /* de-assert clk_req */ 172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 173 data &= ~SERDES_PLL_CLK; 174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 175 176 /* check for clk_ack de-assert */ 177 data = serdes_status_poll(priv, serdes_phy_addr, 178 SERDES_GSR0, 179 SERDES_PLL_CLK, 180 (u32)~SERDES_PLL_CLK); 181 182 if (data) { 183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 184 return; 185 } 186 187 /* de-assert lane reset */ 188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 189 data &= ~SERDES_RST; 190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 191 192 /* check for de-assert lane reset reflection */ 193 data = serdes_status_poll(priv, serdes_phy_addr, 194 SERDES_GSR0, 195 SERDES_RST, 196 (u32)~SERDES_RST); 197 198 if (data) { 199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 200 return; 201 } 202 } 203 204 static void common_default_data(struct plat_stmmacenet_data *plat) 205 { 206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 207 plat->has_gmac = 1; 208 plat->force_sf_dma_mode = 1; 209 210 plat->mdio_bus_data->needs_reset = true; 211 212 /* Set default value for multicast hash bins */ 213 plat->multicast_filter_bins = HASH_TABLE_SIZE; 214 215 /* Set default value for unicast filter entries */ 216 plat->unicast_filter_entries = 1; 217 218 /* Set the maxmtu to a default of JUMBO_LEN */ 219 plat->maxmtu = JUMBO_LEN; 220 221 /* Set default number of RX and TX queues to use */ 222 plat->tx_queues_to_use = 1; 223 plat->rx_queues_to_use = 1; 224 225 /* Disable Priority config by default */ 226 plat->tx_queues_cfg[0].use_prio = false; 227 plat->rx_queues_cfg[0].use_prio = false; 228 229 /* Disable RX queues routing by default */ 230 plat->rx_queues_cfg[0].pkt_route = 0x0; 231 } 232 233 static int intel_mgbe_common_data(struct pci_dev *pdev, 234 struct plat_stmmacenet_data *plat) 235 { 236 char clk_name[20]; 237 int ret; 238 int i; 239 240 plat->pdev = pdev; 241 plat->phy_addr = -1; 242 plat->clk_csr = 5; 243 plat->has_gmac = 0; 244 plat->has_gmac4 = 1; 245 plat->force_sf_dma_mode = 0; 246 plat->tso_en = 1; 247 248 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 249 250 for (i = 0; i < plat->rx_queues_to_use; i++) { 251 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 252 plat->rx_queues_cfg[i].chan = i; 253 254 /* Disable Priority config by default */ 255 plat->rx_queues_cfg[i].use_prio = false; 256 257 /* Disable RX queues routing by default */ 258 plat->rx_queues_cfg[i].pkt_route = 0x0; 259 } 260 261 for (i = 0; i < plat->tx_queues_to_use; i++) { 262 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 263 264 /* Disable Priority config by default */ 265 plat->tx_queues_cfg[i].use_prio = false; 266 } 267 268 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 269 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 270 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 271 272 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 273 plat->tx_queues_cfg[0].weight = 0x09; 274 plat->tx_queues_cfg[1].weight = 0x0A; 275 plat->tx_queues_cfg[2].weight = 0x0B; 276 plat->tx_queues_cfg[3].weight = 0x0C; 277 plat->tx_queues_cfg[4].weight = 0x0D; 278 plat->tx_queues_cfg[5].weight = 0x0E; 279 plat->tx_queues_cfg[6].weight = 0x0F; 280 plat->tx_queues_cfg[7].weight = 0x10; 281 282 plat->dma_cfg->pbl = 32; 283 plat->dma_cfg->pblx8 = true; 284 plat->dma_cfg->fixed_burst = 0; 285 plat->dma_cfg->mixed_burst = 0; 286 plat->dma_cfg->aal = 0; 287 288 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 289 GFP_KERNEL); 290 if (!plat->axi) 291 return -ENOMEM; 292 293 plat->axi->axi_lpi_en = 0; 294 plat->axi->axi_xit_frm = 0; 295 plat->axi->axi_wr_osr_lmt = 1; 296 plat->axi->axi_rd_osr_lmt = 1; 297 plat->axi->axi_blen[0] = 4; 298 plat->axi->axi_blen[1] = 8; 299 plat->axi->axi_blen[2] = 16; 300 301 plat->ptp_max_adj = plat->clk_ptp_rate; 302 plat->eee_usecs_rate = plat->clk_ptp_rate; 303 304 /* Set system clock */ 305 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); 306 307 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 308 clk_name, NULL, 0, 309 plat->clk_ptp_rate); 310 311 if (IS_ERR(plat->stmmac_clk)) { 312 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 313 plat->stmmac_clk = NULL; 314 } 315 316 ret = clk_prepare_enable(plat->stmmac_clk); 317 if (ret) { 318 clk_unregister_fixed_rate(plat->stmmac_clk); 319 return ret; 320 } 321 322 /* Set default value for multicast hash bins */ 323 plat->multicast_filter_bins = HASH_TABLE_SIZE; 324 325 /* Set default value for unicast filter entries */ 326 plat->unicast_filter_entries = 1; 327 328 /* Set the maxmtu to a default of JUMBO_LEN */ 329 plat->maxmtu = JUMBO_LEN; 330 331 plat->vlan_fail_q_en = true; 332 333 /* Use the last Rx queue */ 334 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 335 336 return 0; 337 } 338 339 static int ehl_common_data(struct pci_dev *pdev, 340 struct plat_stmmacenet_data *plat) 341 { 342 plat->rx_queues_to_use = 8; 343 plat->tx_queues_to_use = 8; 344 plat->clk_ptp_rate = 200000000; 345 346 return intel_mgbe_common_data(pdev, plat); 347 } 348 349 static int ehl_sgmii_data(struct pci_dev *pdev, 350 struct plat_stmmacenet_data *plat) 351 { 352 plat->bus_id = 1; 353 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 354 355 plat->serdes_powerup = intel_serdes_powerup; 356 plat->serdes_powerdown = intel_serdes_powerdown; 357 358 return ehl_common_data(pdev, plat); 359 } 360 361 static struct stmmac_pci_info ehl_sgmii1g_info = { 362 .setup = ehl_sgmii_data, 363 }; 364 365 static int ehl_rgmii_data(struct pci_dev *pdev, 366 struct plat_stmmacenet_data *plat) 367 { 368 plat->bus_id = 1; 369 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 370 371 return ehl_common_data(pdev, plat); 372 } 373 374 static struct stmmac_pci_info ehl_rgmii1g_info = { 375 .setup = ehl_rgmii_data, 376 }; 377 378 static int ehl_pse0_common_data(struct pci_dev *pdev, 379 struct plat_stmmacenet_data *plat) 380 { 381 plat->bus_id = 2; 382 plat->addr64 = 32; 383 return ehl_common_data(pdev, plat); 384 } 385 386 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 387 struct plat_stmmacenet_data *plat) 388 { 389 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 390 return ehl_pse0_common_data(pdev, plat); 391 } 392 393 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 394 .setup = ehl_pse0_rgmii1g_data, 395 }; 396 397 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 398 struct plat_stmmacenet_data *plat) 399 { 400 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 401 plat->serdes_powerup = intel_serdes_powerup; 402 plat->serdes_powerdown = intel_serdes_powerdown; 403 return ehl_pse0_common_data(pdev, plat); 404 } 405 406 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 407 .setup = ehl_pse0_sgmii1g_data, 408 }; 409 410 static int ehl_pse1_common_data(struct pci_dev *pdev, 411 struct plat_stmmacenet_data *plat) 412 { 413 plat->bus_id = 3; 414 plat->addr64 = 32; 415 return ehl_common_data(pdev, plat); 416 } 417 418 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 419 struct plat_stmmacenet_data *plat) 420 { 421 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 422 return ehl_pse1_common_data(pdev, plat); 423 } 424 425 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 426 .setup = ehl_pse1_rgmii1g_data, 427 }; 428 429 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 430 struct plat_stmmacenet_data *plat) 431 { 432 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 433 plat->serdes_powerup = intel_serdes_powerup; 434 plat->serdes_powerdown = intel_serdes_powerdown; 435 return ehl_pse1_common_data(pdev, plat); 436 } 437 438 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 439 .setup = ehl_pse1_sgmii1g_data, 440 }; 441 442 static int tgl_common_data(struct pci_dev *pdev, 443 struct plat_stmmacenet_data *plat) 444 { 445 plat->rx_queues_to_use = 6; 446 plat->tx_queues_to_use = 4; 447 plat->clk_ptp_rate = 200000000; 448 449 return intel_mgbe_common_data(pdev, plat); 450 } 451 452 static int tgl_sgmii_phy0_data(struct pci_dev *pdev, 453 struct plat_stmmacenet_data *plat) 454 { 455 plat->bus_id = 1; 456 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 457 plat->serdes_powerup = intel_serdes_powerup; 458 plat->serdes_powerdown = intel_serdes_powerdown; 459 return tgl_common_data(pdev, plat); 460 } 461 462 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = { 463 .setup = tgl_sgmii_phy0_data, 464 }; 465 466 static int tgl_sgmii_phy1_data(struct pci_dev *pdev, 467 struct plat_stmmacenet_data *plat) 468 { 469 plat->bus_id = 2; 470 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 471 plat->serdes_powerup = intel_serdes_powerup; 472 plat->serdes_powerdown = intel_serdes_powerdown; 473 return tgl_common_data(pdev, plat); 474 } 475 476 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = { 477 .setup = tgl_sgmii_phy1_data, 478 }; 479 480 static int adls_sgmii_phy0_data(struct pci_dev *pdev, 481 struct plat_stmmacenet_data *plat) 482 { 483 plat->bus_id = 1; 484 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 485 486 /* SerDes power up and power down are done in BIOS for ADL */ 487 488 return tgl_common_data(pdev, plat); 489 } 490 491 static struct stmmac_pci_info adls_sgmii1g_phy0_info = { 492 .setup = adls_sgmii_phy0_data, 493 }; 494 495 static int adls_sgmii_phy1_data(struct pci_dev *pdev, 496 struct plat_stmmacenet_data *plat) 497 { 498 plat->bus_id = 2; 499 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 500 501 /* SerDes power up and power down are done in BIOS for ADL */ 502 503 return tgl_common_data(pdev, plat); 504 } 505 506 static struct stmmac_pci_info adls_sgmii1g_phy1_info = { 507 .setup = adls_sgmii_phy1_data, 508 }; 509 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 510 { 511 .func = 6, 512 .phy_addr = 1, 513 }, 514 }; 515 516 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 517 .func = galileo_stmmac_func_data, 518 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 519 }; 520 521 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 522 { 523 .func = 6, 524 .phy_addr = 1, 525 }, 526 { 527 .func = 7, 528 .phy_addr = 1, 529 }, 530 }; 531 532 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 533 .func = iot2040_stmmac_func_data, 534 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 535 }; 536 537 static const struct dmi_system_id quark_pci_dmi[] = { 538 { 539 .matches = { 540 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 541 }, 542 .driver_data = (void *)&galileo_stmmac_dmi_data, 543 }, 544 { 545 .matches = { 546 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 547 }, 548 .driver_data = (void *)&galileo_stmmac_dmi_data, 549 }, 550 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 551 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 552 * has only one pci network device while other asset tags are 553 * for IOT2040 which has two. 554 */ 555 { 556 .matches = { 557 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 558 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 559 "6ES7647-0AA00-0YA2"), 560 }, 561 .driver_data = (void *)&galileo_stmmac_dmi_data, 562 }, 563 { 564 .matches = { 565 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 566 }, 567 .driver_data = (void *)&iot2040_stmmac_dmi_data, 568 }, 569 {} 570 }; 571 572 static int quark_default_data(struct pci_dev *pdev, 573 struct plat_stmmacenet_data *plat) 574 { 575 int ret; 576 577 /* Set common default data first */ 578 common_default_data(plat); 579 580 /* Refuse to load the driver and register net device if MAC controller 581 * does not connect to any PHY interface. 582 */ 583 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 584 if (ret < 0) { 585 /* Return error to the caller on DMI enabled boards. */ 586 if (dmi_get_system_info(DMI_BOARD_NAME)) 587 return ret; 588 589 /* Galileo boards with old firmware don't support DMI. We always 590 * use 1 here as PHY address, so at least the first found MAC 591 * controller would be probed. 592 */ 593 ret = 1; 594 } 595 596 plat->bus_id = pci_dev_id(pdev); 597 plat->phy_addr = ret; 598 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 599 600 plat->dma_cfg->pbl = 16; 601 plat->dma_cfg->pblx8 = true; 602 plat->dma_cfg->fixed_burst = 1; 603 /* AXI (TODO) */ 604 605 return 0; 606 } 607 608 static const struct stmmac_pci_info quark_info = { 609 .setup = quark_default_data, 610 }; 611 612 /** 613 * intel_eth_pci_probe 614 * 615 * @pdev: pci device pointer 616 * @id: pointer to table of device id/id's. 617 * 618 * Description: This probing function gets called for all PCI devices which 619 * match the ID table and are not "owned" by other driver yet. This function 620 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 621 * matches the device. The probe functions returns zero when the driver choose 622 * to take "ownership" of the device or an error code(-ve no) otherwise. 623 */ 624 static int intel_eth_pci_probe(struct pci_dev *pdev, 625 const struct pci_device_id *id) 626 { 627 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 628 struct intel_priv_data *intel_priv; 629 struct plat_stmmacenet_data *plat; 630 struct stmmac_resources res; 631 int ret; 632 633 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 634 if (!intel_priv) 635 return -ENOMEM; 636 637 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 638 if (!plat) 639 return -ENOMEM; 640 641 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 642 sizeof(*plat->mdio_bus_data), 643 GFP_KERNEL); 644 if (!plat->mdio_bus_data) 645 return -ENOMEM; 646 647 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 648 GFP_KERNEL); 649 if (!plat->dma_cfg) 650 return -ENOMEM; 651 652 /* Enable pci device */ 653 ret = pci_enable_device(pdev); 654 if (ret) { 655 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 656 __func__); 657 return ret; 658 } 659 660 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 661 if (ret) 662 return ret; 663 664 pci_set_master(pdev); 665 666 plat->bsp_priv = intel_priv; 667 intel_priv->mdio_adhoc_addr = 0x15; 668 669 ret = info->setup(pdev, plat); 670 if (ret) 671 return ret; 672 673 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 674 if (ret < 0) 675 return ret; 676 677 memset(&res, 0, sizeof(res)); 678 res.addr = pcim_iomap_table(pdev)[0]; 679 res.wol_irq = pci_irq_vector(pdev, 0); 680 res.irq = pci_irq_vector(pdev, 0); 681 682 if (plat->eee_usecs_rate > 0) { 683 u32 tx_lpi_usec; 684 685 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 686 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 687 } 688 689 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 690 if (ret) { 691 pci_free_irq_vectors(pdev); 692 clk_disable_unprepare(plat->stmmac_clk); 693 clk_unregister_fixed_rate(plat->stmmac_clk); 694 } 695 696 return ret; 697 } 698 699 /** 700 * intel_eth_pci_remove 701 * 702 * @pdev: platform device pointer 703 * Description: this function calls the main to free the net resources 704 * and releases the PCI resources. 705 */ 706 static void intel_eth_pci_remove(struct pci_dev *pdev) 707 { 708 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 709 struct stmmac_priv *priv = netdev_priv(ndev); 710 711 stmmac_dvr_remove(&pdev->dev); 712 713 pci_free_irq_vectors(pdev); 714 715 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 716 717 pcim_iounmap_regions(pdev, BIT(0)); 718 719 pci_disable_device(pdev); 720 } 721 722 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 723 { 724 struct pci_dev *pdev = to_pci_dev(dev); 725 int ret; 726 727 ret = stmmac_suspend(dev); 728 if (ret) 729 return ret; 730 731 ret = pci_save_state(pdev); 732 if (ret) 733 return ret; 734 735 pci_disable_device(pdev); 736 pci_wake_from_d3(pdev, true); 737 return 0; 738 } 739 740 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 741 { 742 struct pci_dev *pdev = to_pci_dev(dev); 743 int ret; 744 745 pci_restore_state(pdev); 746 pci_set_power_state(pdev, PCI_D0); 747 748 ret = pci_enable_device(pdev); 749 if (ret) 750 return ret; 751 752 pci_set_master(pdev); 753 754 return stmmac_resume(dev); 755 } 756 757 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 758 intel_eth_pci_resume); 759 760 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 761 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 762 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 763 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 764 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 765 * which are named PSE0 and PSE1 766 */ 767 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 768 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 769 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 770 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 771 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 772 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 773 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac 774 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2 775 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 776 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac 777 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad 778 779 static const struct pci_device_id intel_eth_pci_id_table[] = { 780 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, 781 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, 782 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, 783 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, 784 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, 785 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, 786 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, 787 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, 788 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, 789 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, 790 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_phy0_info) }, 791 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_phy0_info) }, 792 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_phy1_info) }, 793 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_phy0_info) }, 794 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_phy1_info) }, 795 {} 796 }; 797 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 798 799 static struct pci_driver intel_eth_pci_driver = { 800 .name = "intel-eth-pci", 801 .id_table = intel_eth_pci_id_table, 802 .probe = intel_eth_pci_probe, 803 .remove = intel_eth_pci_remove, 804 .driver = { 805 .pm = &intel_eth_pm_ops, 806 }, 807 }; 808 809 module_pci_driver(intel_eth_pci_driver); 810 811 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 812 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 813 MODULE_LICENSE("GPL v2"); 814