1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "dwmac-intel.h" 9 #include "dwmac4.h" 10 #include "stmmac.h" 11 12 struct intel_priv_data { 13 int mdio_adhoc_addr; /* mdio address for serdes & etc */ 14 }; 15 16 /* This struct is used to associate PCI Function of MAC controller on a board, 17 * discovered via DMI, with the address of PHY connected to the MAC. The 18 * negative value of the address means that MAC controller is not connected 19 * with PHY. 20 */ 21 struct stmmac_pci_func_data { 22 unsigned int func; 23 int phy_addr; 24 }; 25 26 struct stmmac_pci_dmi_data { 27 const struct stmmac_pci_func_data *func; 28 size_t nfuncs; 29 }; 30 31 struct stmmac_pci_info { 32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 33 }; 34 35 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 36 const struct dmi_system_id *dmi_list) 37 { 38 const struct stmmac_pci_func_data *func_data; 39 const struct stmmac_pci_dmi_data *dmi_data; 40 const struct dmi_system_id *dmi_id; 41 int func = PCI_FUNC(pdev->devfn); 42 size_t n; 43 44 dmi_id = dmi_first_match(dmi_list); 45 if (!dmi_id) 46 return -ENODEV; 47 48 dmi_data = dmi_id->driver_data; 49 func_data = dmi_data->func; 50 51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 52 if (func_data->func == func) 53 return func_data->phy_addr; 54 55 return -ENODEV; 56 } 57 58 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, 59 int phyreg, u32 mask, u32 val) 60 { 61 unsigned int retries = 10; 62 int val_rd; 63 64 do { 65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); 66 if ((val_rd & mask) == (val & mask)) 67 return 0; 68 udelay(POLL_DELAY_US); 69 } while (--retries); 70 71 return -ETIMEDOUT; 72 } 73 74 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 75 { 76 struct intel_priv_data *intel_priv = priv_data; 77 struct stmmac_priv *priv = netdev_priv(ndev); 78 int serdes_phy_addr = 0; 79 u32 data = 0; 80 81 if (!intel_priv->mdio_adhoc_addr) 82 return 0; 83 84 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 85 86 /* assert clk_req */ 87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 88 data |= SERDES_PLL_CLK; 89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 90 91 /* check for clk_ack assertion */ 92 data = serdes_status_poll(priv, serdes_phy_addr, 93 SERDES_GSR0, 94 SERDES_PLL_CLK, 95 SERDES_PLL_CLK); 96 97 if (data) { 98 dev_err(priv->device, "Serdes PLL clk request timeout\n"); 99 return data; 100 } 101 102 /* assert lane reset */ 103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 104 data |= SERDES_RST; 105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 106 107 /* check for assert lane reset reflection */ 108 data = serdes_status_poll(priv, serdes_phy_addr, 109 SERDES_GSR0, 110 SERDES_RST, 111 SERDES_RST); 112 113 if (data) { 114 dev_err(priv->device, "Serdes assert lane reset timeout\n"); 115 return data; 116 } 117 118 /* move power state to P0 */ 119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 120 121 data &= ~SERDES_PWR_ST_MASK; 122 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; 123 124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 125 126 /* Check for P0 state */ 127 data = serdes_status_poll(priv, serdes_phy_addr, 128 SERDES_GSR0, 129 SERDES_PWR_ST_MASK, 130 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); 131 132 if (data) { 133 dev_err(priv->device, "Serdes power state P0 timeout.\n"); 134 return data; 135 } 136 137 return 0; 138 } 139 140 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 141 { 142 struct intel_priv_data *intel_priv = intel_data; 143 struct stmmac_priv *priv = netdev_priv(ndev); 144 int serdes_phy_addr = 0; 145 u32 data = 0; 146 147 if (!intel_priv->mdio_adhoc_addr) 148 return; 149 150 serdes_phy_addr = intel_priv->mdio_adhoc_addr; 151 152 /* move power state to P3 */ 153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 154 155 data &= ~SERDES_PWR_ST_MASK; 156 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; 157 158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 159 160 /* Check for P3 state */ 161 data = serdes_status_poll(priv, serdes_phy_addr, 162 SERDES_GSR0, 163 SERDES_PWR_ST_MASK, 164 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); 165 166 if (data) { 167 dev_err(priv->device, "Serdes power state P3 timeout\n"); 168 return; 169 } 170 171 /* de-assert clk_req */ 172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 173 data &= ~SERDES_PLL_CLK; 174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 175 176 /* check for clk_ack de-assert */ 177 data = serdes_status_poll(priv, serdes_phy_addr, 178 SERDES_GSR0, 179 SERDES_PLL_CLK, 180 (u32)~SERDES_PLL_CLK); 181 182 if (data) { 183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); 184 return; 185 } 186 187 /* de-assert lane reset */ 188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); 189 data &= ~SERDES_RST; 190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); 191 192 /* check for de-assert lane reset reflection */ 193 data = serdes_status_poll(priv, serdes_phy_addr, 194 SERDES_GSR0, 195 SERDES_RST, 196 (u32)~SERDES_RST); 197 198 if (data) { 199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); 200 return; 201 } 202 } 203 204 static void common_default_data(struct plat_stmmacenet_data *plat) 205 { 206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 207 plat->has_gmac = 1; 208 plat->force_sf_dma_mode = 1; 209 210 plat->mdio_bus_data->needs_reset = true; 211 212 /* Set default value for multicast hash bins */ 213 plat->multicast_filter_bins = HASH_TABLE_SIZE; 214 215 /* Set default value for unicast filter entries */ 216 plat->unicast_filter_entries = 1; 217 218 /* Set the maxmtu to a default of JUMBO_LEN */ 219 plat->maxmtu = JUMBO_LEN; 220 221 /* Set default number of RX and TX queues to use */ 222 plat->tx_queues_to_use = 1; 223 plat->rx_queues_to_use = 1; 224 225 /* Disable Priority config by default */ 226 plat->tx_queues_cfg[0].use_prio = false; 227 plat->rx_queues_cfg[0].use_prio = false; 228 229 /* Disable RX queues routing by default */ 230 plat->rx_queues_cfg[0].pkt_route = 0x0; 231 } 232 233 static int intel_mgbe_common_data(struct pci_dev *pdev, 234 struct plat_stmmacenet_data *plat) 235 { 236 int ret; 237 int i; 238 239 plat->phy_addr = -1; 240 plat->clk_csr = 5; 241 plat->has_gmac = 0; 242 plat->has_gmac4 = 1; 243 plat->force_sf_dma_mode = 0; 244 plat->tso_en = 1; 245 246 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 247 248 for (i = 0; i < plat->rx_queues_to_use; i++) { 249 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 250 plat->rx_queues_cfg[i].chan = i; 251 252 /* Disable Priority config by default */ 253 plat->rx_queues_cfg[i].use_prio = false; 254 255 /* Disable RX queues routing by default */ 256 plat->rx_queues_cfg[i].pkt_route = 0x0; 257 } 258 259 for (i = 0; i < plat->tx_queues_to_use; i++) { 260 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 261 262 /* Disable Priority config by default */ 263 plat->tx_queues_cfg[i].use_prio = false; 264 } 265 266 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 267 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 268 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 269 270 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 271 plat->tx_queues_cfg[0].weight = 0x09; 272 plat->tx_queues_cfg[1].weight = 0x0A; 273 plat->tx_queues_cfg[2].weight = 0x0B; 274 plat->tx_queues_cfg[3].weight = 0x0C; 275 plat->tx_queues_cfg[4].weight = 0x0D; 276 plat->tx_queues_cfg[5].weight = 0x0E; 277 plat->tx_queues_cfg[6].weight = 0x0F; 278 plat->tx_queues_cfg[7].weight = 0x10; 279 280 plat->dma_cfg->pbl = 32; 281 plat->dma_cfg->pblx8 = true; 282 plat->dma_cfg->fixed_burst = 0; 283 plat->dma_cfg->mixed_burst = 0; 284 plat->dma_cfg->aal = 0; 285 286 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 287 GFP_KERNEL); 288 if (!plat->axi) 289 return -ENOMEM; 290 291 plat->axi->axi_lpi_en = 0; 292 plat->axi->axi_xit_frm = 0; 293 plat->axi->axi_wr_osr_lmt = 1; 294 plat->axi->axi_rd_osr_lmt = 1; 295 plat->axi->axi_blen[0] = 4; 296 plat->axi->axi_blen[1] = 8; 297 plat->axi->axi_blen[2] = 16; 298 299 plat->ptp_max_adj = plat->clk_ptp_rate; 300 plat->eee_usecs_rate = plat->clk_ptp_rate; 301 302 /* Set system clock */ 303 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 304 "stmmac-clk", NULL, 0, 305 plat->clk_ptp_rate); 306 307 if (IS_ERR(plat->stmmac_clk)) { 308 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 309 plat->stmmac_clk = NULL; 310 } 311 312 ret = clk_prepare_enable(plat->stmmac_clk); 313 if (ret) { 314 clk_unregister_fixed_rate(plat->stmmac_clk); 315 return ret; 316 } 317 318 /* Set default value for multicast hash bins */ 319 plat->multicast_filter_bins = HASH_TABLE_SIZE; 320 321 /* Set default value for unicast filter entries */ 322 plat->unicast_filter_entries = 1; 323 324 /* Set the maxmtu to a default of JUMBO_LEN */ 325 plat->maxmtu = JUMBO_LEN; 326 327 plat->vlan_fail_q_en = true; 328 329 /* Use the last Rx queue */ 330 plat->vlan_fail_q = plat->rx_queues_to_use - 1; 331 332 return 0; 333 } 334 335 static int ehl_common_data(struct pci_dev *pdev, 336 struct plat_stmmacenet_data *plat) 337 { 338 plat->rx_queues_to_use = 8; 339 plat->tx_queues_to_use = 8; 340 plat->clk_ptp_rate = 200000000; 341 342 return intel_mgbe_common_data(pdev, plat); 343 } 344 345 static int ehl_sgmii_data(struct pci_dev *pdev, 346 struct plat_stmmacenet_data *plat) 347 { 348 plat->bus_id = 1; 349 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 350 351 plat->serdes_powerup = intel_serdes_powerup; 352 plat->serdes_powerdown = intel_serdes_powerdown; 353 354 return ehl_common_data(pdev, plat); 355 } 356 357 static struct stmmac_pci_info ehl_sgmii1g_info = { 358 .setup = ehl_sgmii_data, 359 }; 360 361 static int ehl_rgmii_data(struct pci_dev *pdev, 362 struct plat_stmmacenet_data *plat) 363 { 364 plat->bus_id = 1; 365 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 366 367 return ehl_common_data(pdev, plat); 368 } 369 370 static struct stmmac_pci_info ehl_rgmii1g_info = { 371 .setup = ehl_rgmii_data, 372 }; 373 374 static int ehl_pse0_common_data(struct pci_dev *pdev, 375 struct plat_stmmacenet_data *plat) 376 { 377 plat->bus_id = 2; 378 plat->addr64 = 32; 379 return ehl_common_data(pdev, plat); 380 } 381 382 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 383 struct plat_stmmacenet_data *plat) 384 { 385 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 386 return ehl_pse0_common_data(pdev, plat); 387 } 388 389 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { 390 .setup = ehl_pse0_rgmii1g_data, 391 }; 392 393 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 394 struct plat_stmmacenet_data *plat) 395 { 396 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 397 plat->serdes_powerup = intel_serdes_powerup; 398 plat->serdes_powerdown = intel_serdes_powerdown; 399 return ehl_pse0_common_data(pdev, plat); 400 } 401 402 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { 403 .setup = ehl_pse0_sgmii1g_data, 404 }; 405 406 static int ehl_pse1_common_data(struct pci_dev *pdev, 407 struct plat_stmmacenet_data *plat) 408 { 409 plat->bus_id = 3; 410 plat->addr64 = 32; 411 return ehl_common_data(pdev, plat); 412 } 413 414 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 415 struct plat_stmmacenet_data *plat) 416 { 417 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 418 return ehl_pse1_common_data(pdev, plat); 419 } 420 421 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { 422 .setup = ehl_pse1_rgmii1g_data, 423 }; 424 425 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 426 struct plat_stmmacenet_data *plat) 427 { 428 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 429 plat->serdes_powerup = intel_serdes_powerup; 430 plat->serdes_powerdown = intel_serdes_powerdown; 431 return ehl_pse1_common_data(pdev, plat); 432 } 433 434 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { 435 .setup = ehl_pse1_sgmii1g_data, 436 }; 437 438 static int tgl_common_data(struct pci_dev *pdev, 439 struct plat_stmmacenet_data *plat) 440 { 441 plat->rx_queues_to_use = 6; 442 plat->tx_queues_to_use = 4; 443 plat->clk_ptp_rate = 200000000; 444 445 return intel_mgbe_common_data(pdev, plat); 446 } 447 448 static int tgl_sgmii_data(struct pci_dev *pdev, 449 struct plat_stmmacenet_data *plat) 450 { 451 plat->bus_id = 1; 452 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 453 plat->serdes_powerup = intel_serdes_powerup; 454 plat->serdes_powerdown = intel_serdes_powerdown; 455 return tgl_common_data(pdev, plat); 456 } 457 458 static struct stmmac_pci_info tgl_sgmii1g_info = { 459 .setup = tgl_sgmii_data, 460 }; 461 462 static int adls_sgmii_data(struct pci_dev *pdev, 463 struct plat_stmmacenet_data *plat) 464 { 465 plat->bus_id = 1; 466 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 467 468 /* SerDes power up and power down are done in BIOS for ADL */ 469 470 return tgl_common_data(pdev, plat); 471 } 472 473 static struct stmmac_pci_info adls_sgmii1g_info = { 474 .setup = adls_sgmii_data, 475 }; 476 477 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 478 { 479 .func = 6, 480 .phy_addr = 1, 481 }, 482 }; 483 484 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 485 .func = galileo_stmmac_func_data, 486 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 487 }; 488 489 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 490 { 491 .func = 6, 492 .phy_addr = 1, 493 }, 494 { 495 .func = 7, 496 .phy_addr = 1, 497 }, 498 }; 499 500 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 501 .func = iot2040_stmmac_func_data, 502 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 503 }; 504 505 static const struct dmi_system_id quark_pci_dmi[] = { 506 { 507 .matches = { 508 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 509 }, 510 .driver_data = (void *)&galileo_stmmac_dmi_data, 511 }, 512 { 513 .matches = { 514 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 515 }, 516 .driver_data = (void *)&galileo_stmmac_dmi_data, 517 }, 518 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 519 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 520 * has only one pci network device while other asset tags are 521 * for IOT2040 which has two. 522 */ 523 { 524 .matches = { 525 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 526 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 527 "6ES7647-0AA00-0YA2"), 528 }, 529 .driver_data = (void *)&galileo_stmmac_dmi_data, 530 }, 531 { 532 .matches = { 533 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 534 }, 535 .driver_data = (void *)&iot2040_stmmac_dmi_data, 536 }, 537 {} 538 }; 539 540 static int quark_default_data(struct pci_dev *pdev, 541 struct plat_stmmacenet_data *plat) 542 { 543 int ret; 544 545 /* Set common default data first */ 546 common_default_data(plat); 547 548 /* Refuse to load the driver and register net device if MAC controller 549 * does not connect to any PHY interface. 550 */ 551 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 552 if (ret < 0) { 553 /* Return error to the caller on DMI enabled boards. */ 554 if (dmi_get_system_info(DMI_BOARD_NAME)) 555 return ret; 556 557 /* Galileo boards with old firmware don't support DMI. We always 558 * use 1 here as PHY address, so at least the first found MAC 559 * controller would be probed. 560 */ 561 ret = 1; 562 } 563 564 plat->bus_id = pci_dev_id(pdev); 565 plat->phy_addr = ret; 566 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 567 568 plat->dma_cfg->pbl = 16; 569 plat->dma_cfg->pblx8 = true; 570 plat->dma_cfg->fixed_burst = 1; 571 /* AXI (TODO) */ 572 573 return 0; 574 } 575 576 static const struct stmmac_pci_info quark_info = { 577 .setup = quark_default_data, 578 }; 579 580 /** 581 * intel_eth_pci_probe 582 * 583 * @pdev: pci device pointer 584 * @id: pointer to table of device id/id's. 585 * 586 * Description: This probing function gets called for all PCI devices which 587 * match the ID table and are not "owned" by other driver yet. This function 588 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 589 * matches the device. The probe functions returns zero when the driver choose 590 * to take "ownership" of the device or an error code(-ve no) otherwise. 591 */ 592 static int intel_eth_pci_probe(struct pci_dev *pdev, 593 const struct pci_device_id *id) 594 { 595 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 596 struct intel_priv_data *intel_priv; 597 struct plat_stmmacenet_data *plat; 598 struct stmmac_resources res; 599 int ret; 600 601 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); 602 if (!intel_priv) 603 return -ENOMEM; 604 605 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 606 if (!plat) 607 return -ENOMEM; 608 609 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 610 sizeof(*plat->mdio_bus_data), 611 GFP_KERNEL); 612 if (!plat->mdio_bus_data) 613 return -ENOMEM; 614 615 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 616 GFP_KERNEL); 617 if (!plat->dma_cfg) 618 return -ENOMEM; 619 620 /* Enable pci device */ 621 ret = pci_enable_device(pdev); 622 if (ret) { 623 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 624 __func__); 625 return ret; 626 } 627 628 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 629 if (ret) 630 return ret; 631 632 pci_set_master(pdev); 633 634 plat->bsp_priv = intel_priv; 635 intel_priv->mdio_adhoc_addr = 0x15; 636 637 ret = info->setup(pdev, plat); 638 if (ret) 639 return ret; 640 641 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 642 if (ret < 0) 643 return ret; 644 645 memset(&res, 0, sizeof(res)); 646 res.addr = pcim_iomap_table(pdev)[0]; 647 res.wol_irq = pci_irq_vector(pdev, 0); 648 res.irq = pci_irq_vector(pdev, 0); 649 650 if (plat->eee_usecs_rate > 0) { 651 u32 tx_lpi_usec; 652 653 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; 654 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); 655 } 656 657 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); 658 if (ret) { 659 pci_free_irq_vectors(pdev); 660 clk_disable_unprepare(plat->stmmac_clk); 661 clk_unregister_fixed_rate(plat->stmmac_clk); 662 } 663 664 return ret; 665 } 666 667 /** 668 * intel_eth_pci_remove 669 * 670 * @pdev: platform device pointer 671 * Description: this function calls the main to free the net resources 672 * and releases the PCI resources. 673 */ 674 static void intel_eth_pci_remove(struct pci_dev *pdev) 675 { 676 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 677 struct stmmac_priv *priv = netdev_priv(ndev); 678 679 stmmac_dvr_remove(&pdev->dev); 680 681 pci_free_irq_vectors(pdev); 682 683 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 684 685 pcim_iounmap_regions(pdev, BIT(0)); 686 687 pci_disable_device(pdev); 688 } 689 690 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 691 { 692 struct pci_dev *pdev = to_pci_dev(dev); 693 int ret; 694 695 ret = stmmac_suspend(dev); 696 if (ret) 697 return ret; 698 699 ret = pci_save_state(pdev); 700 if (ret) 701 return ret; 702 703 pci_disable_device(pdev); 704 pci_wake_from_d3(pdev, true); 705 return 0; 706 } 707 708 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 709 { 710 struct pci_dev *pdev = to_pci_dev(dev); 711 int ret; 712 713 pci_restore_state(pdev); 714 pci_set_power_state(pdev, PCI_D0); 715 716 ret = pci_enable_device(pdev); 717 if (ret) 718 return ret; 719 720 pci_set_master(pdev); 721 722 return stmmac_resume(dev); 723 } 724 725 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 726 intel_eth_pci_resume); 727 728 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 729 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 730 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 731 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 732 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 733 * which are named PSE0 and PSE1 734 */ 735 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 736 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 737 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 738 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 739 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 740 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 741 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac 742 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2 743 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 744 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac 745 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad 746 747 static const struct pci_device_id intel_eth_pci_id_table[] = { 748 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, 749 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, 750 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, 751 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, 752 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, 753 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, 754 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, 755 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, 756 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, 757 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, 758 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) }, 759 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) }, 760 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) }, 761 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_info) }, 762 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_info) }, 763 {} 764 }; 765 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 766 767 static struct pci_driver intel_eth_pci_driver = { 768 .name = "intel-eth-pci", 769 .id_table = intel_eth_pci_id_table, 770 .probe = intel_eth_pci_probe, 771 .remove = intel_eth_pci_remove, 772 .driver = { 773 .pm = &intel_eth_pm_ops, 774 }, 775 }; 776 777 module_pci_driver(intel_eth_pci_driver); 778 779 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 780 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 781 MODULE_LICENSE("GPL v2"); 782