1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
3  */
4 
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include "dwmac-intel.h"
9 #include "dwmac4.h"
10 #include "stmmac.h"
11 #include "stmmac_ptp.h"
12 
13 struct intel_priv_data {
14 	int mdio_adhoc_addr;	/* mdio address for serdes & etc */
15 	unsigned long crossts_adj;
16 	bool is_pse;
17 };
18 
19 /* This struct is used to associate PCI Function of MAC controller on a board,
20  * discovered via DMI, with the address of PHY connected to the MAC. The
21  * negative value of the address means that MAC controller is not connected
22  * with PHY.
23  */
24 struct stmmac_pci_func_data {
25 	unsigned int func;
26 	int phy_addr;
27 };
28 
29 struct stmmac_pci_dmi_data {
30 	const struct stmmac_pci_func_data *func;
31 	size_t nfuncs;
32 };
33 
34 struct stmmac_pci_info {
35 	int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
36 };
37 
38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 				    const struct dmi_system_id *dmi_list)
40 {
41 	const struct stmmac_pci_func_data *func_data;
42 	const struct stmmac_pci_dmi_data *dmi_data;
43 	const struct dmi_system_id *dmi_id;
44 	int func = PCI_FUNC(pdev->devfn);
45 	size_t n;
46 
47 	dmi_id = dmi_first_match(dmi_list);
48 	if (!dmi_id)
49 		return -ENODEV;
50 
51 	dmi_data = dmi_id->driver_data;
52 	func_data = dmi_data->func;
53 
54 	for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 		if (func_data->func == func)
56 			return func_data->phy_addr;
57 
58 	return -ENODEV;
59 }
60 
61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
62 			      int phyreg, u32 mask, u32 val)
63 {
64 	unsigned int retries = 10;
65 	int val_rd;
66 
67 	do {
68 		val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
69 		if ((val_rd & mask) == (val & mask))
70 			return 0;
71 		udelay(POLL_DELAY_US);
72 	} while (--retries);
73 
74 	return -ETIMEDOUT;
75 }
76 
77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
78 {
79 	struct intel_priv_data *intel_priv = priv_data;
80 	struct stmmac_priv *priv = netdev_priv(ndev);
81 	int serdes_phy_addr = 0;
82 	u32 data = 0;
83 
84 	if (!intel_priv->mdio_adhoc_addr)
85 		return 0;
86 
87 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
88 
89 	/* Set the serdes rate and the PCLK rate */
90 	data = mdiobus_read(priv->mii, serdes_phy_addr,
91 			    SERDES_GCR0);
92 
93 	data &= ~SERDES_RATE_MASK;
94 	data &= ~SERDES_PCLK_MASK;
95 
96 	if (priv->plat->max_speed == 2500)
97 		data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
98 			SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
99 	else
100 		data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
101 			SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
102 
103 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
104 
105 	/* assert clk_req */
106 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
107 	data |= SERDES_PLL_CLK;
108 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
109 
110 	/* check for clk_ack assertion */
111 	data = serdes_status_poll(priv, serdes_phy_addr,
112 				  SERDES_GSR0,
113 				  SERDES_PLL_CLK,
114 				  SERDES_PLL_CLK);
115 
116 	if (data) {
117 		dev_err(priv->device, "Serdes PLL clk request timeout\n");
118 		return data;
119 	}
120 
121 	/* assert lane reset */
122 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
123 	data |= SERDES_RST;
124 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
125 
126 	/* check for assert lane reset reflection */
127 	data = serdes_status_poll(priv, serdes_phy_addr,
128 				  SERDES_GSR0,
129 				  SERDES_RST,
130 				  SERDES_RST);
131 
132 	if (data) {
133 		dev_err(priv->device, "Serdes assert lane reset timeout\n");
134 		return data;
135 	}
136 
137 	/*  move power state to P0 */
138 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
139 
140 	data &= ~SERDES_PWR_ST_MASK;
141 	data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
142 
143 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
144 
145 	/* Check for P0 state */
146 	data = serdes_status_poll(priv, serdes_phy_addr,
147 				  SERDES_GSR0,
148 				  SERDES_PWR_ST_MASK,
149 				  SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
150 
151 	if (data) {
152 		dev_err(priv->device, "Serdes power state P0 timeout.\n");
153 		return data;
154 	}
155 
156 	/* PSE only - ungate SGMII PHY Rx Clock */
157 	if (intel_priv->is_pse)
158 		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
159 			       0, SERDES_PHY_RX_CLK);
160 
161 	return 0;
162 }
163 
164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
165 {
166 	struct intel_priv_data *intel_priv = intel_data;
167 	struct stmmac_priv *priv = netdev_priv(ndev);
168 	int serdes_phy_addr = 0;
169 	u32 data = 0;
170 
171 	if (!intel_priv->mdio_adhoc_addr)
172 		return;
173 
174 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
175 
176 	/* PSE only - gate SGMII PHY Rx Clock */
177 	if (intel_priv->is_pse)
178 		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
179 			       SERDES_PHY_RX_CLK, 0);
180 
181 	/*  move power state to P3 */
182 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
183 
184 	data &= ~SERDES_PWR_ST_MASK;
185 	data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
186 
187 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
188 
189 	/* Check for P3 state */
190 	data = serdes_status_poll(priv, serdes_phy_addr,
191 				  SERDES_GSR0,
192 				  SERDES_PWR_ST_MASK,
193 				  SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
194 
195 	if (data) {
196 		dev_err(priv->device, "Serdes power state P3 timeout\n");
197 		return;
198 	}
199 
200 	/* de-assert clk_req */
201 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
202 	data &= ~SERDES_PLL_CLK;
203 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
204 
205 	/* check for clk_ack de-assert */
206 	data = serdes_status_poll(priv, serdes_phy_addr,
207 				  SERDES_GSR0,
208 				  SERDES_PLL_CLK,
209 				  (u32)~SERDES_PLL_CLK);
210 
211 	if (data) {
212 		dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
213 		return;
214 	}
215 
216 	/* de-assert lane reset */
217 	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
218 	data &= ~SERDES_RST;
219 	mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
220 
221 	/* check for de-assert lane reset reflection */
222 	data = serdes_status_poll(priv, serdes_phy_addr,
223 				  SERDES_GSR0,
224 				  SERDES_RST,
225 				  (u32)~SERDES_RST);
226 
227 	if (data) {
228 		dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
229 		return;
230 	}
231 }
232 
233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
234 {
235 	struct intel_priv_data *intel_priv = intel_data;
236 	struct stmmac_priv *priv = netdev_priv(ndev);
237 	int serdes_phy_addr = 0;
238 	u32 data = 0;
239 
240 	serdes_phy_addr = intel_priv->mdio_adhoc_addr;
241 
242 	/* Determine the link speed mode: 2.5Gbps/1Gbps */
243 	data = mdiobus_read(priv->mii, serdes_phy_addr,
244 			    SERDES_GCR);
245 
246 	if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
247 	    SERDES_LINK_MODE_2G5) {
248 		dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
249 		priv->plat->max_speed = 2500;
250 		priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 		priv->plat->mdio_bus_data->xpcs_an_inband = false;
252 	} else {
253 		priv->plat->max_speed = 1000;
254 		priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
255 		priv->plat->mdio_bus_data->xpcs_an_inband = true;
256 	}
257 }
258 
259 /* Program PTP Clock Frequency for different variant of
260  * Intel mGBE that has slightly different GPO mapping
261  */
262 static void intel_mgbe_ptp_clk_freq_config(void *npriv)
263 {
264 	struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
265 	struct intel_priv_data *intel_priv;
266 	u32 gpio_value;
267 
268 	intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
269 
270 	gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
271 
272 	if (intel_priv->is_pse) {
273 		/* For PSE GbE, use 200MHz */
274 		gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
275 		gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
276 	} else {
277 		/* For PCH GbE, use 200MHz */
278 		gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
279 		gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
280 	}
281 
282 	writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
283 }
284 
285 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
286 			u64 *art_time)
287 {
288 	u64 ns;
289 
290 	ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
291 	ns <<= GMAC4_ART_TIME_SHIFT;
292 	ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
293 	ns <<= GMAC4_ART_TIME_SHIFT;
294 	ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
295 	ns <<= GMAC4_ART_TIME_SHIFT;
296 	ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
297 
298 	*art_time = ns;
299 }
300 
301 static int intel_crosststamp(ktime_t *device,
302 			     struct system_counterval_t *system,
303 			     void *ctx)
304 {
305 	struct intel_priv_data *intel_priv;
306 
307 	struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
308 	void __iomem *ptpaddr = priv->ptpaddr;
309 	void __iomem *ioaddr = priv->hw->pcsr;
310 	unsigned long flags;
311 	u64 art_time = 0;
312 	u64 ptp_time = 0;
313 	u32 num_snapshot;
314 	u32 gpio_value;
315 	u32 acr_value;
316 	int ret;
317 	u32 v;
318 	int i;
319 
320 	if (!boot_cpu_has(X86_FEATURE_ART))
321 		return -EOPNOTSUPP;
322 
323 	intel_priv = priv->plat->bsp_priv;
324 
325 	/* Both internal crosstimestamping and external triggered event
326 	 * timestamping cannot be run concurrently.
327 	 */
328 	if (priv->plat->ext_snapshot_en)
329 		return -EBUSY;
330 
331 	mutex_lock(&priv->aux_ts_lock);
332 	/* Enable Internal snapshot trigger */
333 	acr_value = readl(ptpaddr + PTP_ACR);
334 	acr_value &= ~PTP_ACR_MASK;
335 	switch (priv->plat->int_snapshot_num) {
336 	case AUX_SNAPSHOT0:
337 		acr_value |= PTP_ACR_ATSEN0;
338 		break;
339 	case AUX_SNAPSHOT1:
340 		acr_value |= PTP_ACR_ATSEN1;
341 		break;
342 	case AUX_SNAPSHOT2:
343 		acr_value |= PTP_ACR_ATSEN2;
344 		break;
345 	case AUX_SNAPSHOT3:
346 		acr_value |= PTP_ACR_ATSEN3;
347 		break;
348 	default:
349 		mutex_unlock(&priv->aux_ts_lock);
350 		return -EINVAL;
351 	}
352 	writel(acr_value, ptpaddr + PTP_ACR);
353 
354 	/* Clear FIFO */
355 	acr_value = readl(ptpaddr + PTP_ACR);
356 	acr_value |= PTP_ACR_ATSFC;
357 	writel(acr_value, ptpaddr + PTP_ACR);
358 	/* Release the mutex */
359 	mutex_unlock(&priv->aux_ts_lock);
360 
361 	/* Trigger Internal snapshot signal
362 	 * Create a rising edge by just toggle the GPO1 to low
363 	 * and back to high.
364 	 */
365 	gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
366 	gpio_value &= ~GMAC_GPO1;
367 	writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
368 	gpio_value |= GMAC_GPO1;
369 	writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
370 
371 	/* Poll for time sync operation done */
372 	ret = readl_poll_timeout(priv->ioaddr + GMAC_INT_STATUS, v,
373 				 (v & GMAC_INT_TSIE), 100, 10000);
374 
375 	if (ret == -ETIMEDOUT) {
376 		pr_err("%s: Wait for time sync operation timeout\n", __func__);
377 		return ret;
378 	}
379 
380 	num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
381 			GMAC_TIMESTAMP_ATSNS_MASK) >>
382 			GMAC_TIMESTAMP_ATSNS_SHIFT;
383 
384 	/* Repeat until the timestamps are from the FIFO last segment */
385 	for (i = 0; i < num_snapshot; i++) {
386 		read_lock_irqsave(&priv->ptp_lock, flags);
387 		stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
388 		*device = ns_to_ktime(ptp_time);
389 		read_unlock_irqrestore(&priv->ptp_lock, flags);
390 		get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
391 		*system = convert_art_to_tsc(art_time);
392 	}
393 
394 	system->cycles *= intel_priv->crossts_adj;
395 
396 	return 0;
397 }
398 
399 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
400 				       int base)
401 {
402 	if (boot_cpu_has(X86_FEATURE_ART)) {
403 		unsigned int art_freq;
404 
405 		/* On systems that support ART, ART frequency can be obtained
406 		 * from ECX register of CPUID leaf (0x15).
407 		 */
408 		art_freq = cpuid_ecx(ART_CPUID_LEAF);
409 		do_div(art_freq, base);
410 		intel_priv->crossts_adj = art_freq;
411 	}
412 }
413 
414 static void common_default_data(struct plat_stmmacenet_data *plat)
415 {
416 	plat->clk_csr = 2;	/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
417 	plat->has_gmac = 1;
418 	plat->force_sf_dma_mode = 1;
419 
420 	plat->mdio_bus_data->needs_reset = true;
421 
422 	/* Set default value for multicast hash bins */
423 	plat->multicast_filter_bins = HASH_TABLE_SIZE;
424 
425 	/* Set default value for unicast filter entries */
426 	plat->unicast_filter_entries = 1;
427 
428 	/* Set the maxmtu to a default of JUMBO_LEN */
429 	plat->maxmtu = JUMBO_LEN;
430 
431 	/* Set default number of RX and TX queues to use */
432 	plat->tx_queues_to_use = 1;
433 	plat->rx_queues_to_use = 1;
434 
435 	/* Disable Priority config by default */
436 	plat->tx_queues_cfg[0].use_prio = false;
437 	plat->rx_queues_cfg[0].use_prio = false;
438 
439 	/* Disable RX queues routing by default */
440 	plat->rx_queues_cfg[0].pkt_route = 0x0;
441 }
442 
443 static int intel_mgbe_common_data(struct pci_dev *pdev,
444 				  struct plat_stmmacenet_data *plat)
445 {
446 	char clk_name[20];
447 	int ret;
448 	int i;
449 
450 	plat->pdev = pdev;
451 	plat->phy_addr = -1;
452 	plat->clk_csr = 5;
453 	plat->has_gmac = 0;
454 	plat->has_gmac4 = 1;
455 	plat->force_sf_dma_mode = 0;
456 	plat->tso_en = 1;
457 	plat->sph_disable = 1;
458 
459 	/* Multiplying factor to the clk_eee_i clock time
460 	 * period to make it closer to 100 ns. This value
461 	 * should be programmed such that the clk_eee_time_period *
462 	 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
463 	 * clk_eee frequency is 19.2Mhz
464 	 * clk_eee_time_period is 52ns
465 	 * 52ns * (1 + 1) = 104ns
466 	 * MULT_FACT_100NS = 1
467 	 */
468 	plat->mult_fact_100ns = 1;
469 
470 	plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
471 
472 	for (i = 0; i < plat->rx_queues_to_use; i++) {
473 		plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
474 		plat->rx_queues_cfg[i].chan = i;
475 
476 		/* Disable Priority config by default */
477 		plat->rx_queues_cfg[i].use_prio = false;
478 
479 		/* Disable RX queues routing by default */
480 		plat->rx_queues_cfg[i].pkt_route = 0x0;
481 	}
482 
483 	for (i = 0; i < plat->tx_queues_to_use; i++) {
484 		plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
485 
486 		/* Disable Priority config by default */
487 		plat->tx_queues_cfg[i].use_prio = false;
488 		/* Default TX Q0 to use TSO and rest TXQ for TBS */
489 		if (i > 0)
490 			plat->tx_queues_cfg[i].tbs_en = 1;
491 	}
492 
493 	/* FIFO size is 4096 bytes for 1 tx/rx queue */
494 	plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
495 	plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
496 
497 	plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
498 	plat->tx_queues_cfg[0].weight = 0x09;
499 	plat->tx_queues_cfg[1].weight = 0x0A;
500 	plat->tx_queues_cfg[2].weight = 0x0B;
501 	plat->tx_queues_cfg[3].weight = 0x0C;
502 	plat->tx_queues_cfg[4].weight = 0x0D;
503 	plat->tx_queues_cfg[5].weight = 0x0E;
504 	plat->tx_queues_cfg[6].weight = 0x0F;
505 	plat->tx_queues_cfg[7].weight = 0x10;
506 
507 	plat->dma_cfg->pbl = 32;
508 	plat->dma_cfg->pblx8 = true;
509 	plat->dma_cfg->fixed_burst = 0;
510 	plat->dma_cfg->mixed_burst = 0;
511 	plat->dma_cfg->aal = 0;
512 	plat->dma_cfg->dche = true;
513 
514 	plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
515 				 GFP_KERNEL);
516 	if (!plat->axi)
517 		return -ENOMEM;
518 
519 	plat->axi->axi_lpi_en = 0;
520 	plat->axi->axi_xit_frm = 0;
521 	plat->axi->axi_wr_osr_lmt = 1;
522 	plat->axi->axi_rd_osr_lmt = 1;
523 	plat->axi->axi_blen[0] = 4;
524 	plat->axi->axi_blen[1] = 8;
525 	plat->axi->axi_blen[2] = 16;
526 
527 	plat->ptp_max_adj = plat->clk_ptp_rate;
528 	plat->eee_usecs_rate = plat->clk_ptp_rate;
529 
530 	/* Set system clock */
531 	sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
532 
533 	plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
534 						   clk_name, NULL, 0,
535 						   plat->clk_ptp_rate);
536 
537 	if (IS_ERR(plat->stmmac_clk)) {
538 		dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
539 		plat->stmmac_clk = NULL;
540 	}
541 
542 	ret = clk_prepare_enable(plat->stmmac_clk);
543 	if (ret) {
544 		clk_unregister_fixed_rate(plat->stmmac_clk);
545 		return ret;
546 	}
547 
548 	plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
549 
550 	/* Set default value for multicast hash bins */
551 	plat->multicast_filter_bins = HASH_TABLE_SIZE;
552 
553 	/* Set default value for unicast filter entries */
554 	plat->unicast_filter_entries = 1;
555 
556 	/* Set the maxmtu to a default of JUMBO_LEN */
557 	plat->maxmtu = JUMBO_LEN;
558 
559 	plat->vlan_fail_q_en = true;
560 
561 	/* Use the last Rx queue */
562 	plat->vlan_fail_q = plat->rx_queues_to_use - 1;
563 
564 	/* Intel mgbe SGMII interface uses pcs-xcps */
565 	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII) {
566 		plat->mdio_bus_data->has_xpcs = true;
567 		plat->mdio_bus_data->xpcs_an_inband = true;
568 	}
569 
570 	/* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
571 	plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
572 	plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
573 
574 	plat->int_snapshot_num = AUX_SNAPSHOT1;
575 	plat->ext_snapshot_num = AUX_SNAPSHOT0;
576 
577 	plat->has_crossts = true;
578 	plat->crosststamp = intel_crosststamp;
579 
580 	/* Setup MSI vector offset specific to Intel mGbE controller */
581 	plat->msi_mac_vec = 29;
582 	plat->msi_lpi_vec = 28;
583 	plat->msi_sfty_ce_vec = 27;
584 	plat->msi_sfty_ue_vec = 26;
585 	plat->msi_rx_base_vec = 0;
586 	plat->msi_tx_base_vec = 1;
587 
588 	return 0;
589 }
590 
591 static int ehl_common_data(struct pci_dev *pdev,
592 			   struct plat_stmmacenet_data *plat)
593 {
594 	plat->rx_queues_to_use = 8;
595 	plat->tx_queues_to_use = 8;
596 	plat->clk_ptp_rate = 200000000;
597 	plat->use_phy_wol = 1;
598 
599 	plat->safety_feat_cfg->tsoee = 1;
600 	plat->safety_feat_cfg->mrxpee = 1;
601 	plat->safety_feat_cfg->mestee = 1;
602 	plat->safety_feat_cfg->mrxee = 1;
603 	plat->safety_feat_cfg->mtxee = 1;
604 	plat->safety_feat_cfg->epsi = 0;
605 	plat->safety_feat_cfg->edpp = 0;
606 	plat->safety_feat_cfg->prtyen = 0;
607 	plat->safety_feat_cfg->tmouten = 0;
608 
609 	return intel_mgbe_common_data(pdev, plat);
610 }
611 
612 static int ehl_sgmii_data(struct pci_dev *pdev,
613 			  struct plat_stmmacenet_data *plat)
614 {
615 	plat->bus_id = 1;
616 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
617 	plat->speed_mode_2500 = intel_speed_mode_2500;
618 	plat->serdes_powerup = intel_serdes_powerup;
619 	plat->serdes_powerdown = intel_serdes_powerdown;
620 
621 	return ehl_common_data(pdev, plat);
622 }
623 
624 static struct stmmac_pci_info ehl_sgmii1g_info = {
625 	.setup = ehl_sgmii_data,
626 };
627 
628 static int ehl_rgmii_data(struct pci_dev *pdev,
629 			  struct plat_stmmacenet_data *plat)
630 {
631 	plat->bus_id = 1;
632 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
633 
634 	return ehl_common_data(pdev, plat);
635 }
636 
637 static struct stmmac_pci_info ehl_rgmii1g_info = {
638 	.setup = ehl_rgmii_data,
639 };
640 
641 static int ehl_pse0_common_data(struct pci_dev *pdev,
642 				struct plat_stmmacenet_data *plat)
643 {
644 	struct intel_priv_data *intel_priv = plat->bsp_priv;
645 
646 	intel_priv->is_pse = true;
647 	plat->bus_id = 2;
648 	plat->addr64 = 32;
649 
650 	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
651 
652 	return ehl_common_data(pdev, plat);
653 }
654 
655 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
656 				 struct plat_stmmacenet_data *plat)
657 {
658 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
659 	return ehl_pse0_common_data(pdev, plat);
660 }
661 
662 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
663 	.setup = ehl_pse0_rgmii1g_data,
664 };
665 
666 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
667 				 struct plat_stmmacenet_data *plat)
668 {
669 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
670 	plat->speed_mode_2500 = intel_speed_mode_2500;
671 	plat->serdes_powerup = intel_serdes_powerup;
672 	plat->serdes_powerdown = intel_serdes_powerdown;
673 	return ehl_pse0_common_data(pdev, plat);
674 }
675 
676 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
677 	.setup = ehl_pse0_sgmii1g_data,
678 };
679 
680 static int ehl_pse1_common_data(struct pci_dev *pdev,
681 				struct plat_stmmacenet_data *plat)
682 {
683 	struct intel_priv_data *intel_priv = plat->bsp_priv;
684 
685 	intel_priv->is_pse = true;
686 	plat->bus_id = 3;
687 	plat->addr64 = 32;
688 
689 	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
690 
691 	return ehl_common_data(pdev, plat);
692 }
693 
694 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
695 				 struct plat_stmmacenet_data *plat)
696 {
697 	plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
698 	return ehl_pse1_common_data(pdev, plat);
699 }
700 
701 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
702 	.setup = ehl_pse1_rgmii1g_data,
703 };
704 
705 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
706 				 struct plat_stmmacenet_data *plat)
707 {
708 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
709 	plat->speed_mode_2500 = intel_speed_mode_2500;
710 	plat->serdes_powerup = intel_serdes_powerup;
711 	plat->serdes_powerdown = intel_serdes_powerdown;
712 	return ehl_pse1_common_data(pdev, plat);
713 }
714 
715 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
716 	.setup = ehl_pse1_sgmii1g_data,
717 };
718 
719 static int tgl_common_data(struct pci_dev *pdev,
720 			   struct plat_stmmacenet_data *plat)
721 {
722 	plat->rx_queues_to_use = 6;
723 	plat->tx_queues_to_use = 4;
724 	plat->clk_ptp_rate = 200000000;
725 	plat->speed_mode_2500 = intel_speed_mode_2500;
726 
727 	plat->safety_feat_cfg->tsoee = 1;
728 	plat->safety_feat_cfg->mrxpee = 0;
729 	plat->safety_feat_cfg->mestee = 1;
730 	plat->safety_feat_cfg->mrxee = 1;
731 	plat->safety_feat_cfg->mtxee = 1;
732 	plat->safety_feat_cfg->epsi = 0;
733 	plat->safety_feat_cfg->edpp = 0;
734 	plat->safety_feat_cfg->prtyen = 0;
735 	plat->safety_feat_cfg->tmouten = 0;
736 
737 	return intel_mgbe_common_data(pdev, plat);
738 }
739 
740 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
741 			       struct plat_stmmacenet_data *plat)
742 {
743 	plat->bus_id = 1;
744 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
745 	plat->serdes_powerup = intel_serdes_powerup;
746 	plat->serdes_powerdown = intel_serdes_powerdown;
747 	return tgl_common_data(pdev, plat);
748 }
749 
750 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
751 	.setup = tgl_sgmii_phy0_data,
752 };
753 
754 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
755 			       struct plat_stmmacenet_data *plat)
756 {
757 	plat->bus_id = 2;
758 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
759 	plat->serdes_powerup = intel_serdes_powerup;
760 	plat->serdes_powerdown = intel_serdes_powerdown;
761 	return tgl_common_data(pdev, plat);
762 }
763 
764 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
765 	.setup = tgl_sgmii_phy1_data,
766 };
767 
768 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
769 				struct plat_stmmacenet_data *plat)
770 {
771 	plat->bus_id = 1;
772 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
773 
774 	/* SerDes power up and power down are done in BIOS for ADL */
775 
776 	return tgl_common_data(pdev, plat);
777 }
778 
779 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
780 	.setup = adls_sgmii_phy0_data,
781 };
782 
783 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
784 				struct plat_stmmacenet_data *plat)
785 {
786 	plat->bus_id = 2;
787 	plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
788 
789 	/* SerDes power up and power down are done in BIOS for ADL */
790 
791 	return tgl_common_data(pdev, plat);
792 }
793 
794 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
795 	.setup = adls_sgmii_phy1_data,
796 };
797 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
798 	{
799 		.func = 6,
800 		.phy_addr = 1,
801 	},
802 };
803 
804 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
805 	.func = galileo_stmmac_func_data,
806 	.nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
807 };
808 
809 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
810 	{
811 		.func = 6,
812 		.phy_addr = 1,
813 	},
814 	{
815 		.func = 7,
816 		.phy_addr = 1,
817 	},
818 };
819 
820 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
821 	.func = iot2040_stmmac_func_data,
822 	.nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
823 };
824 
825 static const struct dmi_system_id quark_pci_dmi[] = {
826 	{
827 		.matches = {
828 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
829 		},
830 		.driver_data = (void *)&galileo_stmmac_dmi_data,
831 	},
832 	{
833 		.matches = {
834 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
835 		},
836 		.driver_data = (void *)&galileo_stmmac_dmi_data,
837 	},
838 	/* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
839 	 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
840 	 * has only one pci network device while other asset tags are
841 	 * for IOT2040 which has two.
842 	 */
843 	{
844 		.matches = {
845 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
846 			DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
847 					"6ES7647-0AA00-0YA2"),
848 		},
849 		.driver_data = (void *)&galileo_stmmac_dmi_data,
850 	},
851 	{
852 		.matches = {
853 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
854 		},
855 		.driver_data = (void *)&iot2040_stmmac_dmi_data,
856 	},
857 	{}
858 };
859 
860 static int quark_default_data(struct pci_dev *pdev,
861 			      struct plat_stmmacenet_data *plat)
862 {
863 	int ret;
864 
865 	/* Set common default data first */
866 	common_default_data(plat);
867 
868 	/* Refuse to load the driver and register net device if MAC controller
869 	 * does not connect to any PHY interface.
870 	 */
871 	ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
872 	if (ret < 0) {
873 		/* Return error to the caller on DMI enabled boards. */
874 		if (dmi_get_system_info(DMI_BOARD_NAME))
875 			return ret;
876 
877 		/* Galileo boards with old firmware don't support DMI. We always
878 		 * use 1 here as PHY address, so at least the first found MAC
879 		 * controller would be probed.
880 		 */
881 		ret = 1;
882 	}
883 
884 	plat->bus_id = pci_dev_id(pdev);
885 	plat->phy_addr = ret;
886 	plat->phy_interface = PHY_INTERFACE_MODE_RMII;
887 
888 	plat->dma_cfg->pbl = 16;
889 	plat->dma_cfg->pblx8 = true;
890 	plat->dma_cfg->fixed_burst = 1;
891 	/* AXI (TODO) */
892 
893 	return 0;
894 }
895 
896 static const struct stmmac_pci_info quark_info = {
897 	.setup = quark_default_data,
898 };
899 
900 static int stmmac_config_single_msi(struct pci_dev *pdev,
901 				    struct plat_stmmacenet_data *plat,
902 				    struct stmmac_resources *res)
903 {
904 	int ret;
905 
906 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
907 	if (ret < 0) {
908 		dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
909 			 __func__);
910 		return ret;
911 	}
912 
913 	res->irq = pci_irq_vector(pdev, 0);
914 	res->wol_irq = res->irq;
915 	plat->multi_msi_en = 0;
916 	dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
917 		 __func__);
918 
919 	return 0;
920 }
921 
922 static int stmmac_config_multi_msi(struct pci_dev *pdev,
923 				   struct plat_stmmacenet_data *plat,
924 				   struct stmmac_resources *res)
925 {
926 	int ret;
927 	int i;
928 
929 	if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
930 	    plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
931 		dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
932 			 __func__);
933 		return -1;
934 	}
935 
936 	ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
937 				    PCI_IRQ_MSI | PCI_IRQ_MSIX);
938 	if (ret < 0) {
939 		dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
940 			 __func__);
941 		return ret;
942 	}
943 
944 	/* For RX MSI */
945 	for (i = 0; i < plat->rx_queues_to_use; i++) {
946 		res->rx_irq[i] = pci_irq_vector(pdev,
947 						plat->msi_rx_base_vec + i * 2);
948 	}
949 
950 	/* For TX MSI */
951 	for (i = 0; i < plat->tx_queues_to_use; i++) {
952 		res->tx_irq[i] = pci_irq_vector(pdev,
953 						plat->msi_tx_base_vec + i * 2);
954 	}
955 
956 	if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
957 		res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
958 	if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
959 		res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
960 	if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
961 		res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
962 	if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
963 		res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
964 	if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
965 		res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
966 
967 	plat->multi_msi_en = 1;
968 	dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
969 
970 	return 0;
971 }
972 
973 /**
974  * intel_eth_pci_probe
975  *
976  * @pdev: pci device pointer
977  * @id: pointer to table of device id/id's.
978  *
979  * Description: This probing function gets called for all PCI devices which
980  * match the ID table and are not "owned" by other driver yet. This function
981  * gets passed a "struct pci_dev *" for each device whose entry in the ID table
982  * matches the device. The probe functions returns zero when the driver choose
983  * to take "ownership" of the device or an error code(-ve no) otherwise.
984  */
985 static int intel_eth_pci_probe(struct pci_dev *pdev,
986 			       const struct pci_device_id *id)
987 {
988 	struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
989 	struct intel_priv_data *intel_priv;
990 	struct plat_stmmacenet_data *plat;
991 	struct stmmac_resources res;
992 	int ret;
993 
994 	intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
995 	if (!intel_priv)
996 		return -ENOMEM;
997 
998 	plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
999 	if (!plat)
1000 		return -ENOMEM;
1001 
1002 	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1003 					   sizeof(*plat->mdio_bus_data),
1004 					   GFP_KERNEL);
1005 	if (!plat->mdio_bus_data)
1006 		return -ENOMEM;
1007 
1008 	plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1009 				     GFP_KERNEL);
1010 	if (!plat->dma_cfg)
1011 		return -ENOMEM;
1012 
1013 	plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1014 					     sizeof(*plat->safety_feat_cfg),
1015 					     GFP_KERNEL);
1016 	if (!plat->safety_feat_cfg)
1017 		return -ENOMEM;
1018 
1019 	/* Enable pci device */
1020 	ret = pcim_enable_device(pdev);
1021 	if (ret) {
1022 		dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1023 			__func__);
1024 		return ret;
1025 	}
1026 
1027 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1028 	if (ret)
1029 		return ret;
1030 
1031 	pci_set_master(pdev);
1032 
1033 	plat->bsp_priv = intel_priv;
1034 	intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1035 	intel_priv->crossts_adj = 1;
1036 
1037 	/* Initialize all MSI vectors to invalid so that it can be set
1038 	 * according to platform data settings below.
1039 	 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1040 	 */
1041 	plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1042 	plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1043 	plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1044 	plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1045 	plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1046 	plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1047 	plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1048 
1049 	ret = info->setup(pdev, plat);
1050 	if (ret)
1051 		return ret;
1052 
1053 	memset(&res, 0, sizeof(res));
1054 	res.addr = pcim_iomap_table(pdev)[0];
1055 
1056 	if (plat->eee_usecs_rate > 0) {
1057 		u32 tx_lpi_usec;
1058 
1059 		tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1060 		writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1061 	}
1062 
1063 	ret = stmmac_config_multi_msi(pdev, plat, &res);
1064 	if (ret) {
1065 		ret = stmmac_config_single_msi(pdev, plat, &res);
1066 		if (ret) {
1067 			dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1068 				__func__);
1069 			goto err_alloc_irq;
1070 		}
1071 	}
1072 
1073 	ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1074 	if (ret) {
1075 		goto err_alloc_irq;
1076 	}
1077 
1078 	return 0;
1079 
1080 err_alloc_irq:
1081 	clk_disable_unprepare(plat->stmmac_clk);
1082 	clk_unregister_fixed_rate(plat->stmmac_clk);
1083 	return ret;
1084 }
1085 
1086 /**
1087  * intel_eth_pci_remove
1088  *
1089  * @pdev: pci device pointer
1090  * Description: this function calls the main to free the net resources
1091  * and releases the PCI resources.
1092  */
1093 static void intel_eth_pci_remove(struct pci_dev *pdev)
1094 {
1095 	struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1096 	struct stmmac_priv *priv = netdev_priv(ndev);
1097 
1098 	stmmac_dvr_remove(&pdev->dev);
1099 
1100 	clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1101 
1102 	pcim_iounmap_regions(pdev, BIT(0));
1103 }
1104 
1105 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1106 {
1107 	struct pci_dev *pdev = to_pci_dev(dev);
1108 	int ret;
1109 
1110 	ret = stmmac_suspend(dev);
1111 	if (ret)
1112 		return ret;
1113 
1114 	ret = pci_save_state(pdev);
1115 	if (ret)
1116 		return ret;
1117 
1118 	pci_wake_from_d3(pdev, true);
1119 	pci_set_power_state(pdev, PCI_D3hot);
1120 	return 0;
1121 }
1122 
1123 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1124 {
1125 	struct pci_dev *pdev = to_pci_dev(dev);
1126 	int ret;
1127 
1128 	pci_restore_state(pdev);
1129 	pci_set_power_state(pdev, PCI_D0);
1130 
1131 	ret = pcim_enable_device(pdev);
1132 	if (ret)
1133 		return ret;
1134 
1135 	pci_set_master(pdev);
1136 
1137 	return stmmac_resume(dev);
1138 }
1139 
1140 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1141 			 intel_eth_pci_resume);
1142 
1143 #define PCI_DEVICE_ID_INTEL_QUARK		0x0937
1144 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G		0x4b30
1145 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G		0x4b31
1146 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5	0x4b32
1147 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1148  * which are named PSE0 and PSE1
1149  */
1150 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G	0x4ba0
1151 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G	0x4ba1
1152 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5	0x4ba2
1153 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G	0x4bb0
1154 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G	0x4bb1
1155 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5	0x4bb2
1156 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0	0x43ac
1157 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1	0x43a2
1158 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G		0xa0ac
1159 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0	0x7aac
1160 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1	0x7aad
1161 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G	0x54ac
1162 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G	0x51ac
1163 
1164 static const struct pci_device_id intel_eth_pci_id_table[] = {
1165 	{ PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1166 	{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1167 	{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1168 	{ PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1169 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1170 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1171 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1172 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1173 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1174 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1175 	{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1176 	{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1177 	{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1178 	{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1179 	{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1180 	{ PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1181 	{ PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1182 	{}
1183 };
1184 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1185 
1186 static struct pci_driver intel_eth_pci_driver = {
1187 	.name = "intel-eth-pci",
1188 	.id_table = intel_eth_pci_id_table,
1189 	.probe = intel_eth_pci_probe,
1190 	.remove = intel_eth_pci_remove,
1191 	.driver         = {
1192 		.pm     = &intel_eth_pm_ops,
1193 	},
1194 };
1195 
1196 module_pci_driver(intel_eth_pci_driver);
1197 
1198 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1199 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1200 MODULE_LICENSE("GPL v2");
1201